Abstract: LED lamp circuitry that emulates an incandescent lamp's behaviour upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.

Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.

Abstract: A propagation-delay-based moisture sensor is disclosed that is capable of providing absolute readings of volumetric water content in a moisture-bearing medium without the need to calibrate the sensor or readings for the conductivity or temperature of the medium. It does so by launching a step transition on a transmission line that is everywhere in contact with the measured medium and that returns the waveform to a high-speed latching comparator wherein the amplitude of the returning waveform is analyzed at precise, programmable time increments. Firmware means in a controlling microprocessor facilitate the successive reconstruction of the significant characteristics of the returning waveform. Analysis of these characteristics by the microprocessor leads to an accurate determination of propagation delay even for severely distorted waveforms. From the propagation delay the moisture content of the medium is derived.

Abstract: A capacitance fuel-gauging system has a capacitive probe and a reference capacitor charged in opposite senses from respective dc voltage sources via switches operated in antiphase. Two further switches alternately discharge the capacitors to a 0 volts rail. The outputs of the probe and the reference capacitor are connected to a summing node, which is connected to an amplifier via a pair of switches operated in antiphase to rectify the output. The amplifier connects to a processor, which controls the relative outputs of the voltage sources and provides an output indicating the value of the probe.

Abstract: An electronics circuit designed for a matrix array of receivers configured to detect multiple external resistors of close values selected from the 100 ohm to 1 Mohm range, and to provide different responses according to the resistance of a resistor connected to a receiver.

Abstract: To accomplish circuit trimming of a packaged IC chip by applying a magnetic field thereon, a magnetically configurable adjuster device is coupled with the packaged IC chip. The magnetically configurable adjuster device includes a Hall element, a signal processor and amplifier device, a decoder, and a configurable adjuster that receives a signal outputted by the packaged IC chip. The configurable adjuster includes a plurality of electrically configurable elements and circuit-trimming members. The Hall element senses and converts the magnetic field into a voltage signal by Hall effect. After amplification, the voltage signal is inputted to the decoder. The decoder decodes the voltage signal into decoded signals that configure the configurable adjuster by means of the configurable elements. With the configurable adjuster hence configured, circuit trimming of the packaged IC chip is achieved via the circuit-trimming members.

Abstract: When exposure is performed with a correction lens of a projection optical system being displaced from a target position exceeding an allowable range, a wafer that has been exposed in this manner is prevented from being sent to the next step. The displacement amount of the correction lens from the target position is monitored during scanning and exposure (S306). When a positional displacement exceeding the allowable range occurs (YES in S308), an error is displayed, and the operation is stopped (S309).

Abstract: A method and system for probing with electrical test signals on an integrated circuit specimen using a scanning electron microscope (SEM) positioned for observing a surface of the specimen exposing electrically conductive terminals on the specimen. A carrier is provided for supporting the specimen in relation to the scanning electron microscope while a controller acquires an image identifying conductive path indicia of the surface of the specimen from the scanning electron microscope. A motorized manipulator remotely controlled by the controller manipulates a plurality of probes positionable on the surface of the specimen for conveying and acquiring electrical test signals inside a vacuum chamber which houses at least a portion of the scanning electron microscope, the carrier, the motorized manipulator and the plurality of probes for analyzing the specimen in a vacuum.

Abstract: The present invention provides a probe comprising a probe body having a body longitudinal axis and a shoulder, and a microstylet mechanically coupled to the shoulder, and a method of manufacturing the same. The microstylet extends from the shoulder and has a microstylet longitudinal axis coincident the body longitudinal axis with the microstylet having a cross section substantially smaller than a cross section of the probe body.

Abstract: A probe burn resistant interface apparatus and method for testing an electronic device use a probe made of a shape memory alloy which upon overheating of the probe during functionality testing of an electronic device contracts the probe to disengage the probe from a contact electrically connected to the electronic device and stop current flow through the probe. Upon cooling of the probe, engagement of the probe with the contact is reestablished. The probe in an example embodiment is a wire which has a core made of a shape memory alloy and a layer of a highly elastic metal, for example copper, on an outer surface of the core to aid return of the probe from its contracted state to its initial state upon cooling an overheated probe for reestablishing electrical connection of the probe with the electronic device being tested.

Abstract: An inspection terminal for accurately measuring a characteristic of an electronic chip component without causing an inner electrode layer constituting an external electrode of the electronic chip component to be exposed to the outside, an inspection method, and an inspection apparatus using the same, involves storing an electronic chip component in a storing portion of a turntable and sucking the electronic chip component by a sucking portion provided in a side guard. A linear edge portion of the inspection terminal is pressed from the bottom so as to abut against the external electrode of the electronic chip component. The linear edge portion is arranged to have an obtuse angle and is brought into contact with the external electrode such that the edge portion lies substantially parallel to the longitudinal direction of the external electrode.

Abstract: Ground bounce measurement circuitry, integrated circuit packaging, memory circuit modules, circuit cards, and systems, and methods to form, assemble, and use them are provided. A circuit combination is disclosed which includes an integrated circuit and measurement circuit, constructed so that each may be supported by a single substrate, or enclosed within a single integrated circuit package. The integrated circuit includes a test domain having a test voltage, and a reference domain having a reference voltage. The measurement circuit is operatively connected to the reference domain and the test domain to measure the ground bounce voltage, which is the difference between the test voltage and the reference voltage. The measured value of the ground bounce voltage can then be acquired by a data acquisition system for later recall, or made immediately available for observation using instrumentation outside of the substrate or integrated circuit package environment.

Abstract: A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit. This circuit is held at this voltage for a given stress period. The application of the DC voltage is equivalent to applying a negative gate bias, and isolates the effects of NBTI degradation from CHC (channel hot carrier) degradation or other degradation that occurs when the circuit has a clocked input.

Abstract: The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals (106a-106n) are input from a test device (105) into the circuit unit (100) to be tested via a connecting unit (104), the circuit unit (100) to be tested is tested by means of the test input signals (106a-106n) in order to obtain corresponding test output signals (107a-107n) which indicate an operability of the circuit unit (100) to be tested, a gate unit (101) is connected to the connecting unit (104) by means of a first test mode switching unit (102) and of a second test mode switching unit (103), in such a manner that the test output signals (107a-107n), after being logically combined in the gate unit (101), are provided as a combined test output signal (109) via a single output line (110), and the combined test output signal (109) is output to the test device (105).

Abstract: A method of using bias-dependent S-parameter measurements as a form of microscopy. The microscopy can be used to resolve the details of the internal charge and electric field structure of a semiconductor device. Like other forms of microscopy, the S-parameter microscopy focuses on pseudo “images” and provides a contrast in the “images”. Essentially, the images are gathered in raw form as S-parameter measurements and extracted as small signal models. The models are used to form charge control maps, through a selective method analogous to focusing. Focusing is provided by an algorithm for the unique determination of small signal parameters with contrasts provided by utilizing measured bias dependent activity to discriminate boundaries between the electrical charge and fields. As such, the system is able to accurately forecast semiconductor performance.

Abstract: A driver circuit includes a driver and a control device that controls the driver. The control device modifies the power of the driver based on the waveform of the signal (DAT_OUT) to be driven by the driver and/or based on the waveform of the signal output by the driver. Such a driver circuit makes it possible to reduce the energy consumption of the driver and/or the interference caused by the driver to a minimum.

Abstract: A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.

Abstract: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer.

Abstract: An apparatus and associated method are provided for combining a dynamic logic gate and level shifting circuitry in an improved circuit. The combined dynamic logic gate and level shifting circuit of the invention includes a pair of logic gates each having an output and configured such that only one output of the pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive the outputs of the logic gates, wherein a pair of inputs which transition in a first voltage range control the logic gates to produce an output which transitions in a second voltage range in response to the switching of the output switching circuits.

Abstract: Logic is connected to the outputs of a dynamic logic gate to detect illegal or invalid states. The output of this detection logic sets a state catcher. The output of the state catcher is readable by scan logic so that the occurrence or non-occurrence of the invalid state may be read by test hardware.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A static output signal is generated using a static storage element (104) and transmitted to a NDL gate (110) over a transmission path (112) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.

Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.

Abstract: Input stage having increased input signal noise margin and method for generating an output signal having a predetermined logic level based on the voltage level of an input signal. The input stage includes an input buffer generating an output signal having a logic level based on the voltage of the input signal relative to the voltage of the reference voltage signal. A voltage generator provides a variable output voltage signal that is used as the reference voltage by the input buffer. The voltage of the output voltage signal provided by the voltage generator is dependent on the logic value of the output signal of the input buffer. In this manner, the reference voltage applied to the input buffer can be adjusted based on the logic level of the outputs signal in order to provide increased input signal noise margin.

Abstract: The ESD (Equivalent Shottky Diode, or Emanuil Shvarts Diode) includes a transistor and a sensing circuit, which senses a voltage difference across the ESD. A driving circuit controls the operation of the transistor based on the sensed difference.

Abstract: To avoid that IGBTs are destroyed by receiving overvoltages while an overcurrent flows through series-connected IGBTs of a semiconductor power converting apparatus, a gate driver for controlling a gate voltage of the MOS control semiconductor owns a power supply line having a higher potential than such a gate potential when the MOS control semiconductor is brought into a steady ON state, and when a potential difference between the power supply line and an emitter of the MOS control semiconductor is constant, and also a collector voltage of the MOS control semiconductor exceeds a predetermined value under ON state of the MOS control semiconductor, the power source line of the gate driver supplies a current from the power source line to the gate of the MOS control semiconductor so as to increase the gate voltage of the MOS control semiconductor.

Abstract: The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: An output driver circuit includes a delay device disposed between a signal input and a driver device. The input signal to the driver device can be delayed by a predetermined value with the delay device. The signal amplitude of the output signal from the driver device is compared, in a comparison device, with the signal amplitude of a reference signal at a predetermined time. The time delay for the input signal to the driver device is then set on the basis of the comparison result. A method for adjusting a driver device is also provided.

Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.

Abstract: A power-on control circuit for an integrated circuit of the type having plural voltage source. The circuit is powered on sequentially, thereby preventing bus contention. The power-on control circuit includes a power-on detection for generating an enabling signal and disabling signal to control output buffer. When the high voltage source is powered on and the low voltage is not, the output buffer is at a high impedance state to prevent bus contention. When the low voltage is powered on after the high voltage is powered on, the output buffer is at a normal state.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV′) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

Abstract: A current-steering charge pump circuit and method for switch timing that reduces the amount of switching transients on an output current pulse produced by the charge pump. The charge pump circuit is especially adapted to control a voltage-controlled oscillator (VCO) in a phase-locked loop circuit.

Abstract: A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: An output buffer circuit for reducing a variation of the slew rate due to a variation of process, voltage and temperature (PVT) and the load capacitance of an output terminal, and semiconductor device including the same, include a first slew rate control circuit for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and a second slew rate control circuit for pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal. A pull-up driver is provided for pulling up an output terminal in response to the pull-up signal, and a pull-down driver is provided for pulling down the output terminal in response to the pull-down signal. The first and second slew rate control circuits are controlled by bias voltages that are provided by a phase locked loop circuit and compensate for changes in PVT.

Abstract: A generating a digital wave apparatus is provided. The period of a basic clock signal is divided into a plurality of time points, and the level of the highly accurate digital wave is toggled at these time points. The apparatus comprises a delay phase lock loop, for generating a plurality of delayed clock signals according to the basic clock signal; a first multiplexer and a second multiplexer for outputting one of the delayed clock signals according to a first select signal and a second select signal, respectively; a first edge-triggered flip-flop and a second edge-triggered flip-flop for receiving the output signals of the first multiplexer and the second multiplexer respectively; and a logic gate for outputting the digital wave according to the outputs of the first and the second edge-triggered flip-flops. The digital wave is toggled according to the first select signal, and further toggled according to the second select signal.

Abstract: An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

Abstract: An interface circuit, according to the present invention includes a frequency divider which divides a frequency of a base clock to provide frequency-divided clock signals; a first address register which stores an address signal at a timing in which the frequency-divided clock signal is turned to high; a second address register which stores the address signal at a timing in which the clock signal is turned to low; a first data register which stores a data signal at a timing in which the clock signal is turned to high; and a second data register which stores the data signal at a timing in which the clock signal is turned to low. The data signals stored in the first and second data registers are selectively outputted.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT−) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.

Abstract: A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.