Patents Issued in March 6, 2003
  • Publication number: 20030045064
    Abstract: A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epitaxial layer (3). An N-type bottom layer (7) containing an N-type impurity is disposed so as to make contact with a bottom surface of the P-type well layer (6). A P-type well layer (2) is disposed in such a thickness as to make contact with the N-type bottom layer (7), so that the N-type bottom layer (7) and P-type well layer (2) form a PN junction. Further, in the main surface of the epitaxial layer (3), an N-type well layer (4) containing an N-type impurity and a P-type well layer (5) containing a P-type impurity are selectively disposed so as to sandwich therebetween the P-type well layer (6).
    Type: Application
    Filed: July 30, 2002
    Publication date: March 6, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tatsuya Kunikiyo, Takeshi Hamamoto, Yoshinori Tanaka
  • Publication number: 20030045065
    Abstract: An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.
    Type: Application
    Filed: September 27, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Hiroyuki Maruyama, Makoto Yoshida
  • Publication number: 20030045066
    Abstract: A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave surface. The combination etching includes an isotropic etching and subsequent wet etching. The concave surface increases the distance between the external base for the intrinsic base and the emitter to thereby increase the emitter-base breakdown voltage.
    Type: Application
    Filed: August 26, 2002
    Publication date: March 6, 2003
    Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.
    Inventor: Tomohiro Igarashi
  • Publication number: 20030045067
    Abstract: In a semiconductor integrated circuit device according to the present invention, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Therefore, oxygen permeated into the lower electrode at the time of a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, the oxygen does not reach the surface of the plug, so that such a disadvantage can be prevented that the oxygen permeated through the lower electrode causes the oxidation on the surface of the silicon plug below the lower electrode to form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Hiroshi Sakuma
  • Publication number: 20030045068
    Abstract: The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with a material with an increased dielectric constant. An insulation region is formed in the upper wall region of the trench after the first electrode region or the second electrode region has been formed, by selective and local oxidation.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 6, 2003
    Inventors: Martin Gutsche, Thomas Hecht, Matthias Leonhardt, Uwe Schroder, Harald Seidl
  • Publication number: 20030045069
    Abstract: A capacitor including a first plate of conductive material that is formed in a predetermined shape. A layer of dielectric material is formed on at least a portion of the first plate and substantially conforms to the predetermined shape of the first plate. A second plate of conductive material is formed over the layer of dielectric material.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Brent Gilgen, Belford T. Coursey
  • Publication number: 20030045070
    Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
    Type: Application
    Filed: March 22, 2002
    Publication date: March 6, 2003
    Inventors: Chul-Sung Kim, Si-Young Choi, Jung-Woo Park, Jong-Ryol Ryu, Byeong-Chan Lee
  • Publication number: 20030045071
    Abstract: A method for fabricating a semiconductor memory device is provided to increase the etch selectivity of photoresist by changing the matter properties thereof in forming a trench isolation region. The method includes the steps of: depositing first and second insulating layers on a semiconductor substrate where a shallow trench isolation (STI) region and a deep trench isolation (DTI) region are defined; forming the STI region by selectively etching the second and first insulating layers and the semiconductor substrate; forming a photoresist to cover the STI region and curing the surface of the photoresist; and forming the DTI region by using the cured photoresist and the second insulating layer as a mask.
    Type: Application
    Filed: March 18, 2002
    Publication date: March 6, 2003
    Inventors: Ji Suk Hong, Chul Chan Choi
  • Publication number: 20030045072
    Abstract: Microelectronic device assemblies are provided with reduced-thickness dies. In certain methods of the invention, a die is connected to a mounting surface of a support and the back surface of the die is ground to reduce the die thickness. In certain embodiments, a portion of the mounting surface of the substrate remains exposed, permitting other devices to be electrically coupled directly to the substrate. In other embodiments, a second die is electrically coupled to the ground back surface of the first die via an intermediate layer, enabling a reduced profile stacked die assembly without requiring direct connection to the support.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventor: Tongbi Jiang
  • Publication number: 20030045073
    Abstract: A novel process for lapping a wafer is disclosed, which includes the steps of relieving adhesive stress of an ultraviolet tap attached to a first side of a wafer by irradiation of ultraviolet light, maintaining a lapping jig at a usable temperature of the ultraviolet tape to cause binder applied to the lapping jig to be melted, bonding the first side of the wafer to the lapping jig, and lapping the wafer. Thus, the present invention can provide a process capable of preventing damage to a wafer owing to deformation of an ultraviolet tape. The invention can also simplify an entire process to shorten the time required to complete the process and can minimize damage to a wafer by carrying out a lapping process using an ultraviolet tape as well as a grinding process capable of increasing etching amount of a wafer.
    Type: Application
    Filed: December 10, 2001
    Publication date: March 6, 2003
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong-Goo Yoon, Ju-Young Park
  • Publication number: 20030045074
    Abstract: A method of forming a doped polycrystalline silicon gate in a Metal Oxide Semiconductor (MOS) device. The method includes forming first an insulation layer on a top surface of a crystalline silicon substrate. Next, an amorphous silicon layer is formed on top of and in contact with the insulation layer and then a dopant is introduced in a top surface layer of the amorphous silicon layer. The top surface of the amorphous silicon layer is irradiated with a laser beam and the heat of the radiation causes the top surface layer to melt and initiates explosive recrystallization (XRC) of the amorphous silicon layer. The XRC process transforms the amorphous silicon layer into a polycrystalline silicon gate and distributes the dopant homogeneously throughout the polycrystalline gate.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: Cindy Seibel, Somit Talwar
  • Publication number: 20030045075
    Abstract: A method of selective epitaxial growth for a semiconductor device is disclosed. By employing a hydrogen gas as a selectivity promoting gas in addition to a chlorine gas conventionally used, the method can guarantee the selectivity of epitaxial growth and further increase the growth rate of an epitaxial layer. The method begins with loading a semiconductor substrate into a reaction chamber. The substrate has a mask layer, which is selectively formed thereon to define a first portion exposed beyond the mask layer and a second portion covered by the mask layer. Next, a source gas is supplied into the reaction chamber so that the source gas is adsorbed on the first portion and thus the epitaxial layer is selectively formed on the first portion. Then, the selectivity promoting gas including the H2 gas into the reaction chamber, whereby any nucleus of semiconductor material is removed from the mask layer.
    Type: Application
    Filed: December 28, 2001
    Publication date: March 6, 2003
    Inventors: Sung Jae Joo, Chang Woo Ryoo
  • Publication number: 20030045076
    Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.
    Type: Application
    Filed: May 21, 2002
    Publication date: March 6, 2003
    Applicant: UMC Japan
    Inventor: Yukinobu Hayashida
  • Publication number: 20030045077
    Abstract: After introducing an impurity into a polysilicon semiconductor film formed on a substrate, heat treatment is carried out under the conditions not to activate the implanted impurity. The thickness of the polysilicon film and the sheet resistance after introducing the impurity are measured, and the conditions of forming the semiconductor film are adjusted so that the product of the thickness and the sheet resistance is always constant.
    Type: Application
    Filed: February 11, 2002
    Publication date: March 6, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuki Yoshihisa
  • Publication number: 20030045078
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20030045079
    Abstract: Disclosed is a method for manufacturing a mask ROM of flat cell structure.
    Type: Application
    Filed: July 24, 2002
    Publication date: March 6, 2003
    Inventor: Chang Hun Han
  • Publication number: 20030045080
    Abstract: A MOSFET structure with high-k gate dielectrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material deposition and gate formation.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 6, 2003
    Inventors: Mark R. Visokay, Antonio L.P. Rotondaro, Luigi Colombo
  • Publication number: 20030045081
    Abstract: A stacked silicon gate structure for a MOSFET may be formed in a CVD chamber. The stacked structure includes a first polycrystalline silicon layer, a microcrystalline layer, and second polycrystalline silicon layer. The microcrystalline layer has a randomly orientated crystal structure with a smaller average crystal grain size than the first and second polycrystalline silicon layers. The microcrystalline layer is capable of maintaining its original crystal structure even while undergoing high temperature process substantially without further recrystallization. This allows the microcrystalline layer to suppress migration of dopants in the second polycrystalline silicon layer into the first polycrystalline silicon layer and thereby prevent a shift in the threshold voltage that would otherwise result from such dopant penetration.
    Type: Application
    Filed: June 25, 2002
    Publication date: March 6, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Kuan-Ting Lin, Shih-Che Lin
  • Publication number: 20030045082
    Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
    Type: Application
    Filed: February 20, 2002
    Publication date: March 6, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Jerome M. Eldridge, Kie Y. Ahn, Leonard Forbes
  • Publication number: 20030045083
    Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 6, 2003
    Applicant: Intel Corporation
    Inventors: Steven Towle, John Tang, John S. Cuendet, Henning Braunisch, Thomas S. Dory
  • Publication number: 20030045084
    Abstract: A method of production of a semiconductor module comprised of a semiconductor chip, external connection terminal pads for bonding with solder balls or other external connection terminals, wires electrically connecting the same, and a sealing resin layer sealing the semiconductor chip, external connection terminal pds, and wires, where surfaces of the external connection terminal pads are exposed at bottoms of recesses formed in the sealing resin layer, comprising sealing by a resin external connection terminal pads and soluble metal layers formed at surfaces of the metal substrate by electroplating to form a sealing resin layer at that one surface, then etching away the metal substrate and soluble metal layers to thereby form in the resin sealing layer recesses exposing the external connection terminal pads at their bottoms by a single etching process without requiring special etching stop control.
    Type: Application
    Filed: August 13, 2002
    Publication date: March 6, 2003
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Youichi Kazama, Keiichi Masaki
  • Publication number: 20030045085
    Abstract: The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.
    Type: Application
    Filed: March 1, 2002
    Publication date: March 6, 2003
    Applicant: Fujitsu Limited
    Inventors: Osamu Taniguchi, Tomoko Miyashita, Yasuo Yamagishi, Koji Omote, Yoshihiko Imanaka
  • Publication number: 20030045086
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Application
    Filed: September 4, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hiruzu Yamaguchi, Nobuo Owada
  • Publication number: 20030045087
    Abstract: A conductive layer which is electrically connected to a semiconductor substrate is formed on an insulative layer on the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate in a portion corresponding to a conductive path. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed to the conductive layer, thereby forming the conductive path. After the formation of the conductive path, a heating process is performed to the substrate or the conductive path in order to disconnect the electrical connection of the through portion and the substrate portion by a reaction between the through portion and the semiconductor substrate portion which is in contact therewith.
    Type: Application
    Filed: March 25, 2002
    Publication date: March 6, 2003
    Inventors: Toru Yoshie, Kazuhide Abe, Yusuke Harada
  • Publication number: 20030045088
    Abstract: Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.
    Type: Application
    Filed: July 16, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Toshinori Imai, Tsuyoshi Fujiwara, Tomohiro Shiraishi, Hiroshi Ashihara, Masaaki Yoshida
  • Publication number: 20030045089
    Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.
    Type: Application
    Filed: August 13, 2002
    Publication date: March 6, 2003
    Applicant: Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AG
    Inventors: Guido Wenski, Thomas Altmann, Ernst Feuchtinger, Willibald Bernwinkler, Wolfgang Winkler, Gerhard Heier
  • Publication number: 20030045090
    Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate, and a wiring line groove is formed in the insulating film. Then, a conductive film is formed to fill the wiring line groove and to cover the insulating film. The conductive film is removed using a CMP polishing method until the insulating film is exposed, to complete a wiring line. Subsequently, a front side of the semiconductor substrate is rinsed on which the wiring line is formed, and then a back side of the semiconductor substrate is rinsed while supplying to the front side of the semiconductor substrate, a protection solution for forming a protection film in an exposed surface of the wiring line.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 6, 2003
    Applicant: NEC Corporation
    Inventors: Yasuaki Tsuchiya, Akira Kubo
  • Publication number: 20030045091
    Abstract: A method of forming contact for a semiconductor device is disclosed.
    Type: Application
    Filed: December 28, 2001
    Publication date: March 6, 2003
    Inventors: In Cheol Ryu, Sung Gon Jin
  • Publication number: 20030045092
    Abstract: A method of fabricating a semiconductor device having the steps of forming an insulating layer on a silicon substrate; forming a contact hole in the insulating layer so that a portion of the silicon substrate is exposed in the contact hole; performing an interface treatment process to the exposed portion of the silicon substrate, wherein the interface treatment process includes at least a dry cleaning and a hydrogen heat treatment; and forming a selective silicon plug including single crystalline and polycrystalline silicon structures on the exposed portion of the silicon substrate.
    Type: Application
    Filed: December 28, 2001
    Publication date: March 6, 2003
    Inventor: Dong Suk Shin
  • Publication number: 20030045093
    Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 6, 2003
    Applicant: Micron Technology, Inc.
    Inventors: John H. Givens, Russell C. Zahorik, Brenda D. Kraus
  • Publication number: 20030045094
    Abstract: A semiconductor manufacturing method and a semiconductor manufacturing apparatus are capable of manufacturing semiconductor devices with excellent step coverage and high throughput and at low cost. A substrate (1) is arranged in a thermal CVD apparatus which includes a reaction chamber (5), a gas supply port (7) through which ruthenium precursor gases for depositing ruthenium films or ruthenium oxide films on a substrate (1) are supplied to the reaction chamber (5), and a gas exhaust port 8 through which the precursor gases are exhausted from the reaction chamber (5). A first ruthenium precursor gas is caused to flow from the gas supply port (7) toward the substrate (1) so that a first ruthenium film or a first ruthenium oxide film is deposited on the substrate (1).
    Type: Application
    Filed: August 27, 2002
    Publication date: March 6, 2003
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hideharu Itatani, Atsushi Sano
  • Publication number: 20030045095
    Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.
    Type: Application
    Filed: June 12, 2001
    Publication date: March 6, 2003
    Applicant: Semitool, Inc.
    Inventors: Thomas L. Ritzdorf, Lyndon W. Graham, Robert W. Batz
  • Publication number: 20030045096
    Abstract: There are provided the steps of exposing a surface of a copper (Cu) wiring layer formed over a semiconductor substrate to a plasma of a gas selected from the group consisting of an ammonia gas, a mixed gas of nitrogen and hydrogen, a CF4 gas, a C2F6 gas and a NF3 gas, exposing the surface of the copper (Cu) wiring layer to an atmosphere or a plasma of a gas selected from the group consisting of an ammonia gas, an ethylenediamine gas, a &bgr;-diketone gas, a mixed gas consisting of the ammonia gas and a hydrocarbon gas (CxHy), and a mixed gas consisting of a nitrogen gas and the hydrocarbon gas (CxHy), and forming a Cu diffusion preventing insulating film on the copper (Cu) wiring layer.
    Type: Application
    Filed: July 30, 2002
    Publication date: March 6, 2003
    Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Shoji Ohgawara, Kazuo Maeda
  • Publication number: 20030045097
    Abstract: The invention relates to optical fluoride crystals, and particularly to optical fluoride crystals such as calcium fluoride, which have high transmission levels to below 200 nm light, such as produced by excimer lasers. In particular the invention relates to making optical fluoride crystals with improved transmission surfaces. The invention relates to the elimination of mid-spatial frequency roughness 1-1000 &mgr;m spatial wavelengths and high-spatial frequency <1 &mgr;m spatial wavelengths from optical fluoride crystal surfaces. The removal of the mid-spatial frequency 1-1000 &mgr;m spatial wavelengths and high-spatial frequency <1 &mgr;m spatial wavelengths from the optical fluoride crystal surfaces provides improved transmission at below 200 nm optical lithography wavelengths such as 193 nm and 157 nm.
    Type: Application
    Filed: July 23, 2001
    Publication date: March 6, 2003
    Inventors: Rebecca S. Retherford, Robert Sabia, Vincent P. Sokira
  • Publication number: 20030045098
    Abstract: A method of a single wafer wet/dry cleaning apparatus comprising:
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Steven Verhaverbeke, J. Kelly Truman, Christopher T. Lane
  • Publication number: 20030045099
    Abstract: A method of forming a self-aligned contact hole suitable for a semiconductor substrate having a pair of gate electrodes. First, a nitride etching stop layer is formed over the gate electrodes and the semiconductor substrate. Then, an oxide insulating layer is formed on the nitride etching stop layer, Next, the oxide insulating layer is plasma-etched by an etching gas containing C5F8 and CHF3 or C4F6 and CHF3 so as to form a self-aligned contact hole between the pair of gate electrode.
    Type: Application
    Filed: December 13, 2001
    Publication date: March 6, 2003
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Chi Sun, Tse-Yao Huang
  • Publication number: 20030045100
    Abstract: A method and apparatus for providing in-situ monitoring of the removal of materials in localized regions on a semiconductor wafer or substrate during chemical mechanical polishing (CMP) is provided. In particular, the method and apparatus of the present invention provides for detecting the differences in reflectance between the different materials within certain localized regions or zones on the surface of the wafer. The differences in reflectance are used to indicate the rate or progression of material removal in each of the certain localized zones.
    Type: Application
    Filed: December 21, 2001
    Publication date: March 6, 2003
    Applicant: Massachusetts Institute of Technology
    Inventors: Nanaji Saka, Jamie Nam, Hilario L. Oh
  • Publication number: 20030045101
    Abstract: Two-step process to improve low-K dielectric etch uniformity, apparatus to perform the method, and semiconductor devices formed in accordance with the method. In a first etching step, an insulating hot edge ring is provided. When the photoresist clearing signal is observed using end-point software, the insulating cover is moved aside to expose the conductive edge ring for the remainder of the etch. One aspect of this invention contemplates an insulator cover over a conductive edge ring at the start of wafer etching, which cover is removed after end-pint detection. The present invention contemplates a number of physical configurations whereby the insulator ring is urged into, and away from, its masking of the conductive edge ring.
    Type: Application
    Filed: January 30, 2002
    Publication date: March 6, 2003
    Inventors: Janet M. Flanner, Susan Ellingboe, Christine Janowiak, John Lang, Ian J. Morey
  • Publication number: 20030045102
    Abstract: Provided is a method of manufacturing compound single crystals by epitaxially growing a compound single crystal layer differing from the substrate in which the planar defects generated in the crystal that is epitaxially grown are reduced. The method of manufacturing compound single crystals in which a compound single crystalline layer differing from a compound single crystalline substrate is epitaxially grown on the surface of said substrate. Plural undulations extending in a single direction are present on at least a portion of the surface of said substrate, and in that said undulations are provided in such a manner that as said compound single crystalline layer grows, the defects that grow meet each other.
    Type: Application
    Filed: August 26, 2002
    Publication date: March 6, 2003
    Applicant: HOYA CORPORATION
    Inventors: Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara
  • Publication number: 20030045103
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x≦0.011 and x≧450 &mgr;m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H≦70×10−4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos−1(1-HCZ), where C (cm−1) is the proportionality constant when the radius of curvature of the substrate &rgr; (cm) is expressed as 1/&rgr;=CZ.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 6, 2003
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Publication number: 20030045104
    Abstract: The present invention controls a temperature of a processing liquid to be in within an allowable processing temperature range, whereby the processing efficiency and throughputs can be improved, deterioration of the processing liquid is prevented, and the life of the processing liquid can be extended.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 6, 2003
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Sadayuki Fujishima
  • Publication number: 20030045105
    Abstract: A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 6, 2003
    Inventors: Klaus Feldner, Werner Graf, Albrecht Kieslich, Hermann Sachse
  • Publication number: 20030045106
    Abstract: A chemical mechanical polishing pad and a system and a method for using such a pad are described. The polishing pad includes pockets of continuous porosity, each of the pockets being separated from the other pockets by a non-porous matrix. The non-porous matrix may include a network of trenches, or may have pores which have been filled with a material. The material may include a polymer resin. A system for polishing a wafer includes the polishing pad mounted on a platen. A drive assembly creates relative rotation between the wafer and the polishing pad through a drive shaft. The drive shaft may be connected to the platen or it may be connected to a wafer holder which holds the wafer. Alternatively, one drive shaft may be connected to the platen and another drive shaft may be connected to the wafer holder, and a pair of drive assemblies drive the drive shafts.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventor: Steve Kramer
  • Publication number: 20030045107
    Abstract: A small footprint, integrated and automated semiconductor wafer processing system for planarizing semiconductor wafers. That processing system includes a wafer load station, at least one CMP polishing system, and at least one cleaning system. Also included is at least one wafer unload station and a robotic system. The robotic system, which includes from two to six robotic movers, moves semiconductor wafers through the semiconductor wafer processing system. The semiconductor wafer processing system can also include a buffer system for temporarily holding semiconductor wafers. The buffer system, the robotic system, the cleaning system, the wafer load station, and/or the wafer unload station in some applications are capable of Z-axis motion. CMP polishing systems and cleaning systems can be vertically or linearly stacked.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventor: In Kwon Jeong
  • Publication number: 20030045108
    Abstract: A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.
    Type: Application
    Filed: May 21, 2002
    Publication date: March 6, 2003
    Inventors: Tzu-Ching Tsai, Ping Hsu
  • Publication number: 20030045109
    Abstract: A method for creating a lateral overflow drain, anti-blooming structure in a charge coupled device, the method includes the steps of providing a substrate of a first conductivity type for the charge coupled device; providing a layer of oxide abutting the substrate; providing a layer of nitride abutting the oxide; providing a hard mask abutting the nitride with an etched away portion having a dimension which substantially equals a combined dimension of heavily doped first and second conductivity type subsequently implanted regions in the substrate; placing photoresist in a portion of the etched away portion which remaining etched away portion includes a dimension substantially equal to the first conductivity type subsequently implanted region in the substrate; implanting ions of the first conductivity type through the remaining etched away portion and into the substrate for creating a channel stop; removing the photoresist and placing a second photoresist layer in a portion of the etched away portion wherein a
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Applicant: Eastman Kodak Company
    Inventor: Eric G. Stevens
  • Publication number: 20030045110
    Abstract: A lithography method for plating sub-100 nm narrow trenches, including providing a thin undercoat dissolution layer intermediate a seed layer and a resist layer, wherein the undercoat dissolution layer is relatively completely cleared off the seed layer by the developer solution such that the sides of the narrow trench will be generally vertical, particularly at the base of the narrow trench, thus facilitating plating the narrow trench with a high magnetic moment material
    Type: Application
    Filed: March 28, 2002
    Publication date: March 6, 2003
    Inventors: Xiaomin Yang, Andrew Robert Eckert
  • Publication number: 20030045111
    Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.
    Type: Application
    Filed: October 22, 2002
    Publication date: March 6, 2003
    Inventors: Mark E. Jost, Chris W. Hill
  • Publication number: 20030045112
    Abstract: The present invention is an improved method for etching away portions of epitaxial layers in a multi-layer wafer to form a semiconductor. The method includes implanting ions throughout select portions of an epitaxial layer that are to be removed through etching. The ion implantation weakens the molecular structure of the implanted portions of the epitaxial layer and increases the vulnerability of the implanted portions to select liquid etchants or etching solutions. As such, the etching process has less impact on those portions of the epitaxial layer that were not subjected to ion implantation.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Raymond Jeffrey Vass, Scott I. Hill
  • Publication number: 20030045113
    Abstract: A fabrication method of a semiconductor integrated circuit device using a gas mixture comprising SF6, oxygen and nitrogen as a plasma source gas upon dry etching of a W film, a WNx film and a polycrystal silicon film as a gate electrode material by using a silicon nitride film as a mask, the fabrication method capable of ensuring the shape of the gate electrode upon etching fabrication of a gate electrode of a polymetal structure and improving the etching selectivity to the etching stopper film comprising silicon nitride.
    Type: Application
    Filed: July 19, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Hiroshi Kawakami, Tadashi Umezawa, Kazutami Tago