Abstract: A system for investigating subterranean strata. An electromagnetic field is applied using a dipole antenna transmitter and this is detected using a dipole antenna receiver. Phase information is extracted from a refracted wave response and used to identify the presence and/or nature of a subterranean reservoir.

Abstract: A probe serving for detecting the structure of a dielectric medium. The probe includes at least one transmitter/receiver antenna located near a dielectric boundary surface that defines a dielectric medium, and a signal processor for receiving signals from the antenna and generating data representative of the structure of the dielectric medium. Between the antenna and the face is inserted a cushion of a material having a dielectric number higher than that of the air. In one embodiment, the probe is adapted to inspect if there is a void in the soil around a dielectric pipe, for example a sewer pipe. In this case, the probe is guided inside the pipe with the antennas located on a shaft mounted on the probe with the same axis as the axis of the pipe. Due to the presence of the cushion, an optimally good connection between the antennas and the face defining the dielectric medium is obtained.

Abstract: A coil-on plug testing apparatus for detecting a weak field output by a shielded coil-on plug ignition and generating an output signal representing an ignition signal includes a capacitive sensor attachable to a coil-on-plug device for detecting an electric field generated by the shielded coil-on plug device during a firing event and generating and outputting a voltage in response thereto. A signal processing circuit electrically coupled to the capacitive sensor is configured to generate an output signal in response to variations in the voltage output by the capacitive sensor in response to a detected electric field. The signal processing circuit comprises an amplifier configured to amplify an output voltage of the capacitive sensor.

Abstract: A battery voltage detection device includes: a plurality of (N+1) voltage detection terminals connected to the plurality of N battery blocks; a first plurality of switches each having an inter-terminal capacitance, the plurality of switches being connected to the respective voltage detection terminals connected to the battery blocks; a second switch having an inter-terminal capacitance, to which the first plurality of switches are collectively connected, the first plurality of switches being connected to odd-numbered voltage detection terminals; a third switch having an inter-terminal capacitance, to which the first plurality of switches are collectively connected; a pair of fourth switches connected in series to the second switch and the third switch; and a capacitor provided between the connection point of the second switch and one of the fourth switches, and the connection point of the third switch and the other of the fourth switches.

Abstract: A method for grouping unit cells of a similar impedance spectrum uses pattern matching technology to optimize the performance of a battery pack made of primary or secondary batteries as the unit cells connected in series, in parallel or in combination of them. To make an optimal battery pack with unit cells of a different internal characteristic, the method includes measuring the impedance spectrum of the individual unit cell in a wide frequency region at the same temperature and in the same state of charge (SOC), digitizing the difference in impedance spectrum among the unit cells into a relative value using the pattern matching technology, and selecting unit cells of a most similar impedance spectrum (i.e., a smallest relative difference in impedance spectrum) to make a battery pack.

Abstract: Method of determining the state of charge soc of a battery, in particular a starting battery of a motor vehicle; the state of charge being calculated, in a first operating range, on the basis of a model calculation in which a measured and a calculated battery voltage UBatt, UBatt′ are balanced, using feedback.

Abstract: The present invention provides a device for in-situ measurement and recording of various environmental parameters in a semiconductor fabrication process. The device comprises sensors for detecting the parameters and converting them to sensor outputs; and a data logger coupled to the sensors for receiving the sensor outputs and logging them in a file. The device may also comprise an analog to digital converter to convert the sensor outputs to digital data and a communication module to communicate the digital data with other devices. When applied to reticles used in a semiconductor fabrication process comprising a plurality of stages, the device may be used to monitor electrostatic field and electrostatic discharge activities on and around the reticle, convert the monitored parameters into data, and log the data along with a timestamp and an identification of each individual stage.

Abstract: The invention relates to a writing pen with a liquid crystal screen displaying the tested alcohol concentration value, and its architecture includes a lower barrel, an upper barrel, and a sensor device. The sensor device has a circuit board, wherein a sensor, a liquid crystal screen, and a processing unit are installed on and electrically connected to the circuit board. The circuit board receives the alcohol content in the user's exhaled breath and converts it so that a precise value can be displayed on the liquid crystal screen. Hence, a writing pen that can be readily carried and has a liquid crystal screen displaying the tested alcohol concentration value is completed.

Abstract: Analyzer Sensor. The present invention is an apparatus for detecting signal waveforms on a pair of conductors. The apparatus includes capacitive couplers connected to termination impedance and adapted for placement adjacent to the conductors to capacitively couple the signals of the conductors to the associated termination impedance. The invention further includes a first and second buffer amplifier responsive, respectively, to the signals at the termination impedances, for providing at a first and second output thereof, respectively, an amplified difference of the signals. Furthermore, the invention includes a utility module having a battery source connected to the buffer amplifiers by a line for providing power to the buffer amplifiers at a location distant from the buffer amplifiers.

Abstract: A system for determining the locations of faults on a cable by determining the positions of transformers is described. The locations of transformers can be determined in a reflected signal trace resulting from a voltage pulse coupled into the cable. The reflected pulse signals on the reflected signal trace from the transformers follow a predictable attenuation pattern. Therefore, an algorithm executing on a computer system can be utilized to determine the location of transformers in a reflected signal trace. A fault can then be located by, for example, applying a high voltage to the cable and measuring a new reflected signal trace which shows reflection from the fault. The fault, then, can be located relative to neighboring transformers.

Abstract: The invention concerns an apparatus for inspecting and calculating the residual strength of an aramid fiber cable driving an elevator to determine when such cable is in need of replacement. The apparatus includes a transmitter for introducing an acoustic wave that will travel along the aramid fiber cable and a receiver for receiving the acoustic wave after its has traversed a designated section of the cable. The transmitter and receiver provide signals indicating the times the wave was sent by the transmitter and thereafter received by the receiver. From these signals, a program in the system calculates the wave velocity and the modulus, and the residual strength of the aramid cable.

Abstract: This invention discloses an apparatus and method of determining the temperature of the core of an inductive coil sensor so that the effective inductance of the coil sensor can be temperature compensated to thereby provide an accurate measure of the level of fuel in a tank. The method comprises energizing the sensor with a prescribed voltage, de-energizing the sensor, measuring the resultant voltage across the sensor, and determining the core temperature from the measured resultant voltage across the sensor.

Abstract: A primary, normally open, DC monitoring circuit with a circuit continuity test device is disclosed which will also test one or more additional sensors connected to the circuit. The sensing of lack of continuity or of a fault condition detected by an additional sensor governs the status of a single indicator, generally a warning light.

Abstract: In a signal reproduction block of a DVD reproduction apparatus, an output signal line for outputting a characteristic information signal representing a characteristic of a filter incorporated in the signal reproduction block to the outside is additionally provided on the output side of an A/D converter. In this way, it is possible to prevent an analog data signal from deteriorating during a data signal reproduction process due to a parasitic effect of the output signal line. Moreover, the filter characteristic information signal is output through the output signal line after it is converted to a digital signal by the A/D converter, thereby avoiding the deterioration the characteristic information signal and thus improving the measurement precision.

Abstract: A method for detecting displacements of a micro-electromechanical sensor including a fixed body and a mobile mass, and forming a first sensing capacitor and a second sensing capacitor having a common capacitance at rest. The first and second sensing capacitors being connected to a first input terminal and, respectively, to a first output terminal and to a second output terminal of the sensing circuit. The method includes the steps of closing a first negative-feedback loop, which is formed by the first and second sensing capacitors and by a differential amplifier, feeding an input of the differential amplifier with a staircase sensing voltage through driving capacitors so as to produce variations of an electrical driving quantity which are inversely proportional to the common sensing capacitance, and driving the sensor with the electrical driving quantity.

Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Abstract: A radiation detector includes: a scintillator which produces UV photons in response to receiving radiation from a radiation producing source; and, a wide bandgap semiconductor device sensitive to the UV photons produced by the scintillator. The semiconductor device produces an electric signal as a function of the amount of UV photons incident thereon. Preferably, the electric signal is then measure, recorded and/or otherwise analyzed.

Abstract: An electronic sensor device has at least one sensor component, which bears on a bearing base of a rewiring structure. Contact areas of the sensor component are electrically conductively connected to contact pads of the rewiring structure. External contact areas of the rewiring structure are led outward from a housing for the electrical contact-connection of the electronic sensor device. A method is also described for producing the electronic sensor device.

Abstract: A probe unit to be fixed to a probe device for testing functions of a test body. The probe unit includes: a substrate; probe pins formed on the substrate by lithography, the probe pins having distal ends protruded from the substrate and being made in contact with electrodes of the test body; and a positioning member formed on the substrate by lithography at a predetermined position relative to the probe pins, the positioning means abutting upon a member for positioning the substrate relative to the probe device.

Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.

Abstract: A two-wire sensor (S) is connected to a pole via a first connection line (V1) in which a voltage longitudinal controller (SR) and a current-limiting resistor (R1) are positioned, and via a second connection line (V2) to which the other pole of a power supply source is connected. The output of the voltage longitudinal controller (SR) is connected to the second connection line (V2) via a first limiting diode (D1) and a second limiting diode (D2) which preferably is installed opposite the first connected diode. The joint node of the two limiting diodes (D1, D2) is connected to the control input of the voltage longitudinal controller (SR).

Abstract: The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.

Abstract: The present invention includes a driving circuit and method for driving signals. An input signal is received by the driving circuit on an input signal line which is connected to a bias circuit for a common voltage level. Two output lines from the driving circuit are driven to the receiver which is capable of using differential output lines or a selected single ended output line. Furthermore, the output lines may be driven to a high impedance selected by the voltage level of the input signal. The receiver of the output lines may be a SCSI device using multimode terminators which include low voltage differential and a single ended mode.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

Abstract: There is disclosed a method for loading data into a plurality of programmable devices connected in parallel to one or more data lines comprising the steps of:

Abstract: A reconfigurable chip includes a despreader/correlator function back in order to better implement communication protocols which require despreading and/or correlation. These despreader/correlation functional blocks are used in addition to reconfigurable functional blocks having arithmetic logic units. The functions of the despreader/correlator functional blocks are preferably controlled by instructions from a local instruction memory.

Abstract: Ladder network 396 comprises control terminals including at least ground terminal 50e and master terminal 60e, and slave terminals 51, 53, 55, 57, 59, each individually connected to terminal 50e through fuse elements 12a,b,c,d,e, respectively. Said slave terminals are also sequentially linked, each to the next through antifuses 42a,b,c,d, respectively. Master terminal 60e is connected to terminal 51. By applying programming signals to said control terminals, terminal 60e may be disconnected from terminal 50c and sequentially connected to each slave terminal. Described ladder variations include segmented ladder 400, wherein terminal 60e can be sequentially connected to, and subsequently disconnected from, second conductors 51a,53a,55a,57a,59a; hierarchical ladder network 4000; and programmable SAW transducer 2000.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

Abstract: A method and apparatus for mitigating the hysteresis effect in a sensing circuit used in the evaluation of a property of a system under test. A state monitor circuit is included for detecting the sensing circuit's state upon evaluating the system's property, e.g., a data out signal level. A feedback control generator is provided for generating a control signal operable to transition the sensing circuit's state to a balanced state, wherein the control signal's logic state is capable of being modified substantially immediately upon completion of the evaluation operation.

Abstract: A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

Abstract: A track and hold circuit including a MOS transistor switch, a holding capacitor, and a bulk potential of the MOS transistor switch changed in phase with an input signal in order to reduce harmonic distortions.

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply.

Abstract: A digital delay line includes a delay section and a clock providing section. The delay section comprises N (N being a natural number) unit delay elements which are connected in series and each of which is composed of one logic product gate. The clock providing section provides a first clock signal, or a second clock signal having a phase difference of 180° with respect to the first clock signal, to one among the N unit delay elements according to an externally inputted selection signal. The first clock signal is provided to the unit delay elements bearing even numbers, as counted from a clock output terminal, and the second clock signal is provided to the unit delay elements bearing odd numbers. According to the digital delay line, the jitter characteristic of a delay locked loop can be improved, and the area required for designing the digital delay line can be reduced by one-half in comparison to the existing digital delay line.

Abstract: A D-type latch with current mode switching using MOS transistors for high speed data communication without excessive noise and poor waveform jittering and a method of quantitative circuit design of such D-type latch circuit is presented. With this method, a value of electrically equivalent channel geometry is selected for the input pair of MOS transistors and a different value of electrically equivalent channel geometry is selected for the feedback pair of MOS transistors so as to reduce the resulting amount of output signal ringing as compared to a similar D-type latch circuit where the corresponding values of electrically equivalent channel geometry are equal. Furthermore, a set of output signal waveforms from a divide-by-2 counter and a divide-by-16 counter using the D-type latch as their building block are presented.

Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desirable phase relationships, such as quadrature signals. The phase shift ring oscillator includes an odd number of amplifier stages. Each amplifier stage includes a phase shift network and an amplifier network. CMOS components used in the phase shift and amplifier networks provide voltage controlled variable phase shift and low gain, wide bandwidth, and low output impedance.

Abstract: A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.

Abstract: A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.

Abstract: A voltage mode logarithmic amplifier comprising: a first gain stage for providing an amplified rectified voltage signal responsive to an input voltage signal; a second gain stage for providing a further amplified rectified signal responsive to the input voltage signal; and an output node for producing an output voltage signal responsive to the amplified rectified voltage signal and the further amplified rectified voltage signal. The amplifier further includes: a self-biased replica stage operative to provide a voltage offset signal responsive to temperature; and a differential amplifier operative to receive the voltage offset signal and provide a temperature corrected output voltage signal responsive to the input voltage signal, wherein the differential amplifier is communicatively coupled to both the first gain stage and the second gain stage.

Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.

Abstract: An apparatus and method for providing an analog preset switching system for guitar electronic effect devices is disclosed. The system comprises real-time settable analog presets with LED indication of the preset selection, real-time settable control means for determining how many of the presets are enabled, and true bypass switching means with LED indication of bypass status for switching between effected and non-effected audio signals. A digitally-controlled bypass signal as well as one or more digitally-controlled preset control signals are provided to control analog multiplexers for the real-time settable analog presets and the true bypass switching means. Multiplexing means are also provided for LED indication of the preset selection and bypass status.

Abstract: A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off supply of power source voltage to any optional one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the optional circuit block to other circuit blocks and provided before its signal being branched thereto. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes storage unit for storing a signal right before the power cut.

Abstract: A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: A signal processing circuit using positive feedback while keeping the open loop gain of the circuit less than 1 to avoid oscillation. The circuit includes a floating signal source, a low gain amplifier, a feedback element, and a second stage circuit. The floating signal source produces a voltage that is impressed across the feedback element by the feedback system. The feedback element processes the voltage into an output current. The output current is passed through an output current node to the second stage circuit where the output current can be used as a current reference or be further processed. The output from the low gain amplifier may be used as a voltage output node that provides a voltage that is an amplification of the voltage produced by the floating signal source. The signal processing circuit may be embedded in another circuit, including additional stages of the signal processing circuit.

Abstract: A signal processing circuit using positive feedback while keeping the open loop gain of the circuit less than 1 to avoid oscillation. The circuit includes a floating signal source, a low gain amplifier, a feedback element, and a second stage circuit. The floating signal source produces a voltage that is impressed across the feedback element by the feedback system. The feedback element processes the voltage into an output current. The output current is passed through an output current node to the second stage circuit where the output current can be used as a current reference or be further processed. The output from the low gain amplifier may be used as a voltage output node that provides a voltage that is an amplification of the voltage produced by the floating signal source. The signal processing circuit may be embedded in another circuit, including additional stages of the signal processing circuit.

Abstract: A feed forward type distortion compensation amplification apparatus includes a first division unit for dividing an input signal into a first channel signal and a second channel signal, a main amplifier for amplifying the first channel signal, a variable attenuation unit for processing the second channel signal to provide an amplitude adjusted second channel signal, a delay unit for delaying the amplitude adjusted second channel signal, a second division unit for dividing an output signal of the main amplifier into a third channel signal and a fourth channel signal and subtracting one of the third channel signal and the delayed second channel signal from the other to extract a distortion component introduced by the main amplifier, and a distortion compensation unit for removing a distortion component introduced into the fourth channel signal by the main amplifier, by using the distortion component extracted by the second division unit.