Patents Issued in March 20, 2003
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Publication number: 20030054637Abstract: A method for forming silicide, at least includes following essential steps: provide substrate which is covered with semiconductor structure which has rugged surface; form silicon layer on semiconductor structure; form a metal layer on silicon layer; form capping layer on metal layer; and perform thermal process to form silicide layer by reacting of metal layer and silicon layer, where the thermal stability of capping layer is superior to the thermal stability of silicide layer. The method further perform a pattern process to form numerous conductive lines at least are made of silicide layer. One main characteristic of this invention is to limit agglomeration of silicide by high thermal stable capping layer, such that occurrence of electrical open induced by open of silicide is reduced.Type: ApplicationFiled: September 20, 2001Publication date: March 20, 2003Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Tien-Chu Yang
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Publication number: 20030054638Abstract: The present invention provides a CVD material compound based on an organic ruthenium compound, the organic ruthenium compound consisting of one of cis and trans isomers of tris (2,4-octa-dionato) ruthenium (III). The organic ruthenium compound which consists of cis or trans isomer can be isolated by the steps of preparing tris (2,4-octa-dionato) ruthenium (III) in any method, making the tris (2,4-octa-dionato) ruthenium (III) adsorbed on an adsorbent including alumina, bringing the adsorbent into contact with a first solvent to elute the trans isomer and then bringing the adsorbent into contact with a second solvent having a polarity higher than that of the first solvent to elute the cis isomer.Type: ApplicationFiled: June 21, 2002Publication date: March 20, 2003Applicant: Tanaka Kikinzoku Kogyo K.K. (Japanese Corporation)Inventors: Masayuki Saito, Junichi Taniuchi, Koji Okamoto, Hiroaki Suzuki
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Publication number: 20030054639Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.Type: ApplicationFiled: February 15, 2002Publication date: March 20, 2003Applicant: Optronx, Inc.Inventor: Shrenik Deliwala
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Publication number: 20030054640Abstract: According to a process for treating perfluorides in which a perfluoride treatment undertaker carries out decomposition treatment of perfluorides discharged from a manufacturing plant by using a perfluoride treating apparatus connected to said manufacturing plant, and the cost of treatment of perfluorides calculated according to the amount of perflorides treated by said perfluoride treating apparatus is communicated to the owner of said manufacturing plant, it is possible to reduce the cost required for the decomposition treatment of perfluorides which cost is to be defrayed by the product manufacturer.Type: ApplicationFiled: February 28, 2002Publication date: March 20, 2003Inventors: Shin Tamata, Takashi Yabutani
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Publication number: 20030054641Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.Type: ApplicationFiled: April 11, 2002Publication date: March 20, 2003Applicant: MEMC Electronic Materials, Inc.Inventors: Martin Jeffrey Binns, Robert J. Falster, Jeffrey L. Libbert
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Publication number: 20030054642Abstract: The present invention provides a method of and a system for fabricating a semiconductor device, which are capable of suppressing variations in line widths due to a dependence of a dense/sparse line layout on the line widths within one chip, thereby highly accurately forming micro-patterns on a semiconductor chip or the like. In this method, a numerical aperture of a lens system of an exposure apparatus is adjusted, by a host computer functioning as a numerical aperture adjusting apparatus, so as to reduce variations in line widths of patterns formed in an etching step or resist patterns formed in a photolithography step on the basis of a correlation between the variations in line widths and a dense/sparse line layout for the patterns or a correlation between the variations in line widths and a dense/sparse line layout for the resist patterns.Type: ApplicationFiled: October 23, 2002Publication date: March 20, 2003Inventors: Hiroshi Kagotani, Harunobu Hirano, Mitsuo Hama
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Publication number: 20030054643Abstract: An adhesive tape having an adhesive layer formed on one side of a substrate layer, which renders it possible to minimize the extent of development of chipping or fragmentation (nicks) or crack in chip when the silicon wafer, to which this tape is adhered, is cut into chips using a dicer. The adhesive layer of the tape has a storage modulus G′ of 1 MPa or more at a temperature of 15 to 35° C., and preferably tan&dgr; as represented by the ratio of a loss modulus G″ to the storage modulus G′ is 0.05 or less. The adhesive layer is preferably constructed principally of an olefin polymer.Type: ApplicationFiled: July 22, 2002Publication date: March 20, 2003Inventors: Shin Aihara, Hitoshi Koga
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Publication number: 20030054644Abstract: A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method includes estimating polish rates using polish data near the end of the polish period. Non-linear regression and iterative optimization is presented to extract relevant information. The processing includes least square processing step (43), determining the search fit (44) and determining if this is the best fit (45).Type: ApplicationFiled: August 8, 2002Publication date: March 20, 2003Inventors: Nital Patel, Gregory A. Miller, Steven T. Jenkins
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Publication number: 20030054645Abstract: A microchip-based electrospray device and method of fabrication thereof are disclosed. The electrospray device includes a substrate defining a channel between an entrance orifice on an injection surface and an exit orifice on an ejection surface, a nozzle defined by a portion recessed from the ejection surface surrounding the exit orifice, and an electric field generating source for application of an electric potential to the substrate to optimize and generate an electrospray. The method includes providing a nozzle and annulus pattern to the polished side of a wafer. The nozzle channel is etched and the back side of the wafer lapped or ground until the nozzle through channel is exposed. The annulus etch may be conducted prior to or following the backgrinding process.Type: ApplicationFiled: September 17, 2002Publication date: March 20, 2003Inventor: Gary S. Sheldon
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Publication number: 20030054646Abstract: A mask has a monocrystal substrate having opposite surfaces which are planes having Miller indices {110}. A plurality of penetrating holes are formed in the monocrystal substrate. An opening shape of each of the penetrating holes is a polygon and each side of the polygon is parallel with a plane in a group of the {111} planes. The wall surfaces of the penetrating holes are the {111} planes. In the method of manufacturing a mask, openings are formed in the etching resistant film corresponding to the shape of the penetrating holes and the monocrystal substrate is etched.Type: ApplicationFiled: September 19, 2002Publication date: March 20, 2003Applicant: SEIKO EPSON CORPORATIONInventor: Shinichi Yotsuya
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Publication number: 20030054647Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.Type: ApplicationFiled: November 4, 2002Publication date: March 20, 2003Inventors: Tomoki Suemasa, Tsuyoshi Ono, Kouichiro Inazawa, Makoto Sekine, Itsuko Sakai, Yukimasa Yoshida
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Publication number: 20030054648Abstract: A chemical mechanical polishing (CMP) apparatus and method for sequentially polishing multiple semiconductor wafers on a single polishing pad utilizes multiple slurry delivery lines to supply one or more types of polishing solutions to the surface of the polishing pad. The slurry delivery lines are positioned to direct the polishing solution or solutions to different polishing positions of the polishing pad. The use of multiple slurry delivery lines allows the CMP apparatus to polish the semiconductor wafers at different polishing positions of the polishing pad using different types of polishing solutions.Type: ApplicationFiled: September 18, 2001Publication date: March 20, 2003Inventor: In Kwon Jeong
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Publication number: 20030054649Abstract: A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.Type: ApplicationFiled: October 12, 2001Publication date: March 20, 2003Inventors: Shaoyu Wu, Joon Mo Kang, Pang Dow Foo
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Publication number: 20030054650Abstract: A process is for material-removing machining, on both sides simultaneously, of semiconductor wafers having a front surface and a back surface, the semiconductor wafers resting in carriers which are set in rotation by means of an annular outer drive ring and an annular inner drive ring and being moved between two oppositely rotating working disks in a manner which can be described by means of in each case one path curve relative to the upper working disk and one path curve relative to the lower working disk, wherein the two path curves after six loops around the center have the appearance of still being open, and at each point have a radius of curvature which is at least as great as the radius of the inner drive ring.Type: ApplicationFiled: June 18, 2002Publication date: March 20, 2003Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AGInventors: Guido Wenski, Thomas Altmann, Gerhard Heier, Wolfgang Winkler, Gunther Kann
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Publication number: 20030054651Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.Type: ApplicationFiled: October 30, 2002Publication date: March 20, 2003Inventors: Karl M. Robinson, Pai-Hung Pan
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Publication number: 20030054652Abstract: A method is provided for fabricating a multi-layer microfluidic device on a base. A first layer is positioned on the base in a spaced relationship thereto so as to define a construction cavity therebetween. The first layer has a passageway therethrough which communicates with the construction cavity. A mask is positioned between the construction cavity and an ultraviolet source. The mask corresponds to a channel to be formed in the construction cavity. The construction cavity is filled with material and a portion of the material is polymerized within the construction cavity so as to solidify the same. The solidified material defines the channel. Thereafter, the material is flushed from the channel in the construction cavity.Type: ApplicationFiled: September 14, 2001Publication date: March 20, 2003Inventors: David J. Beebe, Glennys A. Mensing
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Publication number: 20030054653Abstract: The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.Type: ApplicationFiled: March 19, 2002Publication date: March 20, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20030054654Abstract: A new method of forming shallow trench isolations using a reverse mask process is described. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches is etched through the etch stop layer and the polish stop layer into the substrate whereby narrow active areas and wide active areas of the substrate are left between the isolation trenches. An oxide layer is deposited over the etch stop layer and within the isolation trenches. The oxide layer is covered with a mask in the narrow active areas and in the isolation trenches and etched away in the wide active areas stopping at the etch stop layer. Thereafter, the mask is removed and the etch stop layer is polished away to the polish stop layer whereby the oxide layer in the isolation trenches is planarized to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.Type: ApplicationFiled: September 14, 2001Publication date: March 20, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Feng-Chen, Cheng-Hou Loh, Paul Proctor
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Publication number: 20030054655Abstract: When determining the presence of foreign particles in a processing chamber by radiating a laser beam inside a processing chamber and detecting scattered light from foreign particles within the processing chamber, the detection of scattered light is performed using a detecting lens having a wide field angle and deep focal depth. Accordingly, the detection of foreign particles floating in the processing chamber can be performed across a wide range, and with uniform sensitivity, with a detecting optical system having a simple constitution.Type: ApplicationFiled: August 30, 2002Publication date: March 20, 2003Inventors: Hiroyuki Nakano, Takeshi Arai, Toshihiko Nakata
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Publication number: 20030054656Abstract: In a method for manufacturing a semiconductor device, a photoresist pattern layer is formed on an interlayer insulating layer made of inorganic material including CH3-groups and/or H-groups. Then, the interlayer insulating layer is etched by using the photoresist pattern layer as a mask. Finally, a two-step ashing process is performed upon the photoresist pattern layer while the interlayer insulating layer is exposed. The two-step ashing process includes a first step using N2 plasma gas and a second step using N2/H2 plasma gas after the first step.Type: ApplicationFiled: September 9, 2002Publication date: March 20, 2003Applicant: NEC CorporationInventor: Eiichi Soda
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Publication number: 20030054657Abstract: The present invention provides an observation device installed in a chamber that is used for manufacturing semiconductor devices. The observation device includes at least two light-emission sources located at a chamber wall of the chamber, an electric power supplier supplying electric power to the light-emission sources, and a viewer port which is also installed in the chamber wall. The light-emission sources correspond in position to each other in the chamber wall, and emit light downward. The viewer port includes a quartz window so that when the light-emission sources light up the inside of the chamber, an observer can observe a wafer and the chamber inside through the viewer port.Type: ApplicationFiled: September 13, 2002Publication date: March 20, 2003Inventor: Jung-Sik Kim
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Publication number: 20030054658Abstract: A dry silylation process involving plasma etching of a substrate (100) having an upper surface (100S) coated with a first layer (L1) of silylatable material with one or more silylated regions (S1, S2) formed therein. The plasma (66) is oxygen-based plasma having a first region (66L) with a low plasma density and high radical density, and a second region (66U) having a high plasma density and a low radical density. The process includes the steps of exposing the one or more silylated regions to the first plasma region to form respective one or more oxidized regions (OR1, OR2) from the one or more silylated regions. The next step is then exposing the substrate to the second plasma region to selectively etch the silylatable material that is directly exposed to the plasma. The process of the present invention can be used, for example, to form photoresist patterns (P) having straight (vertical) sidewalls (SW) in the fabrication of a semiconductor device.Type: ApplicationFiled: September 30, 2002Publication date: March 20, 2003Inventor: Lianjun Liu
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Publication number: 20030054659Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Therefore, a circuit device and a method for fabricating the same according to the invention solves the above-described and other problems by the structure, wherein an insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12.Type: ApplicationFiled: June 14, 2002Publication date: March 20, 2003Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
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Publication number: 20030054660Abstract: To produce a SiC crystal in a shape which is used as a wafer, a guide is disposed around a SiC crystal substrate so as to cover a peripheral portion of the SiC crystal substrate. Temperature of the guide may be made higher than the sublimation temperature of the SiC when a SiC crystal is disposed upon and caused to grow on the SiC crystal substrate, thereby controlling and restricting the SiC crystal growth in the direction of the guide. Additionally, when the guide is formed in a substantially hexagonal tube shape, the SiC crystal can be produced in a hexagonal pole shape. In this case, when alignment is made between each diagonal passing through a center of the hexagon shape of the guide and specific direction (<11{overscore (2)}0> or <1{overscore (1)}00> of the SiC crystal substrate), the SiC crystal becomes aligned accordingly.Type: ApplicationFiled: September 18, 2001Publication date: March 20, 2003Inventors: Haruyoshi Kuriyama, Hiroyuki Kondo, Shouichi Onda, Kazukuni Hara
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Publication number: 20030054661Abstract: Systems and methods are described for synthesis of films, coatings or layers using electrostatic fields. A method includes applying an electrostatic field across a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: ApplicationFiled: September 20, 2001Publication date: March 20, 2003Inventor: Billy J. Stanbery
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Publication number: 20030054662Abstract: Systems and methods are described for synthesis of films, coatings or layers using surfactants. A method includes providing a surfactant as an impurity within at least one of a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: ApplicationFiled: September 20, 2001Publication date: March 20, 2003Inventor: Billy J. Stanbery
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Publication number: 20030054663Abstract: Systems and methods are described for synthesis of films, coatings or layers using templates. A method includes locating a template within at least one of a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: ApplicationFiled: September 20, 2001Publication date: March 20, 2003Inventor: Billy J. Stanbery
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Publication number: 20030054664Abstract: The whole areas of both surfaces (10a and 10b) of a silicon wafer (10) are covered by silicon nitride films (13, 14) respectively through the intermediary of pad oxide films (11 and 12), and the pad oxide film (11) and the silicon nitride film (13) on the front surface (10a) of the wafer are patterned in desired regions and therefore the front surface (10a) is partially exposed. On the other hand, the pad oxide film (12) and the silicon nitride film (14) on the reverse surface (10b) of the wafer are removed, so the whole area of the reverse surface (10b) is exposed. By simultaneously oxidizing the regions exposed partially on the front surface (10a) of the wafer and the whole area of the reverse surface (10b) of the wafer, silicon dioxide films (15 and 16) are grown on those areas of the wafer.Type: ApplicationFiled: January 3, 2002Publication date: March 20, 2003Inventor: Yoshirou Tsurugida
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Publication number: 20030054665Abstract: Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced. Nitrogen is introduced into the furnace in the entire oxidation process, including the main oxidation steps. In the preparing step of ramp up, the ramp up step and the stable step, prior to the main oxidation, nitrogen is introduced in a sufficient flow rate to make the environment near the saturated vapor pressure to reduce boron outgassing at the trench.Type: ApplicationFiled: April 25, 2002Publication date: March 20, 2003Applicant: MOSEL VITELIC, INC.Inventors: Jen-Te Chen, Kou-Liang Jaw, Mao-Song Tseng, Kou-Wei Yang
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Publication number: 20030054666Abstract: A siloxan polymer insulation film has a dielectric constant of 3.3 or lower and has —SiR2O— repeating structural units. The siloxan polymer has dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.Type: ApplicationFiled: September 24, 2002Publication date: March 20, 2003Applicant: ASM JAPAN K.K.Inventor: Nobuo Matsuki
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Publication number: 20030054667Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10W to about 500W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.Type: ApplicationFiled: August 22, 2002Publication date: March 20, 2003Applicant: Applied Materials, Inc.Inventors: Wai-Fan Yau, David Cheung, Nasreen Gazala Chopra, Yung-Cheng Lu, Robert Mandal, Farhad Moghadam
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Publication number: 20030054668Abstract: The present invention includes a hermetic container provided therein with a mount for mounting thereon a substrate coated with a coating solution made by mixing a component of a coating film and a solvent; a vacuum exhauster connected to the hermetic container through an exhaust passage for reducing a pressure in the hermetic container to vaporize the solvent from the coating solution on the substrate; a current member provided to face a front face of the substrate mounted on the mount; and a current member raising and lowering mechanism for raising and lowering the current member. When the current member is raised and lowered to change in height position while the pressure inside the hermetic container is reduced to vaporize the solvent from the coating solution on the substrate, a liquid flow of the coating solution on the substrate is controlled, thereby controlling the film thickness of a film of the coating solution.Type: ApplicationFiled: August 14, 2002Publication date: March 20, 2003Applicant: TOKYO ELECTRON LIMITEDInventors: Takahiro Kitano, Manabu Hama, Shinichi Sugimoto, Naoya Hirakawa
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Publication number: 20030054669Abstract: In accordance with a specific embodiment of the present invention, a method of forming a gate dielectric is disclosed. A semiconductor wafer is placed in a deposition chamber. The semiconductor wafer is heated and a precursor gas is flowed into the chamber. In one embodiment, the precursor comprises a moiety of silicon, oxygen, and a transition metal. In another embodiment, the moiety includes a group 2 metal.Type: ApplicationFiled: November 1, 2002Publication date: March 20, 2003Inventors: Prasad V. Alluri, Robert L. Hance, Bich-Yen Nguyen, Christopher C. Hobbs, Philip J. Tobin
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Publication number: 20030054670Abstract: Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.Type: ApplicationFiled: September 17, 2001Publication date: March 20, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Tsong Wang, Shi-Wei Wang, Shin-Kai Chen
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Publication number: 20030054671Abstract: In case of depositing a silicon oxide film and a silicate glass film, which are used as inter-layer insulating films by high density plasma CVD method, deposition temperature is set in the range from 400 to 680° C., preferably in the range from 400 to 600° C., furthermore preferably in the range from 450 to 550° C. Thereby, it is aimed to improve reliability of the insulating films by controlling plasma damage while controlling expansion of contact holes caused by a hydrofluoric acid process in pretreatment prior to a process for burying the contact holes with burying material after the contact holes have been formed in the insulating film.Type: ApplicationFiled: October 1, 2002Publication date: March 20, 2003Inventor: Shigeru Fujita
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Publication number: 20030054672Abstract: The invention relates to a holding device for sliding contacts. The holding devices so far known require a very high expenditure for mounting or alignment. A flexible printed circuit board with mechanically rigid carrier elements that permit the adaptation to the geometry of the slipring enables a simple and low-cost structure.Type: ApplicationFiled: August 8, 2002Publication date: March 20, 2003Inventor: Kurt Dollhofer
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Publication number: 20030054673Abstract: A cable management slide system that flexibly follows the displacement of a module into and out of a cabinet housing to allow the rear access ports of the module to be connected to adjacent modules through connectors that are laterally and forwardly positioned with respect to the module. Use of cable management slides on opposite sides of the modules allows one to physically isolate the power cable for the module from the data line of the module thereby inhibiting or preventing electrical interference therebetween.Type: ApplicationFiled: September 17, 2001Publication date: March 20, 2003Inventors: Nathan E. Stremick, Clinton D. Crosby
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Publication number: 20030054674Abstract: A coaxial cable to circuit board connection is provided that has reduced return losses. An apparatus for connecting the coaxial cable to the circuit board includes a tube and an extension member. The tube secures the coaxial cable such that an inner conductor of the coaxial cable may be directly connected to the circuit board. The extension member is connected approximately longitudinally along the tube and extending approximately radially outward from the tube such that an outer conductor of the coaxial cable may be connected to the circuit board.Type: ApplicationFiled: September 17, 2001Publication date: March 20, 2003Inventor: Robert F. Evans
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Publication number: 20030054675Abstract: A socket (1) has a base (2) on which rows of contact pins 4 are arranged, the contact pins being elastically deformable in the vertical direction, an adaptor (5) having rows of contact holes (5d) arranged extending through a seating surface (5c) and which is capable of vertical movement relative to the base (2) so that contact tips (4a) of contact pins (4) can move in respective contact holes (5d). Latches (21) are arranged to be able to press the IC package on the seating surface (5c) of the adaptor (5) and a vertically movable regulator (7) is arranged at a selected position relative to adaptor (5) when stop surfaces (7e) of the regulator are engaged with a part (4e) of the contact pins (4) so as to regulate the position of the contact tips (4a) in the contact holes (5d).Type: ApplicationFiled: September 4, 2002Publication date: March 20, 2003Inventor: Kiyokazu Ikeya
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Publication number: 20030054676Abstract: A socket 1 for testing an electric part 10 has a plurality of contact members 4 which are arranged in the shape of a matrix that are held by a contact holder unit 3 which is secured in a central aperture 6 of socket base 2. The contact holder unit 3 contains a plurality of contact holders 30 which each hold one row of contact members 4 having a thickness equal to the pitch p between neighboring contact members, that are joined together.Type: ApplicationFiled: August 26, 2002Publication date: March 20, 2003Inventors: Hideki Sano, Kiyokazu Ikeya
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Publication number: 20030054677Abstract: The present invention includes a connector with a plurality of insertion holes that each is connected with a male terminal. A plurality of serration is installed at the middle part of the male terminal for fastening the male terminal inside the insertion holes. The rear part of the male terminal is bent to form a Z-shaped leg that is connected with a connecting point on the circuit board. The device is characterized in that the Z-shaped leg and the serration of the male terminal is made by press directly and then turned 90 degrees so as to make the Z-shaped leg facing downwards and have higher strength of structure which can prevent the elastic deformation. Moreover, not only the deformation of connectors caused by assembling with male terminals can be avoided but also the terminals can be assembled into connectors quickly.Type: ApplicationFiled: September 14, 2001Publication date: March 20, 2003Inventor: Chung-Ming Lee
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Publication number: 20030054678Abstract: A slanted connector and a method for mounting the same, having first connector means (20) extended in a first direction and second connector means (29a-c) extended in a slanted direction in relation to the first connector means (20). According to the invention the slanted connector comprises a first part (2) comprising the first connector means (20) and a second part (21a-e) comprising the second connector means (29a-c). The second part (21a-e) is connectable to the first connector means (20) and has a bent form in order to engage the first connector means (20) in a first direction and provide the second connector means (29a-c) protruding in at least one second direction slanted to the first direction, the second part (21a-e) having a circuit pattern to connect the first connector means (20) to the second connector means (29a-c).Type: ApplicationFiled: October 7, 2002Publication date: March 20, 2003Inventor: Joachim Grek
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Publication number: 20030054679Abstract: A safety device for monitoring heat for connection in electrical installations, comprises a first connecting element (14) in thermal relationship with an electrical connection to be monitored. A second element (35) is also designed to be connected to the ground of the general electric installations. Electrical connecting structure (21) connects the two elements and can adopt two states, one an insulating state in normal operating conditions and the other an interrupting state wherein there is contact and hence earthing of the first element with the second when a critical temperature is reached.Type: ApplicationFiled: October 23, 2002Publication date: March 20, 2003Inventor: Cyril Charles
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Publication number: 20030054680Abstract: A pivoting outlet, for electrical and other services, that can be installed in various surfaces such as desktops or similar furniture, drywalls, and outside walls of buildings. The structure pivotally mounts an outlet bracket with a slot for an outlet providing one or more services. A terminal block is included to interconnect the outlet to various sources for the services. The outlet bracket is pivotally rotated between a working and a recessed position. Further, a door, a door tab, a cord guide, and a cord bracket are integrated with the outlet bracket. The cord guide is designed to allow various devices to be connected to the outlet even with the outlet bracket in the recessed position. The cord bracket may be used to secure the cords of the various devices. The combination of these features has a number of advantages including cord strain relief, aesthetics, and weather protection.Type: ApplicationFiled: October 25, 2002Publication date: March 20, 2003Inventor: Lorne Ross
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Publication number: 20030054681Abstract: Locking and unlocking a lever and the both connectors effectively, a lever-joint connector includes one connector 1 having a lever 4 and the other connector 29 having a follower portion engaging slidably with the lever, providing a first locking portion 5 and a pushing portion 6 on the lever 4, providing a first be-locked portion 7 and a second locking portion 9 having a be-pushed portion 28 on the one connector 1, providing a second be-locked portion 30 on the other connector 29, pushing the be-pushed portion 28 during the lever 4 turns by means of the pushing portion 6 to turn the second locking portion 9 for unlocking the second be-locked portion 30.Type: ApplicationFiled: September 17, 2002Publication date: March 20, 2003Applicant: YAZAKI CORPORATIONInventors: Yuji Hatagishi, Naotoshi Sato
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Publication number: 20030054682Abstract: A cable reel is provided that has a movable inner sleeve member rotatably coupled to a stationary outer sleeve member. A flat cable is contained in an annular chamber defined between the sleeve members. Connection cases having same configuration are attached to the opposite ends of a flat cable, respectively. An end of a flat cable can be inserted into either side of the connection case. Each end is bent at the right angle and connected to bus bars that are fixed in the connection case beforehand. The flat cable includes a first conductor group having a greater width and a second conductor group having a smaller width. The first and second conductor groups are arranged on the respective side areas divided by the centerline of a width of the flat cable in a conductor-juxtaposing direction.Type: ApplicationFiled: August 30, 2002Publication date: March 20, 2003Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Shoichi Sugata
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Publication number: 20030054683Abstract: Arcs are prevented as electrical connectors are unmated by including a long and a short contact in an electrical connector with both contacts being connected along the same line between an electrical source and a load. The short contact comprises the lower resistance path between the source and the load and so carries most of the current when the connectors are fully mated. An electronic component, such as an FET or a positive temperature coefficient resistor is connected to the long contact. As the short contact is disconnected, the electronic component initially carries sufficient current to prevent arcing at the short contact. Current through the electronic component decays rapidly so that when the long contact is subsequently disconnected, the electrical energy in the short contact is reduced below an arcing threshold.Type: ApplicationFiled: April 22, 2002Publication date: March 20, 2003Inventors: Lyle S. Bryan, Jeremy C. Patterson, Charles D. Fry, Henry O. Herrmann
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Publication number: 20030054684Abstract: A terminal fitting is provided, by which the terminal fitting can be securely connected electrically to an electric wire. A pressure-welding terminal as the terminal fitting has a wire connecting part, to which an electric wire is press-fit. The electric wire consists of an electrically conductive core wire and an insulating coating. The wire connecting part includes a bottom wall, and first and second pressure-welding members, each of which has a pair of pressure-welding blades arising from the bottom wall. A projection is formed on an end of an inner edge of the blade near to the bottom wall.Type: ApplicationFiled: September 16, 2002Publication date: March 20, 2003Applicant: YAZAKI CORPORATIONInventors: Makoto Yamanashi, Kei Sato, Takuya Hasegawa, Shigeru Tanaka
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Publication number: 20030054685Abstract: An insulation displacement contact (20) having a conductive element (22) with an aperture (24). Contact portions (32) defined by parts of the edge of the aperture (24) converge towards each other and have opposed contact edges (32c) between which is defined a channel (42). Wires (48) introduced into an enlarged portion (24a) of the aperture (24) can be laterally moved into the channel (42) to cut insulation of the wire (48) and make electrical connection between a conductor (52) of the wire and the contact edges (32c).Type: ApplicationFiled: October 9, 2002Publication date: March 20, 2003Inventor: Laval Chung Long Shan
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Publication number: 20030054686Abstract: A connector module for connecting a portable electronic device to a power source and a network on-board a mobile platform, for example an aircraft. The connector module is adapted to be integrated into an interior compartment of the aircraft, either adjacent to or disposed within a seat of the aircraft. The connector module provides a networking port disposed within a housing that is adapted to couple the portable electronic device to the aircraft network. A power port is also disposed within the housing of the connector module and is adapted to receive a DC power cable of the portable electronic device for providing power to the portable electronic device. Several embodiments of the connector module provide various configurations for integrating the connector module into the compartment of the aircraft and/or into the seat of the aircraft.Type: ApplicationFiled: September 19, 2001Publication date: March 20, 2003Inventors: Drew A. Pappas, Andrew A. Thompson, Scott C. Sanner, Stephen J. Moritz