Abstract: A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.

Abstract: A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which identifies a disturbance situation of the integrated circuit, at least one temperature sensor, which detects the temperature of at least one part of the integrated circuit, and a logic device. The logic device ascertains a disturbance mode in dependence a detected disturbance situation and/or the detected temperature and which allocates a first temperature switching stage to the temperature sensor in the normal mode and allocates a second, lower temperature switching stage to the temperature sensor in the disturbance mode. Furthermore, the invention relates to an integrated circuit having such a configuration and also to a method for protecting an integrated circuit against over-temperature conditions.

Abstract: In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.

Abstract: In order to enable a simple and cost-effective directly electrically isolated transmission of data signals, the data signals are superposed on a clock signal in an input stage and are transmitted to an output stage in a directly electrically isolated manner via a decoupling device. The clock signal on which the transmitted signals are superposed is filtered out in the output stage. Pulse shape alterations occurring in the signals because of the transmission or because of the filtering-out of the clock signal are compensated in the output stage so that filtered data signals are present at the output of the circuit configuration.

Abstract: A pre-buffer circuit configured to generate one or more output control signals in response to a bandgap reference based control circuit. The one or more output control signals control output ON resistance and slew rate so as to limit variations in ringing and skew.

Abstract: A semiconductor integrated circuit is provided with logic circuits having transistors. The semiconductor integrated circuit is also provide with a clock tree including clock drivers which have transistors to distribute a clock signal to the logic circuits. Gate lengths of the transistors provided in the clock drivers are longer than that of the transistors provided in the logic circuits.

Abstract: A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Abstract: An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.

Abstract: A system and method are provided for providing an impedance match of an output buffer to a transmission line without significantly increasing the power consumption of the output buffer. A system and method are also provided for providing an impedance match of an output buffer to a transmission line, while still allowing for an adjustable output swing as is required for loads such as laser transmitters and optical modulators.

Abstract: A peak hold circuit that can operate to follow changes in peak value even if the changes are abrupt. The peak hold circuit (1) of the present invention has current control circuit (31), auxiliary switch element (25), and auxiliary constant current circuit (26). Current control circuit (31) counts the number of reference clock pulses RCK after output signal Vout becomes higher than analog voltage DI. When the number of clock pulses counted reaches a prescribed number or larger, auxiliary switch element (25) is turned on to operate auxiliary constant current circuit (26) to increase the amount of drop of output signal Vout per unit time. Consequently, even if output signal Vout becomes higher than the peak value of analog voltage DI, it is possible, by increasing the amount of drop of output signal Vout to make output signal Vout lower than analog voltage DI in a shorter amount of time than in the case in the conventional technology.

Abstract: The invention relates to a detector circuit (100) for detecting short-lasting voltage pulses (spikes) in a power supply voltage (VDD). An integrator (INT) forms the average value (VDD_AV) of the power supply voltage (VDD) and a corresponding energy is stored in a first memory (MEM1). A comparator (COMP) compares the power supply voltage (VDD) with a predetermined voltage interval ([Vref1, Vref2]) and closes a switch (S) when the power supply voltage is outside this interval. The energy from the first memory (MEM1) then flows into a second memory (MEM2) via the switch (S) and a delay circuit (DELAY). When the energy in the second memory (MEM2) exceeds a threshold value, an output stage (OUT) is thereby activated, whose output supplies a signal (SPIKE_DET) indicating a voltage spike.

Abstract: A driver circuit and receiver circuit to reduce power consumption of a digital signal transfer circuit is described. A driver circuit 20 includes a PFET 21, an NFET 23, and an NFET 22 having a low threshold voltage. An input signal DIN-bar is supplied to a gate of the PFET 21, and a reference voltage Vref is supplied to a gate of the NFET 22. A signal having a small amplitude restricted by Vref is outputted from the driver output DOUT. A receiver circuit 40 having a PFET 41 and NFETs 42 and 43 having low threshold voltages, and an inverter having a PFET 44 and a NOT gate 45. The receiver circuit 40 shifts the level of the signal with the small amplitude, drives it with the inverter and outputs a signal ROUT having a CMOS level.

Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.

Abstract: A frequency multiplier is described for synthesizing frequencies. The frequency multiplier includes a phase locked loop (PLL) circuit having an oscillator to generate a number of phase signals and a phase-shifting circuit coupled to the PLL circuit to select one of the phase signals generated by the oscillator according to a defined phase sequence to be passed to a feedback loop. Also included in the frequency multiplier is a divide-by-M circuit inserted in the feedback loop which divides a frequency of the signal selected by the phase-shifting circuit to generate a feedback signal for the PLL circuit. In one embodiment, the feedback signal generated by the divide-by-M circuit serves as a control signal to enable the phase-shifting circuit.

Abstract: A random number generator has a simple configuration using know inexpensive electronic parts and can generate the true physical random numbers at a required generation speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises Hen no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals.

Abstract: A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage.

Abstract: A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((Clk×P)+O1)}.

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal.

Abstract: A current mode step attenuation control circuit with digital technology. The circuit includes several stages of serially connected current attenuation circuits, each having a digital control input port, common mode feedback signal input port and bias input port, which are connected to corresponding a digital control signal, a common mode feedback current and a bias voltage, respectively. An analog input signal inputted to the circuit is controlled by the digital control signal to implement step attenuation. By using the conducting resistance of a MOS transistor to form equivalent resistance or match of current source for attenuation, the circuit eliminates dependence on resistance match of conventional technology. Because step attenuation is directly controlled by a digital control signal, the transmission speed is fast, phase delay is small, control accuracy is high and the device is suitable for digital integrated circuit manufacturing technology.

Abstract: A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase.

Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal when added thereto. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In this manner, third and higher-order corrections can be made, and the detection of characteristics such as data, temperature and other terms is improved.

Abstract: The invention relates to a high frequency switch used in a communication apparatus or the like, such as a portable terminal. The switch includes a first signal terminal, a first diode, the cathode of which is directly or indirectly connected to the first signal terminal, a bias controlling device having an end which is connected to the anode of the first diode, a second signal terminal directly or indirectly connected to the anode of the first diode, an impedance converting device having an end which is directly or indirectly connected to the first signal terminal, a serial circuit having a high frequency voltage dividing device and a second diode, the serial circuit being connected to the other end of the impedance converting device, and a third signal terminal directly or indirectly connected to the other end of the impedance converting device.

Abstract: An analog voltage pulse generator, including a first break-over component of Shockley diode type to activate a rising edge of a pulse on an output terminal and a second component of thyristor type to block the first component and deactivate the pulse.

Abstract: An AC transfer switch (ATS) is provided for switching a system load between at least two AC lines. A first bridge rectifier is connected to a first AC line for providing a first full wave rectified AC waveform. A first pair of oppositely poled silicon controlled rectifiers (SCRs) is coupled to the first bridge rectifier and to the system load. A second bridge rectifier is connected to a second AC line for providing a second full wave rectified AC waveform. A second pair of oppositely poled silicon controlled rectifiers (SCRs) coupled to the second bridge rectifier and to the system load. Control logic is coupled to a gate input of the first pair of oppositely poled silicon controlled rectifiers (SCRs) and a gate input of the second pair of oppositely poled silicon controlled rectifiers (SCRs) for applying one of the first full wave rectified AC waveform or the second full wave rectified AC waveform to the system load.

Abstract: A driver circuit 605 including a p-channel transistor 606 for driving an output from a supply rail at a positive supply voltage, p-channel transistor 606 disposed in an n-well. A detector 500 detects ramp down of the supply voltage below a preselected threshold voltage while a power reservoir 301 maintains a preselected well voltage of the n-well after the supply voltage ramps down below the preselected threshold.

Abstract: A method and a system for supplying power to a microcontroller with a single cell battery. A power supply pump circuit may be incorporated with the microcontroller having dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: A bandgap reference circuit has a pre-regulator that achieves a low temperature coefficient through the use of a first component that generates a first voltage having a negative temperature coefficient and a second component coupled in series to the first component and which generates a second voltage having a positive temperature coefficient. This low temperature coefficient in the pre-regulator allows the bandgap reference circuit to output the bandgap voltage VBG with a low temperature coefficient.

Abstract: An efficient demodulation and low pass filter structure comprises a shift-add-negate structure that effectively multiplies each received sample by a combined demodulation and filter coefficient, and an accumulator that accumulates the products. Low pass filter coefficients are selected such that the shift-add-negate structure implements multiplications by shifts, adds, and negations. In the preferred embodiment, the demodulation and low pass filter structure outputs three complex samples per symbol.

Abstract: A system for varying output power of variable-gain amplifiers (VGA) allows for varying the output power transfer function, thus varying the gain, and, hence, the resolution of the output power of the VGA. The preferred embodiment comprises a variable-slope VGA (VSVGA) circuit configured to operate within a closed-loop power-controlled CDMA handset. The VSVGA circuit manipulates the input control voltage of the VGA, thereby, adjusting the gain of the amplifier by varying the slope of a line which models the amplifier output transfer function. Varying gain of the VGA provides for a varying resolution in the VGA amplifier output transfer function. This variation allows for compatibility of a single CDMA handset with different industry standards.

Abstract: An amplifier comprising an input stage (IPST) having a pair of inputs (INN,INI) for receiving a differential input signal (Vin) and a pair of outputs (CQ6,CQ7) for delivering a differential intermediate signal in response to the differential input signal (Vin); an intermediate stage (INTST) for converting the differential intermediate signal to a non-differential intermediate signal, which intermediate stage (INTST) comprises a current mirror (Q5,R5,Q4,R4) having an input branch (Q5,R5) and an output branch (Q4,R4) for receiving the differential intermediate signal; an output stage (OPST) having an input coupled to the output branch (Q4,R4) and having an output for delivering an output signal (Vout) to an output (OP) of the amplifier; and means for stabilizing the amplifier. The means for stabilizing the amplifier comprises a capacitor (CM2) coupled between the output (OP) of the amplifier and the input branch (Q5,R5), and provides a large bandwidth and low supply voltage amplifier.

Abstract: A differential buffer/driver has a switch network that connects an IOH current source to a differential output to be drive high, and connects an IOL current source to the other differential output to be driven low. Each output can be connected to a pull-down boost current sink. A boost pulse momentarily connects a boost current sink to the differential output being driven low. The differential buffer generates a pair of boost pulses to activate the boost current for either differential output. One boost pulse is activated when one differential output is driven low, while the other boost pulse is activated when the other differential output is driven low.

Abstract: The amplifier output stage circuit includes: a translinear loop 30 having first and second input nodes Vin+ and Vin−; a first transistor Q7 coupled between a first output node of the translinear loop 30 and a first supply node V+; a first output transistor Q9 coupled between an output node 36 of the circuit and the first supply node V+, and having a base coupled to a base of the first transistor Q7; a second transistor Q10 coupled between a second output node of the translinear loop 30 and a second supply node V−; a second output transistor Q12 coupled between the output node 36 of the circuit and the second supply node V−, and having a base coupled to a base of the second transistor Q10.

Abstract: A differential amplifier circuit of the present invention comprises an input circuit 10 for producing a difference voltage signal between a positive input signal and a negative input signal, a feedback bias circuit 20 for inputting the difference voltage signal supplied from the input circuit 10 to provide a bias voltage corresponding to the difference voltage signal and for performing a feedback control on the bias voltage by feeding back an output current, an output circuit 30 for supplying a load with the output current corresponding to the bias voltage, and a current detection circuit 40 for detecting the output current to provide it to the feedback bias circuit 20. The differential amplifier circuit performs class-AB amplification in such a way that the bias voltage provides a current value close to zero when the difference voltage signal is substantially zero.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: A modular high power solid state amplifier and method of assembly, manufacture and use are herein disclosed. The high power amplifier includes a number of amplifiers, a DC board having flexible interconnects, a RF cover including an interlocking RF input, a RF board, a chassis, and a top cover; thereby providing an encased stand-alone solid state amplifier. The solid state components, angled designs, and piggyback topology of the invention provide a compact, efficient, integrated high power amplifier device.

Abstract: A low current amplifier circuit which stably operates at a low current and has a reduced tendency to cause static breakdown includes first and second field-effect transistors. The first field-effect transistor has a gate with a small width for passing a small current when a bias voltage is applied to the gate to compensate for variations in threshold voltage. The second field-effect transistor has a gate with a larger width than that of the first field-effect transistor and a source connected to a drain of the first field-effect transistor. The second field-effect transistor reduces a current flowing through the first field-effect transistor due to static electricity.

Abstract: A broadband power amplifier circuit providing wide bandwidth with low distortion. The broadband power amplifier circuit includes a GaAs pHEMT MMIC with two (2) serially coupled cascode amplifiers in a first half of the circuit, two (2) serially coupled cascode amplifiers in a second half of the circuit, a first balun for receiving a single-ended RF or microwave input signal at a circuit input and providing first and second balanced low level signals to the cascode amplifiers of the first and second circuit halves, respectively, and a second balun for receiving first and second balanced high level signals generated by the cascode amplifiers of the first and second circuit halves, respectively, and providing a single-ended amplified broadband output signal with low distortion at a circuit output.

Abstract: A phase-offset detecting phase comparator for comparing a reference signal and an auxiliary comparison signal which is a frequency-divided VCO output in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the auxiliary comparison signal by the first delay control signal to produce a comparison signal; a second delay element for adding delay to the VCO output by the second delay control signal to produce a PLL output; and a dummy frequency divider for adding delay corresponding to a frequency divider to the PLL output are provided.

Abstract: The present invention provides a phase-locked loop apparatus which extends a capture range in clock reproduction when digital data is reproduced and performs a high-speed and stable phase locking. A phase error is detected by a phase error detector 6 from a signal obtained by the sampling. Further, a frequency error is detected by a frequency error detector 8 on the basis of an inclination of a phase curve obtained by phase error information. A phase-locked loop circuit is controlled on the basis of these obtained phase error and frequency error.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: A phase locked loop (PLL) and method for stable clock generation in applications of wide band channel clock recovery performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and adjusts the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage.

Abstract: A crystal oscillator circuit is disclosed including a differential amplifier, a positive feedback assembly, and a series resonant crystal assembly. The differential amplifier includes a first transistor and a second transistor. The positive feedback assembly is coupled to each of the first and second transistors, and has a loop gain of greater than unity. The series resonant crystal assembly is coupled to one of the first and second transistors, and includes a crystal and a capacitor.

Abstract: All PMOS (p channel metal oxide semiconductor) fully differential voltage controlled oscillator (VCO). A fully differential implementation within the present invention provides for a very effective rejection of common mode noises. In addition, the PMOS implementation of the present invention allows for a substantial reduction in 1/f noise. The PMOS fully differential VCO may be employed within phase locked loops (PLLs) and other applications that require a very clean signal (with very low noise) and that must be operable at very high frequencies. The present invention enables a very compact design, thereby minimizing extraneous noise pickup. The device may be over-driven with a higher power supply than is commonly used in prior art VCOs; the over-driving provides for a higher transconductance gm from the PMOS device enabling higher gain. A center-tapped inductor is shunted to ground in a manner that does not reduce the inductor's quality factor Q.

Abstract: An integrated frequency source with an integrated frequency standard and an integrated frequency synthesizer is disclosed. A voltage-controlled oscillator in the frequency standard is eliminated with a resulting improvement in phase noise. A reference frequency in the frequency standard is provided directly to the frequency synthesizer. The integrated frequency source is put on frequency over temperature by storing reference frequency errors over temperature in a lookup table, measuring the temperature, and calculating in a microprocessor synthesizer control data that offsets the synthesizer to compensate for reference frequency errors.

Abstract: In a high-frequency variable attenuator for variably attenuating an input high-frequency signal in response to a control voltage to produce an output high-frequency signal, a reference voltage generating circuit generates a controllable reference voltage in response to the control voltage. Connected to the reference voltage generating circuit, an attenuating circuit attenuates the input high-frequency signal on the basis of the control voltage in reference with the controllable reference voltage to produce the output high-frequency signal.

Abstract: A directional coupler includes two non-radiative dielectric lines, each formed by a dielectric strip between flat conductive surfaces placed substantially parallel to each other, such that the two non-radiative dielectric lines are close to each other. The main transmission mode of electromagnetic waves at the frequency used is an LSE mode, the electromagnetic waves being propagated in the non-radiative dielectric lines. Therefore, the insertion loss due to mode switching in the coupling portion of the primary line and the secondary line which form the directional coupler can be reduced, and leakage of the electromagnetic waves from the gap between the primary line and the secondary line of the directional coupler when they are separated from each other can be suppressed.

Abstract: A 90 degree splitter which covers a wide frequency range of 1500 to 2500 Mhz in a small footprint of only 0.2 inches by 0.2 inches. This device does not use any capacitors which greatly simplifies the construction and lowers the cost in comparison to conventional splitters.