Abstract: A clad layer is provided as a multilayer structure made of an alternate laminate of 20 layers of Al0.2Ga0.8N 50 nm thick and 20 layers of Ga0.99In0.01N 20 nm thick. The clad layer about 1.4 &mgr;m thick has a low elastic constant because the clad layer is provided as a multilayer structure. In a laser diode, it is useful that another layer such as a guide layer requiring a band gap of aluminum gallium nitride (AlxGa1−xN 0<x<1) is provided as a multilayer structure made of aluminum gallium nitride (AlxGa1−xN 0<x<1) and gallium indium nitride (GayGa1−yN 0<y<1).

Abstract: A Group-III nitride semiconductor light-emitting diode having an electrically conducting silicon (Si) single crystal substrate having on an upper surface thereof at least a light-emitting part having a pn-heterojunction structure composed of a Group-III nitride semiconductor, which light-emitting part is stacked via an intermediate layer composed of a metal or a semiconductor, the single crystal substrate having a back surface electrode on a back surface thereof, a surface electrode on an upper surface of the light-emitting part and a perforated part formed by eliminating the Si single crystal substrate in a region exclusive of the back surface electrode on the back surface of the single crystal substrate and a method of manufacturing thereof are disclosed.

Abstract: A method and system are taught for a system comprising an LED package. The LED package may comprise an anode, a cathode coupled to the anode, an LED die coupled to the cathode and the anode, a lens coupled to the anode, and a viscous or silicone material located in a cavity defined by the lens, the cathode, and the anode. The viscous or silicone material may be a gel, a grease, a non-resilient material, or a non-liquid material. The method and system may further comprise a mounting device, wherein the lens is mechanically coupled to the mounting device in a socket, bayonet, or screwing like fashion. The method and system may further comprise an anode strip comprising an array of anodes utilized to form an array of the LED packages and a carrier strip comprising receiving devices to receive the array of LED packages. A portion of the lens may either be coated with or comprise light excitable material or the viscous material may comprise light excitable material, such that the system emits white light.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: A needless valve is described which avoids the suctioning problems of the prior needleless devices upon deactivation and which preferably provides a positive self-purging effect. The valve is self-purging at the end of an administration cycle, avoiding clogging of attached catheters or other devices, and ensures that substantially all of liquid received into the valve is delivered to the receiver. The valve is also extremely simple in design and easy to construct and assemble, since it consists of only three pieces. The valve has a base with a connector for fluid communication attachment to tubing or other device, a solid elongated fluid channeling rod, and an internal fluid flow conduit; a flexible hollow expandable and contractible plug fitting over and moveable along the rod; and a tubular housing fitting over the plug and attached to the base.

Abstract: A high electron mobility transistor photodetector includes an undoped GaAs buffer, a p-type GaAs layer positioned above the undoped GaAs buffer that is between 0.5 to 1 &mgr;m in thickness, an undoped low temperature GaAs layer positioned above the p-type GaAs layer, an undoped GaAs layer positioned above the low temperature GaAs layer, a layer of undoped InGaAs positioned above the undoped GaAs layer, a layer of undoped AlGaAs positioned above the layer of InGaAs, an n+ AlGaAs charge-suppling layer positioned above the layer of undoped AlGaAs, an n+ GaAs contact layer positioned above the n+ AlGaAs charge-supplying layer, and source and drain ohmic contacts positioned above the n+ GaAs contact layer. A negative bias voltage is applied to the p-type GaAs layer to sweep the holes from the photo-absorptive layer which greatly increases the speed and responsiveness of the device.

Abstract: The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain zone, together with the source zone and drain zone, extend to an n-conductive substrate. The source zone and the drain zone are surrounded by a p-conductive area.

Abstract: In the production of an IT-CCD including many photoelectric converters in columns and rows, vertical transfer CCDs for transferring signal charge accumulated in the photoelectric converters to a horizontal transfer CCD, and readout gate regions to control, for each photoelectric converter, readout operation of signal charge from the photoelectric converters to the vertical charge transfer CCDs; one joining channel is formed for each set of two vertical transfer CCDs to combine the CCDs with each other and hence a high-pixel-density solid-state image pickup device can be implemented using ordinary fine patterning technique.

Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.

Abstract: A storage node electrically connected to one of source/drain regions of a MOS transistor is formed along the side wall and the bottom wall of an opening provided through a silicon nitride film, a BPTEOS film and a TEOS film. The surface of this storage node is roughened. Thus, a semiconductor device having high reliability and a method of manufacturing the same are obtained.

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract: A method for providing semiconductor openings having a substantially straight wall or other desired etch profile. An etchable material layer is formed having target dopant levels or other etch rate varying characteristics to compensate for the characteristics of a selected etching process to achieve the desired etch profile. The etching process may also be varied to further match the characteristics of the etchable material layer.

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

Abstract: A capacitor useful with semiconductor devices and a method for forming such a capacitor is provided. The capacitor comprises a contact formed in a layer of an insulating material of a semiconductor device; a first electrode formed on the layer of insulating material, the first electrode contacting the contact and having a nodular shape; a layer of a dielectric material formed on the first electrode; and a second electrode formed on the layer of the dielectric material. Desirably, the dielectric layer of the capacitor is formed from a high dielectric constant material. In another embodiment, the capacitor includes a layer of a barrier material positioned between the contact and the first electrode.

Abstract: The capacitor related to the present invention has a lower electrode, a dielectric film provided on the lower electrode and made mainly of crystal containing at Ti, O and at least one element selected from the group consisting of Ba and Sr, and an upper electrode provided on the dielectric film, wherein the dielectric film includes a layer which contacts the upper electrode. In case the dielectric film which has a thickness of at least 5 nm and exhibits a first-order differential spectrum measured by means of Auger electron spectroscopy, and the in the first-order differential spectrum, a ratio A/B is at most 0.3, where A is the absolute value A of a difference between a third peak appearing near 420 eV and a fourth peak appearing at a higher energy level and near the third peak, and B is the absolute value B of a difference between a first peak appearing near 410 eV and a third peak appearing at a lower energy level and near the first level.

Abstract: A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source has source voltages above the critical voltage and no conducting channel forms under the gate. Another portion of the source has source voltages below the critical voltage, and thus a conducting channel forms under the gate for this portion of the capacitor. By varying either the gate voltage or the source voltages, the area of the gate that has a channel under it is varied, varying the capacitance. Separate source islands eliminate source current.

Abstract: A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions.

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: In a trench-gate semiconductor device, for example a cellular power MOSFET, the gate (11) is present in a trench (20) that extends through the channel-accommodating region (15) of the device. An underlying body portion (16) that carries a high voltage in an off state of the device is present adjacent to a side wall of a lower part (20b) of the trench (20). Instead of being a single high-resistivity region, this body portion (16) comprises first regions (61) of a first conductivity type interposed with second regions (62) of the opposite second conductivity type. In the conducting state of the device, the first regions (61) provide parallel current paths through the thick body portion (16), from the conduction channel (12) in the channel-accommodating region (15). In an off-state of the device, the body portion (16) carries a depletion layer (50).

Abstract: A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the body region under the source. The layer is used for influencing the conductibility of the source or the threshold voltage in the channel region. Breakdown currents and latch-up effects can thereby be prevented.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.

Abstract: A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.

Abstract: A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.

Abstract: A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch mask, forming an impurity layer in or on a bottom surface of the first trench, forming a second trench exposing a buried oxide layer in the SOI layer in the remainder of the isolation layer region except the portion thereof between the element region and the ground region, and forming an isolation layer by depositing an insulation layer over the SOI substrate having the first and second trenches. The impurity layer can be formed by depositing a SiGe single crystal layer in the bottom surface of the first trench. Also, the impurity layer can be formed by implanting ions in the bottom surface of the first trench.

Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Abstract: In a field effect semiconductor device in which switching is performed by a gate voltage inputted from outside via a gate resistance circuit for restricting charging and discharge currents flowing between an insulated gate and an emitter, the improvement comprises: an insulated gate electrode portion which is formed by a gate electrode pad and a gate electrode insulated from the gate electrode pad; the gate resistance circuit being inserted between the gate electrode pad and the gate electrode so as to be formed integrally with the insulated gate electrode portion; and the gate resistance circuit comprising a first gate resistance and a first series circuit connected to the first gate resistance in parallel and including a second gate resistance and a first diode such that an anode of the first diode is connected to the gate electrode.

Abstract: An n-type semiconductor layer, for example, is provided to be a drain region (1). A plurality of p-type diffusion regions (body regions) are formed regularly on the surface of the semiconductor layer. And an n-type diffusion region is formed, as a source (3), on the surface of each of the plurality of p-type body regions (2), so that a channel region (8) is formed in a part between the source and the drain regions for a transistor cell. On the surface of the transistor cells, provided is a gate electrode (5) via an insulator film (4), and this gate electrode is patterned in a certain shape by removing portions above where adjoining three or four of said cells are bordering on each other without including any part of said channel regions (8). Those portions are referred to as removed portions (10).

Abstract: A method of fabricates a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, a gate oxide layer above the substrate and word lines formed above the gate oxide layer comprises: forming a dielectric layer over the word lines and gate oxide layer, forming and pattern first photoresist layer over the dielectric layer, etching the dielectric layer, stripping the first photoresist layer, forming and pattern second photoresist layer over the dielectric layer to develop an opening area for ion implantation, ion implanting a code implant dopant through the opening area down into the substrate and stripping the second photoresist layer.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: A micromirror is fabricated in a substrate by defining a mirror platform on a first side of the substrate, defining an actuator structure corrected to the platform on a second side of the substrate, and then releasing the mirror platform for motion with the actuator. The actuator may be a comb drive structure having interdigitated movable finger electrodes connected to the mirror platform and stationary finger electrodes mounted on the substrate. The movable and stationary finger electrodes preferably are asymmetrical, and when activated, controllably move the mirror platform either horizontally or vertically with respect to the surface of the substrate. The comb drive structure may be connected at one of its ends to a torsional support beam secured to the substrate, for torsional motion of the mirror platform with respect to the substrate. Alternatively, the comb drive may be connected at both ends to spaced torsional support beams for vertical motion of the platform with respect to the substrate.

Abstract: Low-cost plastic cavity-up land-grid array packages and ball-grid array packages are provided, suitable for wire-bonded chips having micromechanical components. The packages feature a thermal heat spreader and a protective lid. The package structure disclosed is flexible with regard to materials and geometrical detail, and provides solutions to specific functions such as storage space for chemical compounds within the enclosed cavity of the package.

Abstract: The method for producing a micromechanical component includes the following steps: producing a semi-finished micromechanical component; producing openings and forming a cavity; sealing the opening with sealing lids; removing material on the top surface of the first membrane layer, the surface of the first membrane layer being exposed and planarized. The invention also relates to a micromechanical component which can be produced according to the above method and to its use in sensors such as pressure sensors, microphones, or acceleration sensors.

Abstract: The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.

Abstract: A device forming a high energy resolution integrated semiconductor &Dgr;E-E detector telescope is disclosed, in which is formed a very thin &Dgr;E detector portion (14) primarily fabricated from a first semiconductor wafer which is bonded/silicidized to a second semiconductor wafer forming an E detector portion (18). This &Dgr;E-E detector provides a well supported very thin &Dgr;E detector for high resolution. The very thin &Dgr;E detector portion bonded/silicidized to the E detector portion further provides between each other a buried metallic layer (16) acting as a contact common to the two detectors, which metal layer is thin and presents a low resistivity.

Abstract: An avalanche drift photodetector (ADP) incorporates extremely low capacitance of a silicon drift photodetector (SDP) and internal gain that mitigates the surface leakage current noise of an avalanche photodetector (APD). The ADP can be coupled with scintillators such as CsI(Tl), NaI(Tl), LSO or others to form large volume scintillation type gamma ray detectors for gamma ray spectroscopy, photon counting, gamma ray counting, etc. Arrays of the ADPs can be used to replace the photomultiplier tubes (PMTs) used in conjunction with scintillation crystals in conventional gamma cameras for nuclear medical imaging.

Abstract: A simple, low-cost package consisting of a plurality of charge-coupled devices (CCD) having a transparent cover integrated to the CCDs is described. Interconnecting wires having a fine pitch are defined on the cover away from the light sensitive area of the CCDs to provide enhanced wiring capability. The cover is constructed on the same semiconductor wafer containing the CCDs, which are preferably arranged in a matrix formation, allowing the wafer to be diced into individual chips having any desired number of CCDs, all of which are protected by the integrated transparent cover facing the light sensitive surface of the CCDs. This structure has the further advantage of reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is already in place. Dicping width control is achieved using oxide trench as an etch channel.

Abstract: Provided is a power module capable of driving an SR motor, giving a small size and high versatility and reducing a manufacturing cost. A switching element 1a and a diode element 2b which are to be connected to a P power wiring 5 are provided to form a first line on the band-shaped P power wiring 5, a switching element 1b and a diode element 2a which are to be connected to an N power wiring 6 are provided to form a second line aligned with the first line, and first band-shaped portions 41 and 44 of output terminals 3 and 4 and a band-shaped portion 61 of the N power wiring 6 are provided therebetween. The first band-shaped portions 41 and 44 and the band-shaped portion 61 have a two-layer structure with an insulating layer interposed therebetween. The switching elements 1a and 1b and the diode elements 2a and 2b are arranged alternately.

Abstract: A microelectronic structure with a low voltage part and high voltage part, such that the low voltage part is protected against the high voltage part and process of obtaining this protection. The structure includes at least one low-voltage element (2) and at least high-voltage element (4) formed on a semi-conductor substrate (6). According to the invention, at least one channel (18) is formed, passing through the low-voltage element and one semi-conductor zone is formed with doping opposite to that of the substrate, at least around the walls of the channel or channels and a contact point (24) is established in this zone. Application to smart power integrated circuits.

Abstract: An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a power source voltage and a grounding voltage formed between said first P-well region and said bottom N-well region. Thus it is not necessary to maintain a device region, to form a capacitance, to form wiring or maintain a wiring region as in a conventional MOS capacitance while it is possible to obtain a required decoupling capacitance.

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film is comprised of a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film.

Abstract: A sealing dielectric layer is applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin metal diffusion barrier layer without creating pinholes in the metal diffusion barrier layer. The sealing dielectric layer is a CVD deposited film having the composition SixCy:Hz.

Abstract: An anti-reflective coating material layer is provided that has a relatively high etch rate such that it can be removed simultaneously with the cleaning of a defined opening in a relatively short period of time without affecting the critical dimensions of the opening. A method of forming such a layer includes providing a substrate assembly surface and using a gas mixture of at least a silicon containing precursor, a nitrogen containing precursor, and an oxygen containing precursor. The layer is formed at a temperature in the range of about 50° C. to about 600° C. Generally, the anti-reflective coating material layer deposited is SixOyNz:H, where x is in the range of about 0.39 to about 0.65, y is in the range of about 0.02 to about 0.56, z is in the range of about 0.05 to about 0.33, and where the atomic percentage of hydrogen in the inorganic anti-reflective coating material layer is in the range of about 10 atomic percent to about 40 atomic percent.

Abstract: A semiconductor device includes a substrate, and the substrate is formed with a wiring pattern on its surface. The wiring pattern includes electrodes, wire-bonding (WB) pads and connecting portions for connecting the electrodes and the WB pads. The WB pads are so formed that the lengthwise directions thereof are in parallel or approximately in parallel to lines, in radiative form, extending from the center of a die-bonding (DB) area. Accordingly, if a chip having a first size is die-bonded within the DB area, bonding wires become approximately in parallel to the lengthwise directions of the WB pads. Even if a chip having a second size smaller than the first size but the same shape is die-bonded, the bonding wires are also in parallel to the lengthwise directions of the WB pads. Thus, since one substrate can be used regardless of the size of a chip, there is no need to prepare a plurality of wiring patterns for each size of chips.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.

Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on a opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.

Abstract: An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e.g., solder balls) that interface with the memory chip and each logic chip, or through a sequential logic-to-memory electrically conductive path that includes: a first conductive member electrically coupled to a logic chip; an electrically conductive via path through a circuitized substrate; and a second conductive member electrically coupled to the memory chip. The logic chips are electrically coupled to the substrate either directly through an interfacing solder interconnection from the logic chip to the substrate, or indirectly through the memory chip such that the memory chip is electrically coupled to the substrate by an interfacing solder interconnect. The electrical structure may be plugged into a socket of a backplane of a circuit card.