Abstract: A tool to be used with fifth wheels, comprising of a solid piece of material approximately seventeen inches and five centimeters in length and roughly three inches and five centimeters tall. With an angled front that allows easy use in situations involving a king pin of a commercial towing unit becoming stuck behind a fifth wheel. An indentation on the bottom allows for security to the frame of the towing unit and a safety bolt allows for locking protection.

Abstract: A belt reel assembly includes a main frame and a lever pivotally mounted to each other by an axle. The main frame has a first stop plate slidably mounted to selectively engage to ratchet that id mounted on the axle and the lever has a second stop plate mounted to drive the ratchet. A groove is defined in the main frame and has one side formed with a limiting side. The strain of the belt can reverse the axle to release the belt when the stop plate of the lever is moved within the groove. The ratchet drive the stop plate to abut the limiting side and then the ratchet is engaged to the stop plate of the main frame and stopping release the strain of the belt to accomplish the function of releasing the strain of the belt step by step.

Abstract: An apparatus for the controlled lowering to the ground of a cut portion of a tree includes a rope and an anchor having an arrangement of guiding protuberances, each guiding protuberance including a bearing surface frictionally engaging and redirecting the rope without the rope fully encompassing any portion of the anchor including any of the guiding protuberances. Three guiding protuberances define a triangular arrangement. Of the three, a first guiding protuberance is disposed in proximity to an intermediate guiding protuberance defining a segment of a rope path therebetween, and a second guiding protuberance is disposed in proximity to the intermediate guiding protuberance defining another segment of the rope path therebetween without the segments crossing. A mounting member is attachable to the tree and a guiding member is pivotally connected to the mounting member along a pivot axis and includes an arrangement of guiding protuberances generally extending to each side thereof.

Abstract: A lifting device comprises a rotatable pawl with a pawl arm held in a pawl sleeve. The pawl has an open position in which a rope may be freely adjusted in tightening or loosening directions, and a closed position in which the rope is lockably engaged between the pawl and the pawl sleeve. The pawl has a pawl arm against which the locked rope may be directed to rotate the pawl into an open position. The lifting device also includes a pulley for mechanical advantage, and a base for mounting to a surface. A preferred embodiment of the lifting device of the invention comprises a plurality of pulleys for additional mechanical advantage, and is pivotally attached to an overhead surface.

Abstract: A fence post with a quick connect latch for connecting a fence wire to it. The fence post is an elongated post (12) with a plurality of oblique studs (14) positioned in various combinations molded vertically on the fence post or connected together by a base bar (22) applied vertically to the fence post. Each oblique stud (14) protrudes outward, slanting, narrowing toward an outer edge (16) where a pin hole (18) is located. Further including a pin (20) elongated in shape and bent at one end.

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions.

Abstract: A field emission display that is simple to manufacture in a large screen size and that provides improved display characteristics, includes first and second substrates provided opposing one another with a predetermined gap therebetween; a plurality of gate electrodes formed on a surface of the first substrate opposing the second substrate, the gate electrodes being formed in a striped pattern; an insulation layer formed on the first substrate covering the gate electrodes; a plurality of cathode electrodes formed on the insulation layer in a striped pattern to perpendicularly intersect the gate electrodes; a plurality of surface electron sources formed along one long edge of the cathode electrodes; focusing units provided on the cathode electrodes for controlling the emission of electron beams from the surface electron sources; an anode electrode formed on a surface of the second substrate opposing the first substrate; and a plurality of phosphor layers formed on the anode electrode.

Abstract: A superconducting structure that can operate, for example, as a qubit or a superconducting switch is presented. The structure includes a loop formed from two parts. A first part includes two superconducting materials separated by a junction. The junction can, for example, be a 45° grain boundary junction. The second part can couple the two superconducting materials across the junction. The second part includes a superconducting material coupled to each of the two superconducting materials of the first part through c-axis junctions. Further embodiments of the invention can be as a coherent unconventional superconducting switch, or a variable phase shift unconventional superconductor junction device.

Abstract: In an electrically conductive organic compound, a side chain portion simultaneously exhibiting refractive index anisotropy and a conjugated system electrical conductivity is bonded to a main chain portion exhibiting &pgr; conjugated system electrical conductivity. The electrically conductive organic compound is used in the production of a constituent element for electronic devices.

Abstract: There is provided a susceptor with a built-in electrode and a manufacturing method therefor, in which there is no danger of corrosive gas or plasma or the like penetrating to the inside of the substrate, which has excellent corrosion resistance and plasma resistance, in which nonconductivity under high temperatures is improved, and in which leakage current does not occur.

Abstract: An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure.

Abstract: An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure.

Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A method for bonding diamond heat distribution structures to integrated circuit packages using optical contacting. In one embodiment, a heat spreader comprising diamond slab has a flat contact surface which is polished to a high degree of smoothness. An integrated circuit's package also has a flat contact surface which is polished to a high degree of smoothness. The contact surfaces of the diamond slab and the package are thoroughly cleaned and are then placed in contact with each other, establishing an optical contact bond between them. In one embodiment, the contact surfaces of the diamond and package which are to be bonded together are first polished, then a layer of an intermediate material such as silicon carbide is deposited on the polished surfaces. The silicon carbide layers on the contact surfaces are cleaned and placed in contact with each other to establish an optical contact bond.

Abstract: A quantum well structure having an indium gallium arsenide phosphide (InGaAsP) quantum well active region has a low temperature grown indium phosphide (LT-InP) cap layer grown on it. Defects in the cap layer are intermixed into the quantum well active region by rapid thermal annealing to produce a blue shift in the active region. The blue shift increases as the growth temperature of the LT-InP cap layer decreases or as the phosphine flow rate during production of the LT-InP layer increases.

Abstract: The invention provides a light emitting device with uniform light emission, wherein the light emitting device comprises an alloyed film formed on the p-type semiconductor layer. The alloyed film has a structure of long-range order superlattice, and is formed by annealing a multi-metal layer. The alloyed film has superior thermal conductivity and superior electrical conductivity. Thus, the current is uniformly applied to the entire p-type semiconductor layer, and the light emitting device emits uniform light.

Abstract: The light-emitting thyristor matrix array may be provided in which wiring are crossed without being electrically connected to each other. An array of three-terminal light-emitting thyristors in which a substrate is used as a common cathode or anode is divided into blocks n by n (n is an integer≧2), gates of n light-emitting thyristors included in each block are separately connected to n gate-selecting lines, and anodes or cathodes of n light-emitting thyristors included in each block are commonly connected to one terminal, respectively.

Abstract: An optical data storage medium containing a preferably transparent substrate which has optionally already been coated with one or more reflecting layers and onto the surface of which a photorecordable information layer, optionally one or more reflecting layers, and optionally a protective layer or an additional substrate or a top layer are applied, which data storage medium can be recorded on and read using blue or red light, preferably laser light, wherein the information layer contains a light-absorbing compound and optionally a binder, characterized in that at least one diaza hemicyanine dye is used as the light-absorbing compound.

Abstract: A method and apparatus for making sealed or closed microchannel structures in semiconductor wafers is disclosed. Two substrates, preferably a transparent cover substrate and an opaque base substrate, are used. The transparent cover substrate is placed over the opaque base substrate. By using the characteristics of the transparent material, electromagnetic waves are directed through the transparent cover substrate to the opaque base substrate. The laser beam heats the base substrate to its phase change temperature, melting the surface of the base substrate that is in contact with a surface of the cover substrate, coalescing the surfaces together and forming a sealed microchannel structure.

Abstract: This invention provides a novel application of a semiconductor light emitting element or light emitting chip preferably disposed on the underside surface of a clear or translucent substrate. In addition connecting wires leading from said element to the perimeter of the substrate connecting to contact pads leading to a circuit board. The conductors are deposited on the substrate using thin film technology. Preferably the light emitting element is packaged in a flip chip having connecting bumps only on one side.

Abstract: The present invention provides a solid-state image sensor wherein the color shading is decreased, and/or a solid-state image sensor wherein the shading effect is outstanding. Moreover, the invention provides a digital camera having the solid-state image sensor. The solid-state image sensor of the present invention has color filters and/or apertures of a light blocking layer, and the center of the color filters and/or the center of the apertures of the light blocking layer is offset with respect to the center of a light-receiving part, in the direction to the center of a valid cell area. In each photodetecting cell of a preferred solid-state image sensor, micro-lenses are further placed on the light-receiving side of the solid-state image sensor, and preferably, the center of the micro-lens is similarly offset with respect to the center of the light-receiving part. Also, the digital camera is mounted with an above-described solid-state image sensor.

Abstract: A method of integrating a topside optical device, having electrical contacts on a top side, with an electronic chip having electrical contacts on a connection side, involves creating a trench, defined by a wall, from the top side of a wafer containing the topside optical device into a substrate of the wafer, making a portion of the wall conductive by applying a conductive material to the portion; and thinning the substrate to expose the conductive material.

Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p- type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: A light-emitting thyristor matrix array in which the area of a chip may be decreased is provided. A plurality of three-terminal light-emitting thyristors are arrayed in one line in parallel with the long side of the chip, a plurality of bonding pads are arrayed in one line in parallel with the long side of the chip. Thereby, the area of the chip becomes smaller.

Abstract: A direct-wafer-bonded, double heterojunction, light emitting semiconductor device includes an ordered array of quantum dots made of one or more indirect band gap materials selected from a group consisting of Si, Ge, SiGe, SiGeC, 3C-SiC, and hexagonal SiC, wherein the quantum dots are sandwiched between an n-type semiconductor cladding layer selected from a group consisting of SiC, 3C-SiC, 4H-SiC, 6H-SiC and diamond, and a p-type semiconductor cladding layer selected from a group consisting of SiC, 3C—SiC, 4H—SiC, 6H—SiC and diamond. A Ni contact is provided for the n-type cladding layer. An Al, a Ti or an Al/Ti alloy contact is provided for the p-type cladding layer. The quantum dots have a thickness that is no greater than about 250 Angstroms, a width that is no greater than about 200 Angstroms, and a center-to-center spacing that is in the range of from about 10 Angstroms to about 1000 Angstroms.

Abstract: The present invention provides a semiconductor device with reducing dislocation density. The semiconductor device includes multiple nucleuses between a substrate and an AlGaInN compound semiconductor. The dislocation density that is induced by crystal lattice differences between the substrate and the AlGaInN compound semiconductor is significantly reduced and the growth of the AlGaInN compound semiconductor is improved.

Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.

Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.

Abstract: A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate electrode, and a second MOS transistor including a gate electrode having a gate width Li smaller than the gate width Le of the gate electrode of the first MOS transistor and a second gate post oxide film formed on a circumferential side wall of the gate electrode and having a portion differing in thickness from the first gate post oxide film.

Abstract: A seal ring structure having an electrostatic discharge protection function, suitable for a conductive first-type substrate which has a bias provided by a second power source. The new seal ring scheme including a conductive second-type doped diffusion region located on the first-type substrate; and a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.

Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.

Abstract: A method is provided of forming a low resistance contact between a poly-silicon resistor of an integrated circuit and a conducting material, the method comprising the steps of:

Abstract: Semiconductor structures with one or more through-holes are disclosed. A feed-through metallization process may be used to seal the through-holes hermetically.

Abstract: In a semiconductor device for treating signals of frequency not less than 800 MHz, a minimum thickness of an electrically conductive wire connecting a semiconductor electric circuit in the semiconductor device to an electric member other than the semiconductor device is determined along the following formula: 1 2 * 2 ω ⁢   ⁢ μ ⁢   ⁢ κ < h

Abstract: A thrombus filter configured for placement in within a blood vessel lumen defined by a blood vessel wall. Methods and devices for selectively removing the thrombus filter when the presence of a filter in the vascular system is no longer desired. The thrombus filter includes a first strand formation, a second strand formation, and a joined portion.

Abstract: A variable transconductance amplifier including a variable attenuator stage coupled to a transconductance stage. The variable attenuator includes first and second differential to single-ended transconductance stages, each biased by a current device. The variable attenuator receives a differential input voltage signal and develops a current signal. At least one reactive element is coupled between the pair of differential to single-ended transconductance stages. The transconductance stage includes first and second differential pairs each having first and second control terminals and first and second output terminals. The first and second differential pairs are coupled to the first and second differential to single-ended transconductance stages, respectively, of the variable attenuator. The output terminals of the first and second differential pair are cross-coupled to develop a differential output current signal.

Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.

Abstract: A 2-bit non-volatile memory (NVM) transistor having a pair of isolated floating gate electrodes is provided. One of the floating gate electrodes is located over a first source/drain region, and a first adjacent end of a channel region. The other floating gate electrode is located over a second source/drain region and a second adjacent end of the channel region. A control gate extends over both floating gate electrodes and a centrally located portion of the channel region. The floating gate electrodes are independently programmed and independently read, thereby enabling the NVM transistor to effectively store 2-bits of data.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: A semiconductor device and method of manufacture. A liner composed of a high-K material having a relative permittivity of greater than 10 is formed adjacent at least the sidewalls of a gate. Sidewall spacers are formed adjacent the gate and spaced apart from the gate by the liner. The liner can be removed using an etch process that has substantially no reaction with a gate dielectric of the gate.

Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.

Abstract: A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

Abstract: In a semiconductor memory device having a capacitor layer comprising a dielectric film or a ferroelectric film, as an interlayer insulation film formed between the capacitor and a wiring layer formed at the upper part thereof or an insulation film which covers the wiring layer, a multilayered film is used which consists of a first insulation film and a second insulation film laid upon the other; the former being a lower layer and being formed of an organic film, and the latter being an upper layer and being formed of a hard-mask material.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated circuit includes a semiconductor die; a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die; and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells. The memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Abstract: A memory cell array of the non-volatile semiconductor memory device includes a plurality of gate electrodes provided in the row direction, bit lines D1, D2, D3, D4 and source lines S1, S2, S3, S4 provided in the column direction, and memory cells each having a floating gate. The source lines are separately provided in at least two wiring layers. The source line S2 provided in the first layer overlaps the source line S1 provided in the second layer when viewed two-dimensionally. This array structure reduces the dimension of the memory cell array in the row direction, thereby enabling significant reduction in area.

Abstract: A semiconductor memory device having a high quality storage node electrode preventing for example connection failure between a contact plug and the storage node electrode, including first insulating films formed on a substrate, storage node contact holes formed in the first insulating films, storage node contact plugs buried in the storage node contact holes, a storage node electrode formed connected to the storage node contact plug, and a second insulating film formed above the first insulating film at a gap of the storage node electrode, the storage node electrode and the storage node contact plug being connected at least at part of the top surface and the side surface of the storage node contact plug or the storage node electrode and the second inter-layer insulating film being in contact at least at part of the top surface and the side surface of the second insulating film, and a method for producing the same.