Abstract: It is an object of the invention to provide a variable capacitor constituted such that, even when an external control voltage is applied, a stable dielectric constant of the dielectric layer can be obtained. A variable capacitor constituted such that a dielectric layer whose dielectric constant is changed by the application of an external voltage is held between an upper electrode layer and a lower electrode layer, wherein a plurality of capacitance-producing regions a, b are connected to each other.

Abstract: The present invention provides a novel erase method and apparatus for flash memory cells, with special emphasis on source-side injection cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an “internal P-well” within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive. With experimental data, it is demonstrated that better “magnitude balance” has been achieved for the highest erase voltages of opposite polarities.

Abstract: A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode.

Abstract: Irrespective of a specification of the controller, a plurality of TFTs are formed for the controller on a substrate in advance. Then, in accordance with a design of the controller, connection is achieved among sources, drains, and gates, which serve as three terminals in each of the plural TFTs, appropriately through a wiring formed on a layer different from the one where the plural TFTs are formed, so that the controller with a desired specification is formed. At this time, it is not required to use all the TFTs arranged on the substrate and some TFTs may remain unused depending on the specification of the controller.

Abstract: A flash memory structure and its fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material (polysilicon), are processed for formation of a pre-interpoly dielectric treatment layer over the first polysilicon material. The pre-interpoly dielectric treatment layer being a solid material formed by a chemical reaction formed for purposes of improving the reliability of an interpoly dielectric member and results in changing the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The pre-interpoly dielectric treatment layer is formed by exposing the polysilicon stacks to a selected one of at least three ambient reagent gases. The selected gaseous ambient and exposure of the polysilicon stacks being performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.

Abstract: An insulated gate semiconductor device includes a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the first base layer a channel electrically connecting between the source layer and the second base layer, wherein the injection efficiency of hole current from said drain layer is 0.27 in maximum.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: A semiconductor device is provided in which data is hardly destroyed owing to a pass gate leakage even if it is used as a transfer gate of a memory. Partial depletion type transistors formed on a second silicon layer are used for a memory circuit. The partial depletion type transistors formed on the second silicon layer are electrically connected to each other at a body region. Accordingly, an electrode of the transistors formed on the second silicon layer can be fixed at an electrode of the body region by a well contact so that the pass gate leakage hardly occurs. Accordingly, even if the transistors are used for the transfer gate of the memory, there is an advantage that information of cell data can be held with certainty although the transistors are fabricated using an SOI technique. The full depletion type transistors formed on a first silicon layer are used for a logical circuit.

Abstract: Single crystal silicon is graphoepitaxially grown using a step formed on a substrate as a seed by a catalyst PVD process or the like, and the obtained single crystal silicon layer is used for a dual gate type MOSTFT in an electro-optical apparatus such as a display section-peripheral driving circuit integration type LCD.

Abstract: An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad.

Abstract: A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit, an output-signal-fixing circuit and an internal circuit. The output-signal-fixing circuit includes a first capacitor and a second capacitor and fixes an output signal from a second pre-buffer circuit at an “L” level (low voltage) even when an output from the internal circuit is in a floating state. During an ESD test, since an output signal from the second pre-buffer circuit is fixed at an “L” level (low voltage) by the output-signal-fixing circuit, the NMIS transistor is in an OFF state. In this manner, a surge current is prevented from flowing locally into the NMIS transistor.

Abstract: A thin film semiconductor device includes a gate electrode insulator formed through high-heat oxidization of a semiconductor film. The high-heat oxidization of semiconductor film is carried out, in the process of crystallization or recrystallization of non-single-crystalline semiconductor thin film on a base layer, by irradiating predetermined areas of the thin film which is implanted with oxygen ion before irradiation, to convert such areas to oxidized areas, and these areas are processed to gate electrode insulators of electric circuit units in the thin film semiconductor device.

Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region . P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.

Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.

Abstract: An Optical Sub-Assembly housing structure for an optical transceiver module includes a plastic housing holding the light source unit on the inside, the housing having a tubular front coupling portion adapted to hold an optical fiber cable, the tubular front coupling portion having a tapered front opening for guiding the inserted optical fiber cable into position, and a longitudinal slot that makes the tubular front coupling portion deformable for high precision positioning and re-connection performance of the inserted optical fiber cable.

Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 &mgr;m. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm2/s at 250° C. and a thickness of less than 1.5 &mgr;m. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.

Abstract: An LDMOS device is made on a semiconductor substrate 112. It has an N+ source and drain regions 120, 132 are formed within a P well region 122. An interlevel dielectric layer 140 encapsulates biased charge control electrodes 142a and they control the electric field within the area of the drift region 14 between P-base 122 and the N drain region 132 to increase the reverse breakdown voltage of the device. This permits the user to more heavily dope the drift region and achieve a lower on resistance.

Abstract: A semiconductor device having a trench isolation region including an anti-oxidative liner formed to be thin enough to minimize etch wastage caused by a wet etching solution according to a wet loading effect, and a trench isolation method of forming the same. The semiconductor device includes a silicon substrate and a trench isolation region formed in the silicon substrate. A silicon epitaxial growth layer contacts the silicon substrate at a bottom surface of the trench isolation region and fills the lower half of the trench isolation region. A first oxide layer has an L-shaped cross-section and extends from a sidewall of the trench isolation region to a portion of the bottom surface of the trench isolation region. An anti-oxidative liner has an L-shaped cross-section, and extends between the first oxide layer and the silicon epitaxial growth layer, with its inner surface contacting the silicon epitaxial growth layer.

Abstract: Disclosed is a capacitively coupled bridge circuit for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high-and low-voltage sections by using a capacitor. Also disclosed is the use of the invention in an inplantable cardiac defibrillator.

Abstract: Within both a microelectronic fabrication and a method for fabricating the microelectronic fabrication, there is employed at least one fuse layer electrically connected with a series of patterned conductor layers separated by a series of dielectric layers, where the at least one fuse layer is formed at a level no lower than a highest of the series of patterned conductor layers within the microelectronic fabrication. When formed within the context of the foregoing constraint, there is provided enhanced access for actuation of the at least one fuse layer within the microelectronic fabrication.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A semiconductor apparatus includes a capacitor having a substrate, a conductive element and an insulator. The insulator comprises a substantially monocrystalline material having a relatively high dielectric constant. The semiconductor apparatus may further include a supplemental layer having a depletion zone, suitably comprised of a high-resistivity semiconductor material, for forming a voltage-variable capacitor. To facilitate the growth of the insulator and/or other layers, the various layers are suitably lattice matched. Further, the apparatus may include one or more interface layers to facilitate lattice-matching of the various layers.

Abstract: A piezoelectric element for actuating a mechanical component, is proposed in which, with a multilayer structure of piezoelectric layers, the inner electrodes disposed between them can be subjected to an electrical voltage. Since the piezoelectric layers with the inner electrodes function like capacitors, a shunting resistor for a requisite electrical discharge is formed, preferably in the head or foot part, by forming resistor tracks out of a resistor layer.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A stress-balancing layer formed over portions of a spring metal finger that remain attached to an underlying substrate to counter internal stresses inherently formed in the spring metal finger. The (e.g., positive) internal stress of the spring metal causes the claw (tip) of the spring metal finger to bend away from the substrate when an underlying release material is removed. The stress-balancing pad is formed on an anchor portion of the spring metal finger, and includes an opposite (e.g., negative) internal stress that counters the positive stress of the spring metal finger. A stress-balancing layer is either initially formed over the entire spring metal finger and then partially removed (etched) from the claw portion, or selectively deposited only on the anchor portion of the spring metal finger. An interposing etch stop layer is used when the same material composition is used to form both the spring metal and stress-balancing layers.

Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.

Abstract: A semiconductor packaging structure mainly has a lead frame with a die pad and a plurality of leads, a wall portion formed by molding compound positioned around a periphery of the lead frame, a chip mounted on the die pad and electrically connected with the plurality of lead via gold wires, and a cover mounted on the wall portion to enclose the chip. An interval is defined between the die pad and the plurality of leads for filling with an isolating resin, the interval further communicates with multiple gaps and each gap is defined between two adjacent of the plurality of leads, wherein each gap is also filled with the isolating resin.

Abstract: A leadframe for use in a leadless package (a semiconductor device) such as a quad flat non-leaded package (QFN) includes a base frame having a die-pad demarcated severally to correspond to each semiconductor element to be mounted thereon and a plurality of leads arranged around the corresponding die-pad, and an adhesive tape attached to the base frame so as to cover one surface side of each die-pad and the plurality of leads arranged around the corresponding die-pad. The plurality of leads corresponding to each die-pad extend with a comb shape from the corresponding die-pad to an outward direction, with being separated severally from the die-pad, inside a region to be ultimately divided into a semiconductor device. The leadframe further includes a plurality of support bars severally linked to each die-pad. The support bars are supported by the adhesive tape, and extend close to a peripheral portion of the region to be ultimately divided into the semiconductor device.

Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Abstract: The invention relates to an electronic component (2) with at least one semiconductor chip (4) and a flat chip carrier (6) assigned to the at least one semiconductor chip, electrical connections between contact areas (43) on an active chip surface (41) of the semiconductor chip and contact terminal areas (63) on an upper side (61) of the chip carrier being formed by means of strips (81) of material which can undergo microstructuring and are provided with an electrically conductive coating. The invention also relates to a method for producing the electronic component (2).

Abstract: A structure that is constituted by disposing a laminate film and a collector rubber with a metal terminal plate interposed therebetween and a structure that is constituted by disposing a laminate film and a collector rubber with a metal terminal plate interposed therebetween are disposed so as to sandwich a fundamental cell that is constituted by disposing a positive electrode layer and a negative electrode layer, respectively, on surfaces of a separator, the laminate films are fusion bonded at peripheries thereof, and thereby the fundamental cell is sealed in a package cell. In the laminate film, a window portion or an opening is disposed, and a metal terminal plate is partially exposed and used as an external connection terminal. Owing to this configuration, a laminate film packaged storage device in which sealing properties and the volume efficiency are improved can be provided.

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Abstract: A semiconductor device comprising integrated circuit elements realized by means of a stack of layers of semiconductor materials provided on a substrate of semiconductor material and comprising means for preventing the pollution of the circuit elements and of the substrate by hydrogen originating from their environment is characterized in that said means are formed by a layer of a material which absorbs hydrogen (or hydrogen getter) (10), which forms a pattern which is integrated with the circuit elements and whose outer surface (11) is exposed and in contact with the environment.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of the first semiconductor device, and positioning a second semiconductor device over the first semiconductor device and a portion of at least one discrete conductive element protruding thereabove. The adhesive material may be applied to a surface of the first semiconductor device prior to positioning the second semiconductor device thereover, or introduced between the first and second semiconductor devices. Upon curing, the predetermined volume of adhesive material spaces the first and second semiconductor devices a predetermined distance apart from one another. Additional semiconductor devices may also be added to the assembly. The first semiconductor device may be associated with a substrate. Semiconductor device assemblies and packages that are at least partially fabricated in accordance with the method are also disclosed.

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Abstract: A semiconductor device includes a resin housing provided with a functional part, a wire pattern made of a conductive material and molded in the resin housing, a part of the wire pattern being exposed from the resin housing, an electronic part connected with the wire pattern in a state where the electronic parts is molded in the resin housing, and a semiconductor element connected to the part of the wire pattern being exposed from the resin housing. The semiconductor element provides a designated function in cooperation with a functional part of the resin housing.

Abstract: An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28′, 30′) contained within two metal layer (M6′, M7′). The bus grid is located within each of a plurality of contiguous rectangular regions (32′), which are defined by electrical contacts (12′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASIC chip.

Abstract: A leadframe used for a leadless package (a semiconductor device) such as a quad flat non-leaded package (QFN) includes a die-pad portion disposed in a center of an opening defined by a frame portion, and a plurality of lead portions extending from the frame portion toward the die-pad portion in a comb shape. A lead width of a portion along a circumference of a region to be ultimately divided as a semiconductor device, of each of the lead portions, is formed narrower than that of the other portion of the corresponding lead portions. In the leadframe, a plurality of die-pad portions are disposed, the frame portion is provided so as to surround each of the die-pad portions, and a plurality of lead portions corresponding to each of the die-pad portions extend from the frame portion surrounding the corresponding die-pad portion toward the corresponding die-pad portion. Moreover, an adhesive tape is attached to one surface of the leadframe.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: An interconnect component comprises a compliant layer having a first surface and a plurality of electrically conductive leads having first ends and extending through the compliant layer. The first ends extend generally parallel to said first surface.

Abstract: A semiconductor chip packaging device including a semiconductor chip, a heat spreader and a metal layer. The heat spreader is provided above the semiconductor chip, and the metal layer is provided between the heat spreader and the semiconductor chip to bond the heat spreader and the semiconductor chip without using a heat conducting adhesive.

Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

Abstract: The electronic circuit unit of the present invention includes first and second insulating substrates on respective surfaces of which wiring patterns are formed, and thick-film passive elements formed on the surfaces of the first and second insulating substrates in a state in which they are connected to the wiring patterns, wherein the first and second insulating substrates are disposed vertically opposite to each other, and the wiring patterns provided on the first and second insulating substrates are connected through metallic bumps provided between the first and second insulating substrates. With this construction, since the first and second insulating substrates can be disposed vertically, a small-sized electronic circuit unit can be provided which is smaller in a width direction than conventional ones.