Patents Issued in April 24, 2003
  • Publication number: 20030075708
    Abstract: A positive radiation-sensitive composition comprising:
    Type: Application
    Filed: May 14, 2002
    Publication date: April 24, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventor: Kunihiko Kodama
  • Publication number: 20030075709
    Abstract: Novel ultraviolet absorbing compounds that are liquid in nature, are extremely low in color (and thus permit use without the concomitant necessity of adding large amounts of other coloring agents to combat such discoloring), and are highly effective in providing protection in wavelength ranges for which previous attempts at low-color ultraviolet absorbers have failed are provided herein. Such compounds provide such excellent, inexpensive, and beneficial protection from ultraviolet exposure within various media, including, but not limited to, clear thermoplastics. The particular compounds are generally polymeric in nature including various chain lengths of polyoxyalkylenes thereon and are liquid in nature to facilitate handling and introduction within the target media. In addition, such ultraviolet absorbers also exhibit extremely low migratory properties thereby providing long-term protective benefits to the target media as well.
    Type: Application
    Filed: August 21, 2001
    Publication date: April 24, 2003
    Inventors: Todd D. Danielson, Xiaodong E. Zhao, Mary E. Mason, Daniel M. Connor, Eric B. Stephen, Jason D. Sprinkle, Jusong Xia
  • Publication number: 20030075710
    Abstract: The present invention 10 discloses a special purpose tool for removing control arms 18 from ball joint sockets 24 of vehicles 20. The present invention comprises an elongated handle 22 consisting of steel tubing along with a front end piece 16 made from steel round stock being offset with member 30 from the handle 22. Also a U-shaped bracket 28 is welded to the front end piece wherein the bracket has a hook 34 with a point 38 on the hook for contacting various structures of the vehicle 20. The point 38 of the hook, the front tip 36 and the handle 22 all lie in a single plane so that the tool will not rotate and slip off the work piece. The present invention can also have variously shaped surfaces on the point 38 of the hook and the front tip 36 for contacting various structures on a vehicle.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventor: Henry Sim
  • Publication number: 20030075711
    Abstract: An apparatus includes a sleeve comprising a nub, the sleeve sized to receive a bar. The apparatus further includes a movable spindle with a bracket. The bracket is sized to fit over either of the bar and the nub.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventors: Robert D. Cook, Thomas H. Kessler
  • Publication number: 20030075712
    Abstract: A fence assembly includes at least one frame unit and a lamp assembly. The frame unit is formed integrally from plastic, and includes a plate body and a peripheral flange. The plate body includes at least one first post portion and at least one second post portion that forms an angle with the first post portion. The peripheral flange extends rearwardly from a periphery of the plate body such that the plate body and the peripheral flange cooperate to confine a receiving space at a rear surface of the plate body. The lamp assembly includes at least one lamp socket secured on the plate body, at least one light bulb mounted on a corresponding lamp socket, and a power cord connected to the lamp socket. The power cord is disposed in the receiving space and is adapted to be connected to a power source.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventor: Chang-Yuan Lin
  • Publication number: 20030075713
    Abstract: A heterojunction bipolar transistor is provided with a graded band gap layer between a base and subcollector region. The graded band gap layer minimizes the surface leakage current path between the base and subcollector.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventors: Rajashekhar Pullela, Mark Rodwell
  • Publication number: 20030075714
    Abstract: An organic ELECTROLUMINESCENCE device exhibiting a minimal change in the color purity (CIE chromaticity coordinates) even if there is some fluctuation in the optical path length, and a method of manufacturing such an organic EL device are provided.
    Type: Application
    Filed: July 25, 2002
    Publication date: April 24, 2003
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Kenichi Fukuoka, Mitsuru Eida
  • Publication number: 20030075715
    Abstract: The thin film transistor (10) comprises a source region (14), a drain region (15), a channel forming region (16) between the source and drain regions, and a gate electrode (12). In this thin film transistor 10, the channel forming region (16) is composed of an organic compound having a radical.
    Type: Application
    Filed: August 29, 2002
    Publication date: April 24, 2003
    Applicant: NEC Corporation
    Inventors: Masaharu Satoh, Kentaro Nakahara, Jiro Iriyama, Shigeyuki Iwasa, Yukiko Morioka
  • Publication number: 20030075716
    Abstract: A semiconductor device includes a first terminal which receives a signal within a predetermined potential range in a first operation mode, and receives a potential higher above the predetermined potential range in a second operation mode, a high potential detection circuit which is connected to the first terminal, and detects the high potential to generate a high potential detection signal, a second terminal which receives a command signal, a latch circuit which latches the command signal supplied to the second terminal in response to the high potential detection signal, and a third terminal which resets the latch circuit in response to a signal within the predetermined potential range supplied from an exterior of the device.
    Type: Application
    Filed: July 24, 2002
    Publication date: April 24, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Kazuhiro Kitazaki
  • Publication number: 20030075717
    Abstract: The present invention provides a semiconductor element comprising a semiconductor junction composed of silicon-based films, the element being characterized in that at least one of the silicon-based films contains a microcrystal, and microcrystal located in at least one interface region of the silicon-based films containing the microcrystal has no orientation property. Further, the present invention provides a semiconductor element comprising a semiconductor junction composed of silicon-based films, wherein at least one of the silicon-based films contains a microcrystal, and the orientation property of the microcrystal in the silicon-based film containing the microcrystal changes in a film thickness direction of the silicon-based film containing the microcrystal.
    Type: Application
    Filed: March 8, 2002
    Publication date: April 24, 2003
    Inventors: Takaharu Kondo, Shotaro Okabe, Masafumi Sano, Akira Sakai, Ryo Hayashi, Shuichiro Sugiyama
  • Publication number: 20030075718
    Abstract: A plurality of gate lines and a plurality of data lines intersecting the gate lines to define a display area are formed on an insulating substrate including a display area and a surrounding area. On the surrounding area, a gate driving circuit connected to the gate lines and a logic circuit for VI interposed between the gate driving circuit and the gate line and having several first to third NOR gates are formed. A first input terminal of the first NOR gate of the logic circuit for VI is connected to an output terminal of the gate driving circuit, and a second input terminal thereof is connected to a CON1 terminal, and an output terminal thereof is connected to a first input terminal of the second or the third NOR gate. A second input terminal of the second NOR gate is connected to a CON2 terminal and an output terminal thereof is connected to the gate lines in odd number.
    Type: Application
    Filed: June 3, 2002
    Publication date: April 24, 2003
    Inventors: Yong-Kyu Jang, Won-Kyu Lee, Jin Jeon
  • Publication number: 20030075719
    Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 24, 2003
    Inventor: Saptharishi Sriram
  • Publication number: 20030075720
    Abstract: An organic light-emitting device includes a substrate, an anode, a cathode, disposed between the anode and the cathode is an electroluminescent medium including, in sequence: a hole-transporting layer; an interface layer; a light-emitting layer; and an electron-transporting layer. The interface layer comprises a compound having an ionization potential greater than that of the organic compound of the hole-transporting layer, and an energy bandgap equal to or greater than that of the organic compound of the light-emitting layer. Wherein the thickness of the interface layer is in the range of 0.1 nm˜5 nm. The interface layer provides more balanced carrier recombination in the light-emitting layer, and achieves higher luminance efficiency.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 24, 2003
    Applicant: Eastman Kodak Company
    Inventors: Liang-Sheng Liao, Joseph K. Madathil, Kevin P. Klubek, Ching W. Tang
  • Publication number: 20030075721
    Abstract: A color tunable pixel (100) includes a cholesteric liquid crystal (110). The helical pitch of the cholesteric liquid crystal (110) is controlled by applying electrical fields (202, 302) of varying strength and/or frequency perpendicular to an initial helical axis (H) of cholesteric liquid crystal (110) in order to shift the hue of light reflected by the cholesteric liquid crystal (110). The reflectivity of the cholesteric liquid crystal (110) may be controlled by applying an electric field (402) perpendicular to the initial helical axis (H) at a frequency at which the cholesteric liquid crystal (110) exhibits a negative dielectric anisotropy. Alternatively the visible light reflectivity may be controlled by applying an electric field to shift the reflectance of the cholesteric liquid crystal (110) into the infrared portion of the spectrum, or in another embodiment by allowing the cholesteric liquid crystal (110) to revert to an ultraviolet reflected state.
    Type: Application
    Filed: October 18, 2001
    Publication date: April 24, 2003
    Inventor: Zili Li
  • Publication number: 20030075722
    Abstract: The present invention relates to a collimator assembly for use in an optical switch. The collimator assembly includes an integrated LED/photodiode plane disposed in a dual microlens array. The integrated LED/photodiode plane results in a relatively simple way to manufacture high port count collimator arrays with integrated monitoring capabilities. The LED/photodiode plane can be readily produced using standard electronics manufacturing technology.
    Type: Application
    Filed: March 15, 2002
    Publication date: April 24, 2003
    Applicant: Corning, Inc.
    Inventors: Christopher P. Brophy, Marc G. Brun, Mark F. Krol
  • Publication number: 20030075723
    Abstract: The present invention relates to radiation, preferably light emitting, devices with a high radiation emission efficiency and to fabricating these as small devices in an array of such devices. In one embodiment, the emitting devices can be placed in dense arrays. In another embodiment, outcoupling efficiency of the devices is improved, which leads to a reduced power consumption for a given radiation output power. In another embodiment, the speed of the radiation is increased, hence the serial bandwidth per optical channel is increased. The invention further relates to light emitting devices that exhibit uniform radiation emission characteristics.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 24, 2003
    Inventors: Paul Heremans, Maarten Kuijk, Reiner Windisch, Gustaaf Borghs
  • Publication number: 20030075724
    Abstract: The bottom metal contacts of a surface mount LED are extended wider than the glue covering the LED. The extensions provide more area for soldering to a motherboard.
    Type: Application
    Filed: October 19, 2001
    Publication date: April 24, 2003
    Inventors: Bily Wang, Bill Chang
  • Publication number: 20030075725
    Abstract: The present invention relates to vertical-cavity surface-emitting lasers (VCSELs), and more particularly to a method and apparatus for controlling and stabilization of polarization in such devices.
    Type: Application
    Filed: September 10, 2002
    Publication date: April 24, 2003
    Inventors: Krassimir Panajotov, Hugo Thienpont, Irina Veretennicoff
  • Publication number: 20030075726
    Abstract: A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.
    Type: Application
    Filed: November 28, 2002
    Publication date: April 24, 2003
    Inventors: Ming-Dou Ker , Tung-Yang Chen , Tien-Hao Tang
  • Publication number: 20030075727
    Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.
    Type: Application
    Filed: November 21, 2002
    Publication date: April 24, 2003
    Inventor: Nobusuke Yamamoto
  • Publication number: 20030075728
    Abstract: The present invention has a purpose to provide a Schottky diode allowing obtaining a predetermined reverse-direction breakdown voltage even if a surface state in the vicinity of a Schottky junction interface changes due to the welding of the bonding wire. The semiconductor device having a Schottky junction includes a semiconductor substrate of the first conductivity type. A well region of the second conductivity type is formed in the top surface of the semiconductor substrate. A Schottky electrode is formed on the top surface of the semiconductor substrate and has a Schottky junction with the semiconductor substrate. A connecting conductive member is electrically connected on the Schottky electrode. And, the connecting conductive member is selectively connected with the Schottky electrode above the well region.
    Type: Application
    Filed: April 22, 2002
    Publication date: April 24, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigeo Tooi, Katsumi Satoh
  • Publication number: 20030075729
    Abstract: A semiconductor device is disclosed and includes a drain region of a first conductivity type, having a first major surface. Diffused into the drain region is a body region of a second conductivity type. A source region is diffused in the body region and it has a general polygonal shape when viewed at the first major surface with two notches directed towards the center of the source region from opposite sides. The body region is accessible through the notches. An oxide layer covers the source and body regions except for a contact opening position over the source region between the two notches exposing only that portion of the source region that is between the two notches and at least a portion of the accessible body region in each of the two notches to facilitate a source contact.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 24, 2003
    Inventor: Richard A. Blanchard
  • Publication number: 20030075730
    Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the surface of the trench and on the top surface and the bottom surface of the device region. A conductive layer is formed on the gate dielectric layer. The conductive layer is patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventor: Wen-Yueh Jang
  • Publication number: 20030075731
    Abstract: A mouthpad for cleaning teeth and oral transmucosal drug delivery has a U-shaped plate sized to cover substantially only the biting surfaces of upper and lower teeth of a human jaw. The plate is positioned between the upper teeth and lower teeth such that when the teeth are rinsed with a liquid, the liquid flows primarily through the crevices between individual teeth and physically detaches the adhering residue within. Alternatively, using fluids containing drugs for rinsing while biting on the plate can deliver drugs through the oral mucosa. A method of cleaning teeth and delivering drugs through oral mucosa using a plate positioned between the upper and lower teeth is also disclosed.
    Type: Application
    Filed: August 27, 2002
    Publication date: April 24, 2003
    Inventors: Lingjun Chen, Shuqi Chen
  • Publication number: 20030075732
    Abstract: The present invention relates to a configuration having a first shunt resistor and at least one second shunt resistor connected in parallel with the first shunt resistor. The load terminals of the shunt resistors are disposed at the front side of the shunt resistors and between a first and a second supply potential. The load terminals each have a large-area rear-side contact connection to which different potentials are applied.
    Type: Application
    Filed: September 9, 2002
    Publication date: April 24, 2003
    Inventors: Torsten Franke, Roman Tschirbs
  • Publication number: 20030075733
    Abstract: Semiconductor layers for serving as active layers of a plurality of thin film transistors in a pixel are arranged in the same direction and irradiated with laser light with the scanning direction matched to the channel length direction of the semiconductor layers. It is possible to coincide the crystal growth direction with the carrier moving direction, and high field effect mobility can be obtained. Also, semiconductor layers for serving as active layers of a plurality of thin film transistors in a driving circuit and in a CPU are arranged in the same direction, and are irradiated with laser light with the scanning direction matched to the channel length direction of the semiconductor layers.
    Type: Application
    Filed: September 10, 2002
    Publication date: April 24, 2003
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara
  • Publication number: 20030075734
    Abstract: According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 24, 2003
    Inventors: Yoon-Soo Chun, Dong-Won Shin, Ki-Nam Kim
  • Publication number: 20030075735
    Abstract: A semiconductor circuit having a power supply voltage detection circuit to detect a potential level of an external power supply voltage and to output a detection signal depending on a comparison result with the potential level. A system control circuit detects the detection signal, outputs a status signal and an interrupt signal, and outputs a clock selection signal in response to an operation control signal. A CPU outputs the operation control signal to the system control circuit in response to the status signal and the interrupt signal. A clock generation circuit generates a plurality of clock signals and a clock selection circuit selects one clock signal among the plurality of clock signals in response to the clock selection signal. The clock selection circuit then outputs the one clock signal as a system clock signal.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 24, 2003
    Inventor: Hiroo Nakano
  • Publication number: 20030075736
    Abstract: A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a differential amplifier. Thus, interconnections within a circuit block and a ground wiring can be made with a single metal layer, since an area where the interconnections cross with each other is eliminated. Herewith cross talk due to the intersection of the interconnections can be resolved. Also, the interconnections between the differential amplifier and the emitter follower circuits can be made equal in length. It is possible to assign a second metal layer to interconnections between circuit blocks and a third metal layer to a power supply so that characteristics of the semiconductor integrated circuit are improved.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 24, 2003
    Inventor: Masahiro Shiina
  • Publication number: 20030075737
    Abstract: This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer These layers are sequentially grown on the buffer layer. Since a pre-processing of forming two depressions in the sub-collector layer before growing the collector layer, the top surface of the emitter layer becomes planar surface. This results on the reduction of pits induced in the etching of the emitter contact layer, thus enhances the reliability and the high frequency performance of the HBT.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 24, 2003
    Inventors: Takeshi Kawasaki, Kenji Kotani, Masaki Yanagisawa, Seiji Yaegashi, Hiroshi Yano
  • Publication number: 20030075738
    Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
    Type: Application
    Filed: May 21, 2002
    Publication date: April 24, 2003
    Inventor: Kent Kuohua Chang
  • Publication number: 20030075739
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Application
    Filed: September 20, 2002
    Publication date: April 24, 2003
    Applicant: STMICROELECTRONICS S.r.I.
    Inventors: Antonino Schillaci, Paola Maria Ponzio
  • Publication number: 20030075740
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.
    Type: Application
    Filed: November 25, 2002
    Publication date: April 24, 2003
    Inventors: Gang Bai, David B. Fraser, Brian S. Doyle, Peng Cheng, Chunlin Liang
  • Publication number: 20030075741
    Abstract: The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode.
    Type: Application
    Filed: September 24, 2002
    Publication date: April 24, 2003
    Inventors: Anton Petrus Maria Van Arendonk, Edwin Roks, Adrianus Johannes Mierop
  • Publication number: 20030075742
    Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.
    Type: Application
    Filed: November 29, 2002
    Publication date: April 24, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventor: Mahito Shinohara
  • Publication number: 20030075743
    Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 24, 2003
    Inventors: Jules D. Levine, Ross A. La Rue, Daniel Curcio, Timothy Boles, Joel Goodrich, David Hoag, Noyan Kinayman
  • Publication number: 20030075744
    Abstract: Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16) function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
    Type: Application
    Filed: April 5, 2000
    Publication date: April 24, 2003
    Inventors: Katsuyuki Horita, Takashi Kuroi, Yasuyoshi Itoh, Katsuomi Shiozawa
  • Publication number: 20030075745
    Abstract: As a first semiconductor element and a second semiconductor element, provided are two p-type MOS transistors (11a, 11b) for forming an element pair (11). These MOS transistors (11a, 11b) are compared with each other in electronic characteristic and a result of which is utilized for determining binary logic for the element pair (11). These MOS transistors (11a, 11b) are integrated and hence, they are equally subjected to ambient temperature. As a result, the result of comparison therebetween in electronic characteristic is unlikely to be subjected to ambient temperature.
    Type: Application
    Filed: May 6, 2002
    Publication date: April 24, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigenobu Maeda, Koichiro Mashiko
  • Publication number: 20030075746
    Abstract: As a first semiconductor element and a second semiconductor element, provided are two p-type MOS transistors for forming an element pair. These MOS transistors are compared with each other in electronic characteristic and a result of which is utilized for determining binary logic for the element pair. These MOS transistors are integrated and hence, they are equally subjected to ambient temperature. As a result, the result of comparison therebetween in electronic characteristic is unlikely to be subjected to ambient temperature.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 24, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigenobu Maeda, Koichiro Mashiko
  • Publication number: 20030075747
    Abstract: The present invention relates to a semiconductor device and a method of fabricating the same for simplifying a fabrication process of the semiconductor device and enhancing the performance and yield of the device. A first metal wiring on a semiconductor substrate serves as a first electrode of a metal-insulator-metal (MIM) capacitor. A dielectric film pattern is formed on the first metal wiring. A first via-contact plug on the dielectric film pattern contacts a side of the first metal wiring. An interlayer insulation film is formed having second via-contact plugs in a parallel array structure. The second via-contact plugs contact the dielectric film pattern and serve as a second electrode of the MIM capacitor. A second metal wiring is formed on the interlayer insulation film to contact the first via-contact plug and the second via-contact plugs.
    Type: Application
    Filed: August 22, 2002
    Publication date: April 24, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kil Ho Kim
  • Publication number: 20030075748
    Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.
    Type: Application
    Filed: April 17, 2002
    Publication date: April 24, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiyuki Furuie, Nobuhisa Honda
  • Publication number: 20030075749
    Abstract: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6 inch, 8 inch and 12 inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 24, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Pierre C. Fazan
  • Publication number: 20030075750
    Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 24, 2003
    Applicant: NEC Corporation
    Inventor: Kiyokazu Ishige
  • Publication number: 20030075751
    Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.
    Type: Application
    Filed: November 1, 2002
    Publication date: April 24, 2003
    Inventors: David Y. Kao, James Beacher
  • Publication number: 20030075752
    Abstract: A semiconductor device comprises a first Cu interconnect layer, an interlayer insulation film formed thereon, a via hole formed in the interlayer insulation film to expose a part of the first Cu interconnect layer and a Cu via 124 formed within the via hole and connected to the first Cu interconnect layer. A TaN barrier film and a Ta barrier film are laminated on the side surface of the Cu via, and only the Ta barrier film is formed under the bottom surface thereof. The adherence between the TaN barrier film and the interlayer insulation film is strong, and the adherence between the Ta barrier film and copper is strong. Both the barrier films prevent Cu contamination due to diffusion of Cu and at the same time, enhance adherence between Cu and the interlayer insulation film at the side surface of the Cu via to prevent removal of the Cu via.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 24, 2003
    Applicant: NEC CORPORATION
    Inventor: Koichi Motoyama
  • Publication number: 20030075753
    Abstract: A stacked capacitor on a contact plug of a semiconductor substrate and the method for fabricating the same. A cylindrical conductive layer is formed upon a contact plug of a semiconductor substrate as a lower electrode of a stacked capacitor and there is an opening in the cylindrical conductive layer. A barrier layer is deposited inside the opening of the cylindrical conductive layer and fills a portion of the opening. A capacitor dielectric layer is deposited on the cylindrical conductive layer and on the barrier layer and an upper electrode layer is formed on the capacitor dielectric layer to complete the stacked capacitor.
    Type: Application
    Filed: September 13, 2002
    Publication date: April 24, 2003
    Inventors: Chung-Ming Chu, Masuhiro Kiyotoshi, Masatoshi Fukuda, Tosiya Suzuki, Min-Chieh Yang
  • Publication number: 20030075754
    Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.
    Type: Application
    Filed: November 21, 2002
    Publication date: April 24, 2003
    Inventors: Shenlin Chen, Er-Xuan Ping
  • Publication number: 20030075755
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Application
    Filed: November 16, 1998
    Publication date: April 24, 2003
    Inventor: SHUNPEI YAMAZAKI
  • Publication number: 20030075756
    Abstract: In a non-volatile semiconductor memory device, the device is miniaturized by increasing the coupling ratio between a floating gate and a control gate electrode and reducing the write voltage. In a non-volatile memory device (a so-called floating gate type flash memory 300)) having a floating gate electrode FG in an insulation film (a tunnel oxide film (4), an ONO film structure (9)) between a semiconductor layer (a Si substrate (1)) and a control gate electrode CG, wherein charge is accumulated in the floating gate electrode FG, thereby causing a change in the threshold voltage of a transistor, and thus storing data, the floating gate electrode FG faces substantially the entire surfaces of a bottom surface and a side of the control gate electrode CG via the insulation film (the ONO film structure (9)).
    Type: Application
    Filed: September 13, 2002
    Publication date: April 24, 2003
    Inventor: Toshiharu Suzuki
  • Publication number: 20030075757
    Abstract: A semiconductor memory capable of increasing the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate thereby easily performing high-speed writing with a low diffusion layer voltage is provided. This semiconductor memory comprises the floating gate, a first diffusion layer capacitively coupled with the floating gate for controlling the potential of the floating gate and the control gate arranged oppositely to the floating gate. In an erase operation, the control gate feeds a tunnel current to the floating gate in a direction substantially parallel to the main surface of a semiconductor substrate. Thus, the tunnel current can be fed by extracting carriers from the floating gate also when the control gate has no region overlapping with the upper portion of the floating gate.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 24, 2003
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Hideaki Fujiwara