Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer, to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.

Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.

Abstract: Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.

Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.

Abstract: Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Abstract: Hybrid diodes with excellent ESD protection capacity. Each hybrid diode has two diodes: one is a poly-bounded diode formed as a junction between a substrate and a diffusion region thereon, the other is a poly diode formed as a poly gate having two regions with different conductivity. The poly-bounded diode and the poly diode are connected in series or in parallel to form a hybrid diode. The parallel hybrid diode has smaller operation resistance and as a result better ESD robustness. The series hybrid diode has lower capacitance load and is especially suitable for the ESD protection in high-speed or radio frequency integrated circuit input/output design. The hybrid diode can also be applied in the ESD protection circuit in an input/output port, a power-rail ESD clamp circuit, and a whole-chip ESD protection system. The hybrid diodes can be also implemented in the silicon-on-insulator (SOI) CMOS process.

Abstract: Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods are described. In one embodiment, a monolithic inductance-enhancing integrated circuit comprises a transistor supported by a bulk monocrystalline silicon substrate. An inductor assembly is supported by the substrate and operably connected with the transistor in an inductance-enhancing circuit configuration having a quality factor (Q) greater than 10. In another embodiment, a complementary metal oxide semiconductor (CMOS), inductance-enhancing integrated circuit includes a field effect transistor supported over a silicon-containing substrate and having a gate, a source, and a drain. A first inductor is received within an insulative material layer over the substrate, and is connected to the gate. A second inductor is received within the insulative material layer and is connected to the source.

Abstract: A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity to said first region and having a lower dopant concentration than said first region, a second MOS transistor formed on a main surface of said second region and configuring a radio frequency switch circuit switching on/off an input and output of a radio frequency signal, and a first MOS transistor formed on a main surface of said first region and configuring a radio frequency circuit other than said radio frequency switch circuit. There can be provided a high performance, highly reliable semiconductor integrated circuit with an RF switch circuit provided on a silicon substrate by SOPing.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: The present invention provides for an improved polarized-light detector device. The device comprises a photodiode having a first contact disposed on the backside of a light-sensing medium and a second contact disposed on the frontside of the light-sensing medium. A spin filter medium is disposed between the backside of the light-sensing medium and the first contact. The application of a magnetic field aligns the magnetic moments in the spin-filter medium to cause the device to discriminate between different polarizations of an optical signal. The polarization discrimination is affected by introducing a net magnetization into the spin filter medium, thereby allowing selected spin-polarized electrons to either be transmitted through the spin filter medium to the point of detection or deflected from further transmission. Additionally, the invention is embodied in a polarization-selective-light detector array and methods for discriminating a polarized optical signal and selective optical wavelength detection.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: A galvanometer unit comprises a limited-rotation motor with a load element such as a mirror attached to a shaft extending from the motor. In a servo loop that controls the angular position of the mirror, a position-sensor attached to the shaft provides position feedback information. The sensor includes a rotor which is positioned at the null point of the fundamental torsional resonance mode of the rotating system, thereby essentially eliminating feedback components resulting from the resonance.

Abstract: An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.

Abstract: This invention prevents a cross talk caused by intersection of interconnections, and offers a semiconductor integrated circuit with improved circuit characteristics. By disposing a pair of emitter follower circuits symmetrically with respect to a center line of a differential amplifier, an area where the interconnections cross with each other is eliminated and interconnections within a circuit block and a ground wiring can be made with a single metal layer. Herewith cross talk due to the intersection of the interconnections can be resolved.

Abstract: This invention pertains to a device and a method for injecting spin polarized monochromatic electrons with a particular magnetic moment at room temperature and in absence of an external magnetic field into a nonmagnetic electrode. The device comprises a ferromagnetic electrode, a nonmagnetic electrode spaced from the ferromagnetic electrode, a nanocrystal doped with a single active paramagnetic ion disposed in the space between the electrodes, and an electrical connection between the electrodes for applying voltage to move the electrons from the ferromagnetic electrode, through the doped nanocrstal and into the nonmagnetic electrode.

Abstract: A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction in the substrate. Each trench is filled with an isolation material and has an adjacent trench separated therefrom by a strip region. The device also includes multiple gate structures, for storing charge in a nonvolatile manner, arranged above the surface of the substrate and electrically isolated therefrom. The gate structures are arranged in parallel strips extending in a second direction that cross the strip regions. The device further includes multiple word lines, each of which is arranged on a corresponding gate structure from the multiple gate structures. The device also includes multiple active regions of a second conductivity type, each of which is arranged at one end of a corresponding strip region and each of which is electrically connectable to the gate structures of the corresponding strip region.

Abstract: Disclosed is a bipolar transistor capable of reducing an emitter area at a given operating frequency and output power, as well as satisfying a demand for a device having a higher output power and operating frequency. The bipolar transistor includes a bar-type trunk having a polygonal cross-section, and a plurality of polygonal branches having a polygonal cross-section connected to the trunk, in which a current operating performance of the emitter is improved by increasing a value of a planar structure of the emitter.

Abstract: The present invention discloses a circuit having a make-link type fuse. The circuit comprising a first make-link type fuse connected between a gate of a transistor and a first supply voltage.

Abstract: A semiconductor substrate made of P− type or P−− type silicon having a thickness of approximately 700 &mgr;m and a resistivity of 10 &OHgr;·cm to 1000 &OHgr;·cm is provided, a BOX layer with a thickness of 0.2 &mgr;m to 10 &mgr;m is provided on the semiconductor substrate and a p− type SOI layer is provided on this BOX layer. A first insulating film, which makes contact with the BOX layer, is locally buried in this p− type SOI layer and a CMOS is formed in a region of the p− type SOI layer wherein the above-described first insulating film is not provided. A second insulating film is provided above the first insulating film and over the CMOS, so as to cover the CMOS, and an inductor is provided on the region of this second insulating film corresponding to the first insulating film.

Abstract: Film capacitors have a thin carrier film (1) as dielectric. The surfaces of the carrier films are provided with conductor layers (2)—serving as electrodes—made of metal or made of a nonmetallic conductor. If the capacitor is charged during operation, electric fields with large field strengths can arise at the edges of the conductor layers (2), which can lead to breakdowns. The invention is essentially distinguished by the fact that an edge zone coating (3) is present at the edges of the electrode-forming conductor layer (2), which edge zone coating is only partly charged in the time periods—for example of the alternating-current period—which are critical for changes in the applied voltage. To that end, the edge zone coating of the film must have a surface conductivity which is less than the surface conductivity of the conductor layer.

Abstract: A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of the memory material. The region of conductive material is preferably a sidewall layer of conductive material.

Abstract: A semiconductor device in which a transistor having a first conduction type collector layer, a second conduction type base layer and a first conduction type emitter layer is formed on a semiconductor substrate. The device includes an insulating layer formed on the semiconductor substrate and having a contact hole for connecting an electrode to the base layer, a diffusion source layer formed in the contact hole and containing an impurity for controllably imparting the second conduction type, and a high concentration region formed in the vicinity of a boundary surface between the base layer and the diffusion source layer in the base layer, the high concentration region being formed smaller in thickness than the base layer, containing the same kind of impurity as the impurity contained in the diffusion source layer, and having an impurity concentration higher than the average impurity concentration of the base layer.

Abstract: A semiconductor device is provided that simplifies wiring pattern and is capable of being etched through an etching hole as a concavity is produced over a short time period. According to the semiconductor device of the present invention, a dielectric film 12 is formed so as to shield the concavity formed upon the upper surface of a silicon substrate 10. A circuit pattern that has a thermoelectric conversion element 18 is formed upon the dielectric film. The upper surface of the silicon wafer becomes a (100) surface, and a first etching hole 16 extending in the <110> direction of the silicon substrate and a second etching hole 17 extending in the <−110> direction are formed. These holes intersect in a cross shape. Shapes of the first and second etching holes become parallelograms which have oblique sides tilted with respect to <110> and <−110>. Imaginary rectangles passing though the vertices of the first and second etching holes are continuous.

Abstract: A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Abstract: A multilayer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: Each lead frame for a power chip has one side main surface on which a power chip is mounted and a suspension lead part provided projectingly from a region reserved for forming mold resin in addition to a lead terminal. Thus, the lead frame can be supported by the plurality of suspension lead parts in a molding step. A metal block is provided on the other main surface of the lead frame to face the power chip. Consequently, a semiconductor device with good heat radiation properties and good insulation breakdown voltages can be obtained.

Abstract: A semiconductor element, and a pair of insulation substrates sandwiching the semiconductor element therebetween forms a substrate unit. The substrate unit is press-fitted in a recess provided between first radiation block and cooling block. The press-fitting of the substrate unit is performed by a second radiation block which is screwed to push the first radiation block toward the cooling block. A high thermal-conductive radiation material is disposed at the interfaces between each of the insulation substrates and each of the blocks to keep adhesiveness therebetween.

Abstract: The invention provides a method and apparatus for electrically connecting the die of a high power semiconductor device to a substrate with a conductive strap such that the connection is resistant to the shear stresses resulting with changes in temperature. In one embodiment, the method includes providing a substrate having first and second portions that are electrically isolated from each other. A semiconductor die having top and bottom surfaces and one or more active electronic devices formed therein is also provided. The device has a first terminal connected to a first conductive layer on the bottom surface of the die, and a second terminal connected to a second conductive layer on the top surface of the die. The first conductive layer is electrically coupled to a top surface of the first portion of the substrate. The second conductive layer is electrically coupled to the second portion of the substrate with a metal strap.

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

Abstract: The present invention relates to a stacked semiconductor package and a fabricating method thereof, wherein patterned conductor portions having a wiring function for changing the wiring of leads for controlling operations of stacked semiconductor chips are printed on surfaces of the semiconductor chips. According to the present invention, when the semiconductor chips are stacked one above another, the fabrication processes are simplified by eliminating use of a printed circuit board (PCB) with wiring formed therein for connecting the leads of the semiconductor chips to each other. Further, the connection between the leads can be made in various manners by using an electrically conductive ink or adhesive, so that the stacked semiconductor package can be easily fabricated.

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

Abstract: An optical connector system is disclosed which utilizes a pair of substrates having optical elements associated therewith. Fiducial features in conjunction with alignment members are further utilized to provide for a greater alignment of the optical elements. Methods for forming the optical connector system are also provided.

Abstract: This is a COC type semiconductor device in which a second bump of a second semiconductor chip is bonded on a first bump provided on a first semiconductor chip. The bumps of the first and second semiconductor chips are made of a first metal having relatively high melting point such as Au, and the junction portion of the bump is bonded through a second metal layer having lower melting point than that of the first metal. A step lower than the central part is formed at least in a part of the outer periphery at the top surface of the first bump. In this structure, in the semiconductor device of COC type, even if a protective film of polyimide or other resin is formed on the chip surface, a semiconductor device capable of maintaining a high bond strength in the junction portion of the bump is obtained.

Abstract: Electronic devices with a semiconductor chip and leadframes with device positions and methods for producing the same are encompassed by the invention. The electronic devices include a semiconductor chip disposed with its rear side on a chip island. The chip island has a coplanar pattern of electrically conductive contact layer regions alternating with insulating adhesion layer regions, which is covered by the semiconductor chip.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: A MEMS capping method and apparatus uses a cap structure on which is formed a MEMS cavity, a cut capture cavity, and a cap wall. The cap wall is essentially the outer wall of the MEMS cavity and the inner wall of the cut capture cavity. The cap structure is bonded onto a MEMS structure such that the MEMS cavity covers protected MEMS components. The cap structure is trimmed by cutting through to the cut capture cavity from the top of the cap structure without cutting all the way through to the MEMS structure.

Abstract: A method of manufacturing a tape carrier comprises: a step of providing a tape carrier having bonding portions formed in rows in the width direction, repeating in the longitudinal direction, and having identification marks delimiting regularly repeating matrices formed of pluralities of rows and columns of the bonding portions; a step of examining the tape carrier; a step of removing a defective location of the tape carrier detected in the examination step, and joining together the separated tape carrier to preserve the regular repetition of the matrix; and a step of forming a join mark for delimiting a matrix in which the join formed in the joining step is positioned.

Abstract: A chip including a power MOS circuit in the high level side and a chip including a power MOS circuit in the low level side are accommodated within one sealing body. In this structure, the leads connecting the drain electrodes of the power MOS circuits in the high level and low level sides are set wide and are projected asymmetrically from both longer sides surfaces of the sealing body. Accordingly, the semiconductor device including a composite power MOSFET can be mounted easily.

Abstract: The present invention provides a small-sized and inexpensive semiconductor device wherein a synchronous dynamic random access memory and a flash memory are built in a single encapsulater. A flash memory chip and a synchronous dynamic random access memory chip (SDRAM chip) are fixed to a main surface of a wiring board in a parallel state, and another SDRAM chip is fixed onto the flash memory chip. Electrodes for the respective semiconductor chips are respectively exposed and these electrodes are connected to their corresponding electrodes of the wiring board. An encapsulater formed of an insulating resin is formed on the main surface side of the wiring board so as to cover wires. Since the encapsulater is formed by cutting a block encapsulater formed by block molding by dicing, the side faces of the encapsulater result in cut surfaces. Bump electrodes are provided on the back surface of the wiring board in an array fashion.

Abstract: A wiring pattern formation method for forming a wiring pattern on a wafer by using a transcribing operation includes a transcribing step of thermally pressing and adhering a transcribing original substrate 19 that contains a metallic wiring layer 15 to be transcribed and has a linear expansion coefficient in which a dimensional error from a wafer 10 is within a predetermined range in a heated condition, on the wafer 10, and then adhering and transcribing the metallic wiring layer 15.

Abstract: A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive structure. A third insulative material is deposited over the conductive structure and the sidewall etch stop. The third insulative material is different in composition from the second insulative material. A contact opening is etched through the third insulative material to the conductive structure using an etch chemistry which is substantially selective to the second insulative material of the sidewall etch stop. Integrated circuitry independent of the method of fabrication is disclosed.

Abstract: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Abstract: A first insulating film is formed on a semiconductor substrate. A first pattern group having a plurality of first conductors respectively having a first width and separated from each other by a first interval is formed on the first insulting film. A second conductor having a second width larger than the first width is formed separately from a first conductor of the plurality of first conductors at an end of the first pattern group by a first distance in parallel with the plurality of first conductors. A third conductor having a width equal to the second width is formed on the same side as the second conductor with respect to the first pattern group and separated from the first conductor by the first distance. A fourth conductor having a width equal to the second width is formed between the second and third conductors and separated from the first conductor by the first distance.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Abstract: A corrosion resistant electrode structure for interconnecting a decoupling capacitor to a substrate is disclosed. In an exemplary embodiment of the invention, the electrode structure includes a first chromium layer formed upon the capacitor and a first nickel layer formed upon the first chromium layer. A noble metal conductive layer is then formed upon the first nickel layer and a second nickel layer is formed upon said noble metal conductive layer. The second nickel layer has a thickness which is greater than a thickness of the first nickel layer. A second chromium layer is then formed upon the nickel layer.

Abstract: A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.

Abstract: An interconnect structure comprises a first level metal wiring line patterned on a semiconductor substrate, an inter-metal dielectric (IMD) layer formed on the metal wiring line, a contact plug passing through the IMD layer and electrically connected to the top of the first level metal wiring line, and a second level metal wiring line patterned on the IMD layer and electrically connected to the top of the contact plug. A cap layer is sandwiched between the top of the IMD layer and the bottom of the second level metal wiring line.