Abstract: A high-vacuum packaged microgyroscope for detecting the inertial angular velocity of an object and a method for manufacturing the same. In the high-vacuum packaged microgyroscope, a substrate with an ASIC circuit for signal processing is mounted onto another substrate including a suspension structure of a microgyroscope in the form of a flip chip. Also, the electrodes of the suspension structure and the ASIC circuit can be exposed to the outside through polysilicon interconnection interposed between double passivation layers. The short interconnection between the suspension structure and the ASIC circuit can reduce the device in size and prevents generation of noise, thereby increasing signal detection sensitivity. In addition, by sealing the two substrates at low temperatures, for example, at 363 to 400° C. using co-melting reaction between metal, for example, Au, and Si in a vacuum, the degree of vacuum in the device increases.

Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.

Abstract: An optoelectronic component has a lens that is formed in the surface of an encapsulant surrounding a semiconductor diode element. With respect to emitters, the lens reduces internal reflection and reduces dispersion to increase overall efficiency. With respect to detectors, the lens focuses photons on the active area of the detector, increasing detector sensitivity, which allows a detector having a reduced size and reduced cost for a given application. The lens portion of the encapsulant is generally nonprotruding from the surrounding portions of the encapsulant reducing contact surface pressure caused by the optoelectronic component. This non-protruding lens is particularly useful in pulse oximetry sensor applications. The lens is advantageously formed with a contoured-tip ejector pin incorporated into the encapsulant transfer mold, and the lens shape facilitates mold release.

Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.

Abstract: Within a method for fabricating a microelectronic, and a microelectronic fabrication fabricated in accord with the method, there is formed upon a bond pad formed over a substrate a conductor passivation layer. Within the method and the microelectronic fabrication, the bond pad is formed from a conductor material selected from the group consisting of aluminum and aluminum alloy conductor materials, and the conductor passivation layer is formed from a noble metal conductor material. The invention provides particular value for fabricating color filter sensor image array optoelectronic microelectronic fabrications with attenuated bond pad corrosion.

Abstract: The prevention of the deterioration of the minority carrier lifetime of a semiconductor substrate can be achieved by patterning the material of an impurity diffusion protecting layer on the surface of a semiconductor substrate by a making except a thermal oxidation process of the semiconductor substrate, for example by printing and firing paste material or by depositing paste material using a mask by CVD and forming a diffusion layer in the shape of an inverted pattern of the impurity diffusion protecting layer. Also, a low-priced photovoltaic device the photo-electric conversion efficiency of which is high can be manufactured by patterning and forming them.

Abstract: The present invention relates to a semiconductor device and has an object to enhance a di/dt tolerance and a dV/dt tolerance without increasing an ON resistance.

Abstract: Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

Abstract: The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: A novel fuse structure. An optimal position of laser spot is defined above a substrate. A first conductive layer is formed on part of the substrate. A first dielectric layer is formed on the substrate and the first conductive layer. A second conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and the second conductive layer. A third conductive layer comprising the position of laser spot is formed on part of the second dielectric layer. A plurality of first conductive plugs penetrate the first dielectric layer, to electrically connect the first conductive layer and the second conductive layer. At least one second conductive plug penetrates the second dielectric layer, to electrically connect the second conductive layer and the third conductive layer. Thus, the third conductive layer serves as a backup conductive layer when the second conductive layer is broken.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are present in the ranges of less than 10° or 58°-62°.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: A film-integrated key top include a resin key top and a resin film which is integrated with the resin key top. The resin film may be three types: (1) a matte film that contains powders fine enough to provide the film with translucency, (2) a laminate film that includes a base film and a resin matte layer which is laminated on at least one side of the base film, wherein the resin matte layer contains powders fine enough to provide the film with translucency, (3) a processed film that includes the base film or the laminate film, wherein at least a surface of the film is processed to have a roughened portion. Thus, a film-integrated key top which shows excellent translucency as well as excellent matte texture is provided.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80% Al2O3.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.

Abstract: In a lead frame which has second tie bars 4a2, 4b2 in the vicinity of plastic packages 15, first notches 1 are formed along first edges of the second tie bars 4a2, 4b2 (in areas defined on both sides of the inner leads 12a, 12b and to come into contact with a punch during the tie bar cutting step). The first notches 1 prevent troubles associated with close arrangement of the second tie bars 4a2, 4b2 and the plastic packages 15. In addition, second notches 2 are provided along second edges of the second tie bars 4a2, 4b2. These second notches 2 are designed to receive the tips of outer leads 13a, 13b which extend from neighboring plastic packages 15 of the lead frames 100a, 100b.

Abstract: An interposer-based semiconductor package (40) having at least one semiconductor die (21) attached to one side thereof also has, prior to placement on a printed wiring board (61), an underfill material (31) disposed at least partially thereon. Depending upon the embodiment, the underfill material (31) may initially cover interface electrodes (12) on the interposer (11). Such material (31) can be selectively removed to partially expose the interface electrodes (12). In other embodiments, apertures (101) can be left in the underfill material (31) during deposition, or formed after the underfill material (31) has been deposited, and the interface electrodes (12) subsequently formed in the apertures (101). Deposition of the underfill material (31) can be done with a single interposer-based package (40) or simultaneously with a plurality of such packages. Once deposited, the underfill material can be processed to render it relatively stable an substantially non-tacky.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: An improved structure of a pin platform of an integrated circuit having a pin platform body including a chip seat and a plurality of leading plates having their end portions being concentrated on the chip seat and the chip seat being connected to the pin platform body via the connection plate, characterized in that the surrounding of the chip seat is provided with a framing side, and the framing side is connected to a connection plate, and the surface of the chip seat is smaller than the connection surface of the IC to be installed, and the size of the framing side is larger than the size of the connection face of the IC. Therefore, a high performance greenery package is obtained and the ground wire of the IC can be soldered to the framing side, which provides a smooth connection and a communication.

Abstract: In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.

Abstract: A surface acoustic wave (SAW) filter includes a SAW chip mounted in a recession of a multi-layer substrate, a sealing plate covering the recession, an end surface electrode that is provided on the outer surface of the substrate and is in conduction with the SAW chip, a metal conductor for radiating heat that is provided on the surface at the opposite side from the sealing plate of the multi-layer substrate, and a through hole provided in the substrate, one end thereof being connected to the metal conductor. The other end of the through hole is connected with the SAW chip through the intermediary of a metal constituent, such as an electrically conductive adhesive layer.

Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.

Abstract: A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array.

Abstract: A semiconductor device (100) has a semiconductor chip (102) mounted on a tape carrier (104). Tape carrier (104) of thickness t has a plurality of via holes (118) of inner diameter Dv penetrating the tape carrier (104). Solder balls (114) having outer diameter Db are attached through the via holes (118) to serve as external connection terminals for the semiconductor chip (102). Specific dimensional relationships are established among thickness t of tape carrier (104), inner diameter Dv of via holes (118) and outer diameter Db of solder balls (114) in order to improve connection reliability by reducing poor connections of solder balls (114).

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack comprises a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etching the platinum in argon, followed by a wet etch in aqua regia using an oxide hardmask. Alternatively, the titanium-tungsten and platinum layers are deposited sequentially and patterned by a single plasma etch process with a photoresist mask.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A plurality of successive layers are firmly adhered to one another and to a wafer surface and an electrical component or sub-assembly even when the wafer surface is not even and the layers are bent. The wafer surface is initially cleaned by an ion bombardment of an inert gas (e.g. argon) on the wafer surface in an RF discharge at a relatively high gas pressure. The wafer surface is then provided with a microscopic roughness by applying a low power so that the inert gas (e.g. argon) ions do not have sufficient energy to etch the surface. A layer of chromium is then sputter deposited on the wafer surface as by a DC magnetron with an intrinsic tensile stress and low gas entrapment by passing a minimal amount of the inert gas through the magnetron and by applying no RF bias to the wafer. The chromium layer is atomically bonded to the microscopically rough wafer surface.

Abstract: In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: A method and system for electrically interconnecting a semiconductor device and a component is presented. The semiconductor device includes a dielectric portion on at least one face thereof. Similarly, the component includes a dielectric portion on at least one face thereof. The device and component are constructed and arranged to be stacked and bonded together. A first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component. A second laser deposits a conductor along a path between the starting pad and destination pad. As such, smaller, more condensed electronic packages may be fabricated.

Abstract: A flip chip semiconductor device having non-solder contact terminals is assembled by securing the chip and substrate with a rapidly thermosetting adhesive. The process is amenable to various bump and substrate materials, and has the advantage of simultaneously adhering the components and of providing a void free underfill. The process makes use of absorption of infrared energy by the chip to heat the adhesive and cause it to flow prior to rapidly solidifying from the center outwardly. The rapid assembly, using a simple infrared exposure apparatus is compatible with reel to reel, or other highly automated in-line processes.

Abstract: A chip scale package (CSP) comprises a flip chip and chip carrier with features to enhance its electrical and thermal performance. The flip chip connects to the chip carrier through alternating signal and ground connections. Top layer routing on the chip carrier substantially maintains ground-based guard isolation between neighboring signal lines. The arrangement of inter-layer vias and bottom layer traces also maintains the isolation for flip chip signals routed to the bottom layer of the chip carrier, where they are available for interconnection with a primary circuit board via solder balls or the like. The bottom layer further includes a centralized ground plane. Special thermal vias extend from the top layer into this bottom layer ground plane. Dedicated solder ball connections for the ground plane provide a ground path between the flip chip and the primary circuit with very low electrical and thermal impedances.

Abstract: A semiconductor device includes a first conductive member, a second conductive member, a semiconductor chip, which is located between the conductive members, a bonding member, which is located between the first conductive member and the semiconductor chip, another bonding member, which is located between the second conductive member and the semiconductor chip, a molding resin, which is located between the first and second conductive members to seal the semiconductor chip, and a bonding member anti-sticking means, which is located between the molding resin and a surface of one member selected from the group consisting of the semiconductor chip and the conductive members. The bonding member anti-sticking means prevents the bonding members from sticking to the surface in the manufacturing process. As a result, the otherwise insufficient connection due to the sticking between the molding resin and the surface is improved, and the semiconductor device becomes durable in electric performance.

Abstract: A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.

Abstract: It is intended to lower an increase of an area of an unused area or a wiring area, which is caused due to addition or enhancement of a particular function of a semiconductor device without significantly changing layout of the semiconductor device which has been previously designed. A semiconductor device (100A) has a layout in which a wiring area (102) is surrounded by an extension block (103) as a second semiconductor region and is completely sandwiched between a block (101) and the extension block (103). A plurality of wires (104) are laid across the wiring area (102) only at a single position between two adjacent ones of a plurality of pads (102a) in the wiring area (102), to connect a CPU (201c) in the block (101) and each of a ROM (301), a RAM (302) and an A/D converter (303) in the extension block (103) with each other.

Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.

Abstract: A semiconductor device includes a nitride film between a gate electrode and an ohmic electrode contacting to a diffusion region adjacent to the gate electrode, at least on a side of the gate electrode facing the ohmic electrode.

Abstract: A humidifier (24) for use with a breathable gas supply apparatus (20). The humidifier (24) comprises a hollow body (42, 44) adapted for partial filling with water to a predetermined maximum water level, a gas inlet (48) to the body (42, 44) above the maximum water level and a gas outlet (50) from the body (42, 44) above the maximum water level. The humidifier (24) further comprises a constant temperature heating element (30) for heating the water and/or an adjustable flow divider (62) adapted to divide the interior of the body (42, 44) above the maximum water level into a relatively dry gas region (68) and a relatively wet gas region (70). The position of the divider (62) is variable so as to vary the relative proportion of the gas flowing from the inlet (48) to the outlet (50) that passes through the relatively dry (68) and relatively wet (70) gas regions to thereby vary the amount of humidification thereof.

Abstract: One embodiment of the invention is a multi layer GI POF where each layer comprises essentially one polymer and one or more dopants. Each layer may comprise the same or different polymers although it is preferred that each layer comprise the same homopolymer. Useful dopants include cyclic or acyclic organic compounds of less than about 20 carbons, alkyl metal oxides or rare earth alkyl oxides. Another embodiment of the invention is a method of making the GI POF according to the invention.

Abstract: A method and apparatus for forming a hydrophilic layer on a surface of polymer layer of a reflector economically and safely. The method for manufacturing a reflector includes steps of molding a base body of the reflector; forming reflective layer for reflecting light on a surface of the base body; forming a layer of water-repellent polymer on a surface of the reflective layer; and performing hydrophilic treatment on a surface of the polymer layer using plasma of gaseous argon.

Abstract: The present invention provides novel encapsulation compositions and methods. In particular, the invention relates to fluorescent capsule compositions, which consists of a layer of a polymer shell enclosing one or more fluorescent materials such as fluorescent microspheres and which are capable of emitting at least two distinct fluorescent signals. Also provided are methods for their preparation. The compositions and methods of this invention are useful in a variety of applications, including preparation of multiplexed arrays for industrial, chemical, immunological, and genetic manipulation and analysis especially as related but not limited to flow cytometry.

Abstract: The invention relates to a device for the automated production of dental workpieces. A blank is inserted in a substantially slab-shaped support of the device, said support being dimensioned such that the blank does not extend beyond it in any direction. The blank is linked with corresponding inner walls of a recess provided in the support only on two opposite faces while a gap is left between the other inner walls of the recess and the corresponding faces of the blank. The inventive design allows to avoid tensions and microcracks of the blank material thereby caused. The gaps further make the blank directly accessible for a lateral working by the milling tool.

Abstract: A method is provided for forming items from ecoceramic-based silicon-carbide. A wood preform is machined to a general shape having over- or undersized dimensions. The preform is pyrolyzed to transform the wood of the preform to a porous, carbonaceous material that retains the general shape of the preform. The preform is then machined to final, net-shape dimensions and immersed in liquid silicon or silicon alloy that penetrates and infuses the preform. The infused preform is held at a temperature sufficient to cause the transformation of the material in the preform to silicon carbide, completing formation of the item. Also provided is a method of forming ecoceramic-based tooling and composite components using the tooling.

Abstract: A repair device can repair a puncture in a normally pressurized vehicle tire. The device has a dispenser with dual barrels containing a pair of separate constituents adapted to form a cement that can adhere to the vehicle tire. A static mixer can be mounted on the dispenser for receiving and mixing the pair of constituents to form the cement. An injection tube mounted on the static mixer is sized to fit into the puncture. A pair of piston heads slidably fitted in the dual barrels can push the pair of constituents through the static mixer to form the cement for injection from outside the tire, through the injection tube, and into the puncture to reach inside the tire. After removing the injection tube, the cement that was injected is allowed to set at least partially before using the tire.

Abstract: A combination fastener and foam sheet having enhanced fastener retention and methods of forming a foam sheet are provided so that the fastener is not easily removed from the foam sheet when an outward force is applied thereto. The combination preferably includes a foam sheet including a fibrous material and urethane foam material abuttingly contacting and substantially surrounding the fibrous material so that the fibrous material is substantially contained within and retained by the urethane foam material. The combination also, preferably includes a fastener having threaded portions positioned within the foam sheet so that the threaded portions are retained in the foam sheet and are not easily removed when an outward force is applied thereto. The foam sheet preferably also has a strengthening material such as glass also substantially surrounded by the urethane foam.