Abstract: The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side region and the second-side region and is defined by a masking photoresist step and is scalable. The gate region comprises two stack-gate transistors formed in the side portions of the gate region with a select-gate transistor being formed therebetween for the first embodiment of the present invention and with a bit-line conductive island formed over a common-drain diffusion region for the second embodiment of the present invention. The first-side/second-side region comprises a common-source conductive bus line being integrated with a conductive erasing anode for high-speed erasing. The cell size of each bit is smaller than 4F2.

Abstract: In an insulated gate semiconductor device having first, second and third gate electrodes (10) which are buried in first, second, and third trenches (7), an emitter electrode (11) is commonly connected to a base region (4), an emitter region (5) and the second gate electrode (10b), and the third gate electrode (10c) is connected to only the first gate electrode (10a). An insulating interlayer (9) interposed between the emitter electrode (11) and the gate electrodes (10) has a pattern configuration such that the second gate electrode is partially connected to the emitter electrode, to thereby control a gate capacity and suppress a short-circuit current caused by a crack.

Abstract: A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.

Abstract: According to one embodiment of the present invention, a semiconductor structure includes an SOI memory cell having a pass transistor having a body and a driver transistor having a body. The SOI memory cell also includes a source voltage contact coupling the bodies of the pass transistor and the driver transistor and a non-square conductive active region coupled to the source voltage contact. The shortest distance between the body of the pass transistor and the source voltage contact is greater than the shortest distance between the body of the pass transistor and the body of the driver transistor, and the shortest distance between the body of the pass transistor and the non-square conductive active region is less than the shortest distance between the bodies of the pass transistor and the driver transistor.

Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.

Abstract: The object of the present invention is to suppress a short channel effect on a threshold voltage. A channel region 5, a pair of source-drain regions and an isolating film 2 having a trench isolation structure are selectively formed in a main surface of a semiconductor substrate 1. An upper surface of the isolating film 2 recedes to be lower than an upper surface of the channel region 5 in a trench portion adjacent to side surfaces of the channel region 5 and to be almost on a level with the upper surface of the channel region 5 in other regions. Consequently, a part of the side surfaces of the channel region 5 as well as the upper surface thereof are covered by a gate electrode 4 with a gate insulating film 3 interposed therebetween. A channel width W of the channel region 5 is set to have a value which is equal to or smaller than a double of a maximum channel depletion layer width Xdm.

Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

Abstract: The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.

Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.

Abstract: A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: A field effect transistor comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode.

Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.

Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

Abstract: A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nitride on a substrate, and a silicon nitride film is deposited on the titanium oxide film. The silicon nitride film will prevent oxidation of the titanium oxide film when the surface of the substrate is subjected to thermal oxidation in the next process step. Next, the silicon nitride film and the titanium oxide film on the I/O circuit region are removed, while the silicon nitride film and the titanium oxide film on the internal circuit region remain, and the substrate is subjected to thermal oxidation to form a silicon oxide film as a gate insulation film on the surface of the I/O circuit region.

Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract: A method of forming a diffusion barrier layer in a semiconductor device is disclosed. A high-k gate dielectric layer is formed over a substrate. A silicon nitride barrier layer is subsequently formed over the high-k gate dielectric layer by reacting tetrachlorosilane with ammonia through a chemical vapor deposition process. The silicon nitride barrier layer substantially blocks diffusion of impurities from an ensuing overlying gate layer. A semiconductor device comprising the silicon nitride barrier layer, and a method of fabricating such a semiconductor device are also disclosed.

Abstract: The present invention relates to a method for manufacturing a micromechanical component (100), that has at least one hollow space (110) and a functional element (12) that is provided at least partially in the hollow space (110) and/or a functional layer (13a, 13b, 13c) that is provided at least partially therein, and to a micromechanical component (100) that is manufactured in accordance with the method, according to the species of the relevant independent patent claim.

Abstract: A method of making a micro electro-mechanical switch or tunneling sensor. A cantilevered beam structure and a mating structure are defined on an etch stop layer on a first substrate or wafer; and at least one contact structure and a mating structure are defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer. A bonding layer, preferably a eutectic bonding layer, is provided on at least one of the mating structures. The mating structure of the first substrate is moved into a confronting relationship with the mating structure of the second substrate or wafer. Pressure is applied between the two substrates so as to cause a bond to occur between the two mating structures at the bonding or eutectic layer. Then the first substrate or wafer and the etch stop layer are removed to free the cantilevered beam structure for movement relative to the second substrate or wafer.

Abstract: A blue LED or ultra-violet (UV) LED chip is packaged with a cover of fluorescent material. When the LED emits blue or UV light, the light is converted into colorless or white light radiating from the package. The package is furnished with bottom contacts for surface mounting.

Abstract: A solid state image pickup device having: a semiconductor substrate having a light receiving area; a number of pixels formed in the light receiving area of the semiconductor substrate in a matrix shape, each of the pixels having a main photosensitive field having a relatively large area and a subsidiary photosensitive field having a relatively small area; a main color filter array formed above the semiconductor substrate and covering at least the main photosensitive fields in register with the respective pixels; and a micro lens array formed on the color filter array and covering at least the main photosensitive fields in register with the respective pixels, wherein an image signal can be selectively picked up from either one of the main and subsidiary photosensitive fields. A solid state image pickup device having a high resolution can be provided.

Abstract: A diode of the present invention has a Si substrate, a Si film of a first conductivity type laminated on this Si substrate, and a SiGe film of a second conductivity type laminated on this first conductivity type Si film.

Abstract: The present invention provides a method of manufacturing a semiconductor device. The method may include forming first and second adjacent tubs in an epitaxial layer, and simultaneously forming a base region in the first tub and lightly doped drain (LDD) regions in the second tub adjacent a first gate located over the second tub. The method may also include simultaneously forming a base contact region and a source/drain contact region.

Abstract: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.

Abstract: A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.

Abstract: A semiconductor wafer (70) that includes a support body (72), at least one thin die (20, 60), and a plurality of tethers (78, 178). The support body (72) is made of a semiconductor material. The thin die (20, 60) has a circuit (21) formed thereon and has an outer perimeter (74) defined by an open trench (76). The open trench (76) separates the thin die (20, 60) from the support body (72). The tethers (78, 178) extend across the open trench (76) and between the support body (72) and the thin die (20, 60). A method of making a thin die (20, 60) on a wafer (70) where the wafer (70) has a support body (72), a topside (82) and a backside (90). A circuit (21) is formed on the topside (82) of the wafer (70).

Abstract: A recess is formed in a semiconductor substrate and a contact hole is formed in a bottom region of the recess. Circuit elements on a main surface of the semiconductor substrate are connected to conductive elements on an opposite surface of the substrate through the contact hole in the recess.

Abstract: In order to determine the dielectric constant of a layer deposited on a semiconducotr wafer (2), the density of the layer is obtained. To obtain that density, the wafer (2) without the layer is weighed in a weighing chamber (4) in which a weighing pan (7) supports the wafer on a weighing balance. The weight of the wafer is determined taking into account the buoyancy exerted by the air on the wafer (2). Then the layer is deposited on the wafer (2) and the weighing operation repeated. Alternatively a reference wafer may be used. If the material of the layer is known, the weight of the layer can be used to derive its density using a thickness measurement. Alternatively, if the density is known, the thickness can be obtained.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices wherein a patterned layer of a metal, alloy, nitride or silicide is subjected to a low temperature, wide beam electron beam annealing. The process involves depositing a silicide, nitride, metal, or metal alloy layer onto a substrate; and then overall flood exposing said entire layer to electron beam radiation under conditions sufficient to anneal the layer.

Abstract: Wiring lines for use at a high frequency having reduced resistance and/or inductance are disclosed that may be readily manufactured in a semiconductor integrated circuit. Wiring lines can include extension lines (2), connected to both ends of an inductor (1), that may each include divided wiring lines (2a and 2b) that are separated by a slit (3). A length, width and thickness of divided wiring lines (2a and 2b) can be essentially equal, resulting in divided wiring lines (2a and 2b) of essentially equal longitudinal resistance. A width of a slit (3) may preferably be greater than a width of each of divided wiring lines (2a and 2b).

Abstract: A semiconductor package with a die pad having a recessed portion is proposed, wherein a lead frame is used, having a die pad formed with at least a through hole, and a plurality of leads. A chip is mounted on the die pad and covers the through hole, with a bottom surface of the chip being partly exposed out the through hole. The through hole is formed at its peripheral edge with a recessed portion that dents from a top surface of the die pad and is associated with the through hole. During a molding process, the recessed portion is entirely filled with an encapsulating compound used for encapsulating the chip and die pad. This prevents forming of voids between the chip and die pad, and assures packaged products to be free of die crack or popcorn effect, thereby significantly improving yield and reliability of the packaged products.

Abstract: A semiconductor chip mounting substrate having a semiconductor bare chip and a substrate electrically connected to the semiconductor bare chip by wire bonding is provided. Here, a protective film is provided on the surface of the semiconductor bare chip and is disposed so as to expose all or a part of a bonding wire.

Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.

Abstract: A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.

Abstract: A lead frame for a resin-molded semiconductor device is provided with die pads for separately mounting chips of power elements and a control IC thereon; terminal leads arranged in a row at one side and including leads for the die pads, and a main circuit, a control power supply and signal circuit separated from the die pads; and a dam bar connecting the terminal leads. In the main circuit terminals and control power supply terminals, a plurality of leads is formed and drawn in advance. After the lead frame is set in a mold die and is resin-molded, certain leads that are not used as the terminal leads are selected among the plurality of the leads, and the certain leads are cut and removed together with the dam bar.

Abstract: Charge prevention patterns disposed on one surface of a circuit board and electrolytic plating patterns disposed on the other surface of the circuit board are disposed in a zigzag pattern in end surfaces of the substrate. The thickness of a coating layer is smaller than the thickness of a card case.

Abstract: A stack of integrated circuits in thin small outline packages (TSOP's) is constructed with an air space in between adjacent packages. The TSOP's have a plurality of connection terminals extending therefrom. A lead frame is disposed adjacent to the packages, positioned medially of the air space and having a plurality of connection terminals in registration with and in electric contact with the plurality of TSOP connection terminals. The TSOP's have a chip select terminal and several unused terminals. The lead frame has a strain-relieved conductor extending between the chip select terminal on a TSOP higher in the stack to the adjacent TSOP lower in the stack. Moreover, TSOP locating surfaces are included on the lead frame in the finished stack.

Abstract: A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips.

Abstract: A stacked package includes a substrate, a first die, at least one signal transmission plate, at least one second die, a plurality of conductive wires, and a molding compound. The first die is electrically connected with the substrate using flip-chip bonding. The signal transmission plate is provided on the first die and includes an insulating layer, a layout wire layer, and a solder mask layer. The layout wire layer is formed on the insulating layer, and the solder mask layer is formed on the layout wire layer. The solder mask exposes partial area of the layout wire layer at the center and peripheries of the signal transmission plate to form a plurality of die bonding pads and a plurality of wire bonding pads. The second die is electrically connected with the die bonding pads using flip-chip bonding, and the wire bonding pads are electrically connected with the substrate via the conductive wires so that the signals from the second die are transmitted to the substrate.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer.

Abstract: A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: A semiconductor device includes at least three circuit substrates laid one upon another. The device further includes first circuit elements mounted, respectively, on at least two of the three circuit substrates. It also includes a second circuit element mounted on one of the three circuit substrates and configured to change connection between the first circuit elements.

Abstract: An apparatus for processing a high-frequency electrical signal. The apparatus comprises a circuit carrier and an electrical circuit mounted on the circuit carrier. The electrical circuit processes a signal within a predetermined frequency range, the predetermined fundamental frequency range having a low end in the range being about 1 GHz or higher. An encapsulent material encapsulates at least a portion of the electrical circuit. The circuit carrier, electrical circuit, and encapsulent material form a package having resonant frequencies. The resonant frequencies are outside the predetermined frequency range.

Abstract: To increase the reliability of a non-contact IC card for use in such applications as a door key, etc., two separate combinations of an IC chip and an antenna coil coupled to that chip are provided in the card, with each IC chip storing the same information, such as a key code. Since the probability of both of the IC chips being damaged concurrently due to application of external force is very much smaller than the probability of failure of a single IC chip, the objective of enhanced reliability is effectively achieved.