Abstract: A heat-sensitive recording material including a support having succesively disposed thereon a heat-sensitive recording layer, a light transmittance adjusting layer and a protective layer, wherein the light transmittance adjusting layer contains a UV absorbent precursor represented by the general formula (1): 1

Abstract: A pneumatic nail puller tool for use with a standard needle scaler actuator. A needle scaler typically actuates a chipping hammer installed by means of a chuck. The nail puller tool is so sized and configured as to replace the chipping hammer and lock into its chuck. The nail puller, so installed, is useful in quickly removing nails from a work piece, even where a nail head is buried in the work piece. The nail puller includes a central shaft having a shank having flats and a detent seat for locking into the needle scaler chuck at one end and a nail removing claw at the opposing end. The claw is angled relative to the shaft to provide a lever point to assist in extracting the nail. The claw has sharp entrance points for digging into the work piece to grip an embedded nail head.

Abstract: The invention relates to a service stand (1), which is positioned beneath the rear part of a motorcycle and which extends from there to both sides of the motorcycle, the service stand having a lever member (2) for lifting the rear part of the motorcycle so that the rear wheel (3) is lifted off the ground (4), and members for connecting the service stand (1) to the rear part of the motorcycle. According to the invention the service stand (1) placed beneath a motorcycle leaning on its side stand has a connecting member (5), on the opposite side from the side stand, the connecting member being pre-adjustable in the height direction, whereas the height position of the connecting member (6) on the same side as the side stand can be adjusted in the height direction by the lever member (2).

Abstract: An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conductivity layer has an anisotropic sheet resistivity profile and provides for substantially uniform emissions over the emissive surface of the emitter.

Abstract: A field emission display device and a method of fabricating the same are provided. The field emission display device includes a substrate, a transparent cathode layer, an insulation layer, a gate electrode, a resistance layer, and carbon nanotubes. The transparent cathode layer is deposited on the substrate. The insulation layer is formed on the cathode layer and has a well exposing the cathode layer. The gate electrode is formed on the insulation layer and has an opening corresponding to the well. The resistance layer is formed to surround the surface of the gate electrode and the inner walls of the opening and the well so as to block ultraviolet rays. The carbon nanotube field emitting source is positioned on the exposed cathode layer. An alignment error between the gate electrode and the cathode is removed, and carbon nanotube paste is prevented from remaining during development, thereby preventing current leakage and short circuit between the electrodes and diode emission.

Abstract: An optoelectronic semiconductor chip has an active layer containing a photon-emitting zone. The active layer is attached to a carrier member at a bonding side of the active layer. The active layer has at least one recess therein with a cross-sectional area that decreases with increasing depth into said active layer proceeding from said bonding side.

Abstract: An amplification type solid-state image pickup device has a plurality of pixels each of which comprises a photodiode 4, a signal-amplification-use MOS transistor 1 for amplifying signal charges stored in the photodiode 4, a reset-use MOS transistor 2 for resetting signal charges stored in the photodiode 4, and a pixel-selection-use MOS transistor 3 for selecting a signal amplified by the signal-amplification-use MOS transistor 1. During a first period, a reset drain voltage VP(i) is turned and held in a Low state. During second and third periods thereof, the reset drain voltage VP(i) is changed to a High state. A reset gate voltage RS(i) is set to a first voltage (VDD−&Dgr;V) during the first and second periods, and the reset gate voltage RS(i) is set to a second voltage VDD higher than the first voltage by a specified voltage &Dgr;V during the third period.

Abstract: An electronic device includes first and second electrical contacts electrically coupled to a semiconductor polymer film, which includes mono-substituted diphenylhydrazone.

Abstract: The invention relates to a material including carbon, oxygen, silicon and hydrogen and having a dielectric constant of from about 2.1 to about 3.0 where an FTIR scan of the material includes at least two major peaks signifying Si—CH3 bonding. The invention further relates to a material which has a variable dielectric constant through the thickness of the material. Another aspect of the invention is the method of making the material.

Abstract: A transistor having a channel width, W, and a channel length, L, defined by non-rectangular electrodes. The transistor is a thin film field effect transistor having an insulated gate electrode. One of a source and drain electrodes is connected to a display electrode and one is connected to a data line. The source and drain electrodes can be interdigitated to provide a desired W/L ratio. The gate is connected to a select line. An overlap region between a display electrode and a select line for another pixel defines a capacitor. The transistor is fabricated to be situated behind the display electrode so as to maximize an aperture ratio. The design enables the use of conventional printing methods, such as screen printing, ink jet printing, printing through a stencil, flexo-gravure printing and offset printing.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/m2 at room temperature, 900 mJ/m2 at 150° C., and 1800 mJ/m2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.

Abstract: A polycrystalline silicon thin film for a TFT and a display device using the same where the number of crystal grain boundaries exerts a fatal influence on movement of electric charge carrier, providing a distance “S” between active channels of the TFT having dual or multiple channels with a relation S=mGs·sec &thgr;−L, and also providing a display device in which uniformity of TFT characteristics is improved by synchronizing the number of the crystal grain boundaries included in each of the channels of the dual or multiple channels

Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

Abstract: To provide a semiconductor device composed of a semiconductor element or a group of semiconductor elements, in which a crystalline semiconductor film having as few grain boundaries as possible in a channel formation region is formed on an insulating surface, which can operate at high speed, which have high current drive performance, and which are less fluctuated between elements.

Abstract: The present invention provides a high efficient nitride semiconductor element having an opposed terminal structure, whose terminals facing each other, and a method for producing thereof.

Abstract: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.

Abstract: A semiconductor light emitting device is fabricated by forming a mask having an opening on a substrate, forming a crystal layer having a tilt crystal plane tilted from the principal plane of the substrate by selective growth from the opening of the mask, and forming, on the crystal layer, a first conductive type layer, an active layer, and a second conductive type layer, which extend within planes parallel to the tilt crystal plane, and removing the mask. The semiconductor light emitting device can be fabricated without increasing fabrication steps while suppressing threading dislocations extending from the substrate side and keeping a desirable crystallinity. The semiconductor light emitting device is also advantageous in that since deposition of polycrystal on the mask is eliminated, an electrode can be easily formed, and that the device structure can be finely cut into chips.

Abstract: A boron-phosphide-based semiconductor light-emitting device having a semiconductor substrate of a first conduction type having, on its bottom surface, a bottom electrode; a first boron-phosphide-based semiconductor layer of a first conductive type provided on the substrate; a Group III-V compound semiconductor active layer provided on the first boron-phosphide-based semiconductor layer; a second boron-phosphide-based semiconductor layer of second conduction type provided on the active layer; and a top electrode provided on the surface of the second boron-phosphide-based semiconductor layer.

Abstract: The invention describes a radiation-emitting semiconductor component with a luminescent conversion element, at which the semiconductor body is placed in a recess of the base body. A cup-like area is molded inside of the recess around the semiconductor body, which contains the luminescent conversion element and coats the semiconductor body. The cup-like portion is formed as indentation inside of the recess or as annular border on the base of the recess.

Abstract: An improved integrated optical device (5a-5g) is disclosed containing first and second devices (10a-10g; 15a, 15e), optically coupled to each other and formed in first and second different material systems. One of the first or second devices (10a-10g, 15a, 15e) has a Quantum Well Intermixed (QWI) region (20a, 20g) at or adjacent a coupling region between the first and second devices (10a-10g; 15a, 15e). The first material system may be a Ill-V semiconductor based on Gallium Arsenide (GaAs) or Indium Phosphide (InP), while the second material may be Silica (SiO2), Silicon (Si), Lithium Niobate (LiNbO3), a polymer, or glass.

Abstract: A semiconductor component has a substrate and a semiconductor body that contains at least one nitride compound semiconductor and is arranged on a surface of the substrate. An electrically conductive masking layer with a predetermined mask structure is arranged between the substrate and the semiconductor body. The masking layer partly covers the surface of the substrate. Furthermore, the invention describes a method for fabricating such a semiconductor component.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: A high frequency switch, has

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. An annular flange may also be embedded in the plastic molded insulation ring and connected to an annular rib of a pole piece by a circular connector.

Abstract: A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple &dgr;-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple &dgr;-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple &dgr;-doped InAlAs layer (204) as a carrier supplying layer is reduced.

Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.

Abstract: An n-type impurity (ions) is implanted into a cell P-well 104 through contact holes 161 to form n-type diffusion layers 171. At this time, the ranges over which no n-type impurity diffusion zone 171 is to be formed are all covered by a third silicon oxide film 151 and, as a result, no n-type impurity is implanted over these ranges. In addition, since the contact holes 161 are formed between transfer gates 111 through self-alignment, the n-type impurity diffusion zones 171 are formed at specific positions with a high degree of accuracy even in a highly miniaturized DRAM. Furthermore, since the transfer gates 111 are each provided with a side wall 115 constituted of a silicon nitride stopper film 123 and a second silicon oxide film 121, the n-type impurity is not implanted into the transfer gates.

Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Depressions and projections with stripe shape or rectangular shape are formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film along the depressions and projections with stripe shape of the insulating film, or along a longitudinal axis direction or a transverse axis direction of the rectangular shape. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave laser light may also be used.

Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.

Abstract: A semiconductor device comprising a flexible or rigid substrate (11) having a gate electrode (21), a source electrode (61 and 101), and a drain electrode (62 and 102) formed thereon and organic semiconductor material (51, 81, and 91) disposed at least partially thereover. The gate electrode (21) has a thin dielectric layer 41 formed thereabout through oxidation. In many of the embodiments, any of the above elements can be formed through contact or non-contact printing. Sizing of the resultant device can be readily scaled to suit various needs.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: One or more deep-array implants under the photosensitive region of a semiconductor substrate are conducted to improve optical cross-talk between pixel cells. According to an embodiment of the present invention, one or more deep-array implants of a first conductivity type are used to dope predefined regions of a well of a second conductivity type. This way, first conductivity type dopants from the one or more deep-array implants counterdope second conductivity type dopants from the predefined regions of the well. The dosage and energy of each deep-array implant may be optimized so that the collection of signal carriers by the photosensitive region and the photoresponse for different wavelengths are maximized.

Abstract: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Abstract: A semiconductor memory device able to increase the effective area of a capacitor in a memory cell and ensure a sufficient amount of charge contained in a read signal while maintaining the smallest cell area and a method for producing the same, wherein a first node electrode, a first ferroelectric film, and plate electrodes form four ferroelectric capacitors, plate electrodes, a second ferroelectric film, and a second node electrode form other four ferroelectric capacitors, the first node electrode is electrically connected to the second node electrode, a capacitor below a plate electrode is connected in parallel with the capacitor above the plate electrode, and these two capacitors connected in parallel form a memory cell storing 1 bit of data.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N−S and/or a second drain layer N−D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

Abstract: A semiconductor device having a capacitor according to the present invention has a storage node and a cell plate opposed to each other through a capacitor dielectric layer, and at least either the storage node or the cell plate is formed to have a mixed crystal layer of SiGe containing a p-type impurity. Thus, a semiconductor device having a capacitor capable of effectively preventing reduction of the capacitance can be obtained.

Abstract: A non-volatile semiconductor memory device according to the present invention includes: a plurality of element isolation regions formed at predetermined intervals in the main surface of a semiconductor substrate; a first silicon oxide film, a nitride film and a second silicon oxide film formed on the semiconductor substrate; a word line formed on the second silicon oxide film; an interlayer insulating film formed on the word line; a plurality of bit lines formed on the interlayer insulating film in a plurality of regions positioned above the plurality of element isolation regions; and an interlayer insulating film formed between the bit lines. Accordingly, in this non-volatile semiconductor memory device, the withstand voltage between the bit lines increases and, therefore, the occurrence of current leakage can be prevented so that an improvement in performance can be implemented. In addition, the manufacturing cost can be lowered.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of improving the characteristics of the semiconductor integrated circuit device by reducing a leakage current of a capacitor used in a DRAM memory cell. A data storage capacitor connected to a data transfer MISFET in a memory cell forming area via plugs is formed in the following manner. That is, a lower electrode composed of an Ru film is formed in a hole in a silicon oxide film, and then, a tantalum oxide film is deposited on the lower electrode. Thereafter, a first thermal treatment in an oxidizing atmosphere is performed to the film at a temperature sufficient to repair an oxygen defect and having no influence on the materials below the tantalum oxide film. Further, a second thermal treatment in an inactive atmosphere is performed at a temperature at which the tantalum oxide film is not completely crystallized (650° C.) and higher than that applied in the later process.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Abstract: The present invention describes a method for fabricating flash memory. In accordance with the present invention, the forming of the floating gate does not require an additional photolithography step. As a result, the misalignment problem between the floating gate and the active area may be resolved. On the other hand, because of the specific floating gate structure of the present invention, high coupling capacitance between the floating gate and control gate can be achieved by recessing the shallow trench isolation more. Therefore, the method does not sacrifice the whole cell size.

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: The present invention provides a system for efficiently producing versatile multiple input floating gate structures. The present invention provides multiple-input floating gate device (100, 400) that has a first input (106, 406) formed in a first active device region (202, 502) and a second input (108, 408) formed in a second active device region (204, 504). A floating gate (200, 500) is disposed upon the first and second inputs, separated from the inputs by a dielectric layer. A device body, formed in a third active device region (210, 506), is coupled to the first and second inputs through the floating gate.

Abstract: [Problem] There are provided a semiconductor device which is operable with a small occupied area, high reliability, and low power consumption, a nonvolatile semiconductor storage apparatus using the device and a manufacture method of the device.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions, each having a pair of upwardly extending sharp edges that extend lengthwise parallel to, and are adjacent to, one of the isolation regions. Control gates are each formed with a substantially vertical face portion by covering a portion of a conductive layer with a protective layer, and performing an anisotropic etch to remove the exposed portion of the conductive layer. An insulation sidewall spacer is formed against the vertical face portion. The control gates have protruding portions that extend over the floating gates, including portions of the pair of upwardly extending sharp edges.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.