Abstract: A circuit combination (16,86) is presented for providing digital signals indicative of slew rates of drive signals (112,140) provided to H-bridge power drive transistors (60,62,64) of motor windings (66) of a mass data storage device (10). The circuit combination includes a plurality of predriver circuits (53-55) producing predrive signals according to a commutation sequence for connection to respective the power drive transistors (60,62,64). A multiplexer (40) is connected to selectively direct at least some of the drive signals to a multiplexer output port, and a digital comparison circuit (86) receives the at least some drive signals from the multiplexer output port and produces a digital outputs (120,158) having state time changes in dependence upon rise and fall times of the predriver output signals.

Abstract: A circuit (16,86) provides digital signals indicative of slew rates of phase signals (220) of H-bridge power drive transistors (60,62,64) of motor windings (66) of a mass data storage device (10). The circuit uses up and down phase control signals (UP,DN) to initiate up and down voltage changes in the motor phase signals. A portion of the circuit (180) produces a state change in a phase status output signal (196) when the phase signal (220) is less than a supply voltage (186). A digital comparison circuit (210) compares the phase status output signal (196) and the up and down control signals (UP,DN), and produces respective rise and fall digital outputs (216,217) when the up and down phase control signals and the phase status output signal are the same. The respective rise and fall digital outputs (222,224) have state change timings that indicate rise and fall times of said motor phase signals (220).

Abstract: A novel method and apparatus is presented for reducing the slew rate signals on transmission lines of integrated circuits. When a transmission line is to be driven to a state by a driver device, the voltage on predrive line controlling the driver device is pulled to a level at or very near to the turn-on threshold voltage the driver device, much more quickly than the turn-on setup time of the driver device. A programmed impedance is then connected between an “on” voltage source and the predrive line to result in a controlled slope of the transmission line signal. Once the voltage level on the transmission line reaches a predetermined reference voltage (e.g., the saturation voltage of the driver device, the predrive line is quickly pulled to the “on” voltage level.

Abstract: A novel method and apparatus is presented for reducing the slew rate signals on transmission lines of integrated circuits by stepwise ramping up or down the voltage level on the transmission line. Switched capacitors or current sources are connected to either directly to the transmission line itself, or to the control input of a driver device characterized by a linear region during which the output voltage on the transmission line is proportional to the voltage seen at the control input.

Abstract: A programmable termination circuit (12) selectively providing a termination voltage to a driver or receiver of a high-speed serial link, such as CML I/O's. The programmable termination circuit (12) is adapted for use both at a transmitter front end (10) and at a receiver front-end (20) to selectively terminate the respective circuit to one of multiple available voltage supplies (VDDA, VDDT), such as 1.8 volts and 3.3 volts. The programmable termination circuit is software controllable via a single control signal (TS). A level shifter (14) circuit is provided for coupling the termination control signal (TS) to the programmable termination circuit (12) to level shift the termination control signal to a logic level suitable with large FETs (M1, M2) coupled to and controlling the connection of the voltage supplies.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: FIFO queues enable multiple accesses to data stored therein. A release pointer points to a queue location containing previously read data until a release signal is asserted that changes the release pointer while a read pointer is used to read data from the queue. The repeat signal allows the read pointer to reread previously read data. Asserting the repeat signal sets the read pointer to the value of the release pointer. Once data is no longer needed, the release signal is asserted, causing the release pointer to be incremented with the read pointer thereby freeing memory locations. FIFO queues may comprise multiple release pointers, multiple release and multiple repeat signals. FIFO queues may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues may comprise multiple read pointers and an input signal for determining which read pointer is used.

Abstract: A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB.

Abstract: A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.

Abstract: According to the present invention, a data transmitting/receiving buffer provides an AND 5a for obtaining a logical product of an output enable signal/OE and receiving data RD, and outputting a receiving trigger signal RTG; inverter 6 for inverting the output enable signal/OE; and an AND 5b for obtaining a logical product of an output signal in the inverter 6 and transmitting data TD, and for outputting a receiving trigger signal RTG. It is possible to observe the only receiving signal by observing differential signals D+, D− at the cable side 30 by a receiving trigger signal RTG with an oscilloscope 40. Further, it is possible to observe the only transmitting signal by observing the differential signals D+, D− BY A TRANSMITTNG TRIGGER SIGNAL TTG. Thereby, a data transmitting/receiving buffer can select waveforms of a transmitting signal and a receiving signal to observe the selected waveform.

Abstract: Various systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units that are each configured to generate the clock enable signal for a respective one of the CSRs.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

Abstract: The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: The circuit comprises a plurality of supply modules for delivering current to a common load. Each supply module is equipped with a driving circuit for controlling the current delivered by the module. The supply modules are connected together by a share bus on which a signal is present for balancing the current delivered by each supply module, in such as way as to control and reduce the difference between the current delivered by a dominant supply module and the current delivered by the remaining supply modules of the circuit. Associated to each supply module are means for generating a PWM signal, the duration of which is proportional to the current delivered by the respective supply module. In addition, each supply module is connected to the share bus in such a way that on the latter there is present a digital share signal, which is a function of the digital PWM signal generated by the dominant supply module.

Abstract: A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a clock frequency of second clock domain logic. Each flip flop is capable of sampling data only on an edge of a clock and outputting data only on an edge of the clock. By utilizing flip flops in the synchronizer, data values are only allowed to change on clock edges. This, in turn, greatly improves clock skew tolerance, and also setup time margins for the first clock domain logic and for the second clock domain logic.

Abstract: A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

Abstract: The present invention provides a DLL (Delay-Locked Loop) circuit having: a delay device (1) for generating at least one delayed clock signal (7) from an input clock signal (6); a phase detector (2) for comparing the delayed clock signal (7) with the input clock signal (6); a first control device (3, 4) for generating a first control signal (5) for influencing a delay time of the delay device (1); a device (12) for generating a signal Q (Q), whose frequency is proportional to the reciprocal of the delay time (Delay) of the delay device (1); a device (13, 23) for evaluating the signal Q (Q) and generating an output signal (17); and a second control device (15) for modifying the first control signal in accordance with the output signal (17). The present invention likewise provides a method for generating a control signal of a DLL circuit.

Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Abstract: Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance.

Abstract: A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the adjacent wiring 4, it is made possible to change the delay of the signal S3 in the signal wiring 3 in several picoseconds, by using crosstalk with the signal S4 in the signal wiring 4.The inventive delay control circuit device can be provided by simply adding adjacent wiring 4 and a control circuit 13 to signal wiring 3. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Abstract: An improved apparatus and method for interfacing a time variant waveform between two hardware environments. In one aspect, the invention comprises a circuit for accurately simulating the output of one or more types of sensing device (e.g., passive bridge pressure transducer) for use with a plurality of different monitoring and/or analysis devices, thereby obviating the need for specialized interface circuitry adapted to each different monitor/analyzer. In one exemplary embodiment, the sensing device comprises a non-invasive blood pressure monitor (NIBPM), which universally interfaces with prior art patient monitors via the interface circuit of the invention. In a second aspect of the invention, an improved NIBPM device incorporating the interface circuit is disclosed. An improved disconnect circuit adapted to sense the status of the electrical connection between the sensing device and monitor is also described.

Abstract: Analog circuitry is disclosed for conditioning a signal from linear and rotary variable differential transformers having a primary winding, a pair of secondary windings and a movable core. The circuitry includes a unique closed loop negative feedback mechanism which, over time, adjusts the frequency of a voltage controlled oscillator so that a steady-state condition is achieved within the circuitry, whereby the total integrated value of the secondary winding voltages at an integrator remains equal to a reference voltage, thereby reducing the computational burden associated with solving an equation to determine the position of the movable core of the transformer.

Abstract: A voltage clamping circuit comprises a first high current gain circuit adapted to receive current from the first line; and a first switching circuit that turns on the first high current gain circuit to flow current away from the first line when the first switching circuit senses a first voltage from the first line above a clamping voltage, and turns off the first high current gain circuit when the first switching circuit senses the first voltage below the clamping voltage.

Abstract: A circuit and methods for use in increasing both bandwidth and switching speed of CML circuits. Two differential pairs are provided with one differential pair having a size that is a fraction of the other pair. Thus, one pair will have a size of W while the other will have a size of W/A. Each one of the first differential pair is coupled to at least one of the second pair. By reconfiguring the connections between the two pairs, circuits which have fast charging/discharging times and increased bandwidth are obtained.

Abstract: The invention relates to a temperature sensor having a first FET transistor circuit and a second FET transistor circuit and also to a method for operating a temperature sensor. Both FET transistor circuits are operated at an operating point that lies outside the temperature-independent operating point. The difference between the voltages at the first and second FET transistor circuits is evaluated as a measure of the temperature at one of the FET transistor circuits. The invention enables the temperature sensor to provide a relatively large output signal even in the case of only small changes in temperature.

Abstract: A buried fuse reading device includes at least one buried fuse and at least one sense amplifier sensing a condition of the buried fuse. A validation circuit in the buried fuse reading device detects and indicates when output from the sense amplifier is valid.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap-cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A resistance adjustable of resistance mirror circuit comprises: a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value nI0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.

Abstract: A current switch circuit including a current switch including a first transistor and a second transistor connected as a differential pair and receiving a differential logic signal at their bases, and logic signal controlling circuitry coupled to the first and second transistors for offsetting a transition starting point of the differential logic signal to offset a self-heating induced shift in a switching threshold of the current switch.

Abstract: A variable time constant integrator includes an amplifier configured to generate an output signal, a capacitor coupled to provide feedback to the amplifier, and a variable gain element coupled to the output of the amplifier and to the capacitor. The variable gain element is configured to provide the product of a gain and the output signal to the capacitor. The variable gain element is also configured to receive an indication of a new value of the gain and to responsively set the gain equal to the new value of the gain. Adjusting the gain of the variable gain element adjusts the integrator's time constant.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A variable impedance load (104) is provided at the output of a radio frequency (RF) driver amplifier (102) having a variable gain. In an exemplary embodiment, the variable load (104) comprises a resistor (R) in series with a semiconductor device (M1). The semiconductor device (M1) has an impedance level determined by a drive current. The value of the drive current is related to the gain of the RF driver amplifier (102).

Abstract: A power amplifier clipping circuit prevents sudden output changes when clipped from excessive input voltage, and includes an input voltage divider, two bias transistors connected to a positive voltage source, a third bias transistor connected to the first bias transistor and a first differential amplifier, a first current source connected to the third bias transistor and a negative voltage source and the first differential amplifier, fourth and fifth bias transistors connected to a negative voltage source and a second differential amplifier, a sixth bias transistor connected to the fourth bias transistor and the second differential amplifier, a second current source connected to the sixth bias transistor and a positive voltage source, a first output voltage controller connected between the negative voltage source and an output with a serial input resistor, and a second output voltage controller connected between the positive voltage source and the output and power amplifier.

Abstract: A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.

Abstract: A circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.

Abstract: A FET amplifier which minimizes the worsening of the distortion-susceptibility due to variations in the ambient temperature of operation is to be provided. An LDMOS FET 1, whose source terminal is grounded and to which are applied a gate voltage Vgs from a gate bias terminal 3 via a temperature-compensating circuit 2 and a choke coil and a drain voltage Vds from a drain bias terminal 4 via a choke coil operates as a source-grounded type amplifier. In the temperature compensating circuit 2, the resistances of fixed resistance elements 21 and 22 connected in parallel are set to be the same or have the same number of digits, and those of thermosensitive resistance elements (thermistors) 23 and 24 are set to be a combination of a value greater by one digit and a value smaller by one digit than that of the fixed resistance element 21 or the fixed resistance element 22 at the standard level (+25° C.) in the ambient temperature range of operation.

Abstract: The present invention provides a communication semiconductor integrated circuit device equipped with a high-frequency power amplifier circuit including a gain control amplifier and a bias circuit which supplies such a bias current as to linearly change the gain of the gain control amplifier, and a wireless communication system using the same. A bias current generating circuit which supplies a bias current to a linear amplifier that constitutes the communication high-frequency power amplifier circuit, comprises a plurality of variable current sources respectively different in current value and start level. These variable current sources are controlled according to an input control voltage and thereby combine their currents into a bias current. The combined bias current changes exponentially with respect to the input control voltage.

Abstract: An RF power amplifier for amplifying an RF signal over a broad range of power with improved efficiency includes a main amplifier for amplifying an RF signal over a first range of power and with a power saturation level below the maximum of the broad range of power. A plurality of auxiliary amplifiers are connected in parallel with the main amplifier with each of the auxiliary amplifiers being biased to sequentially provide an amplified output signal after the main amplifier approaches saturation. The input signal is applied through a signal splitter to the main amplifier and the plurality of auxiliary amplifiers, and an output for receiving amplified output signals from the main amplifier and the plurality of auxiliary amplifiers includes a resistive load R/2. The split input signal is applied through a 90° transformer to the main amplifier, and the outputs of the auxiliary amplifiers are applied through 90° transformers to a output load.

Abstract: A circuit for power amplification for an audio amplifier that reduces power supply noise amplified to the load. The circuit takes the prior art circuit's existing output coupling cap and power supply decoupling cap and connecting them in series from the power supply to ground. The output of the amplifier is then directly coupled to the load and the other side of the load is connected at the “null point” between the two capacitors.

Abstract: A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (&Dgr;fmax) in the oscillating frequency; (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term (187, 331) can be used to expedite correction of the digitally controlled oscillator when large phase error changes (335) occur.

Abstract: A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting device is provided between the oscillator and the PLL. This phase shifting device can temporally shift the edges of the signal output by the oscillator to a variable extent, and feeds the resultant signal to the PLL as an input signal. Such a clock signal generating device makes it possible to realize a spread spectrum oscillator which is constructed in a simple manner and can be made small.

Abstract: A quadrature vestigial sideband (QVSB) communication system provide bandwidth efficient data transmission using cross coupled data signaling during both transmit and receive having controlled intersymbol interference. The QVSB modem includes cross coupled arm transmit and receive data filtering on both of the I&Q channels providing a bandwidth efficient QVSB spectra. A quadrature crosstalk maximum likelihood sequence estimator implements a Viterbi decoding algorithm for providing estimated data sequence outputs. The receiver is a coherently aided demodulator synchronized by a synchronization loop providing time and phase references using the estimated data sequence outputs.

Abstract: A method of tuning individual filters in an assembly of filters connected to a manifold, such as a microwave multiplexer, prior to assembly of the multiplexer, is accomplished by energizing a subject filter to be tuned with an electromagnetic signal provided by a network analyzer. The filter is tuned by adjustment of a tuning component, such as a tuning screw within the filter, while the network analyzer presents the transfer function of the filter during the tuning process. To compensate for tuning effects of the other filters and of the manifold, which are manifested upon a connection of the filters to the manifold, the transfer function of the assembly is loaded into a computer of the network analyzer. Thereby, during a tuning of the filter, the presentation of the filter transfer function by the network analyzer includes the tuning effects of the rest of the assembly.

Abstract: The invention relates to a method of resolving collisions between at an arrangement with a flat board comprising microwave integrated modules and at least one microstrip lines for guiding a signal on said flat board and a waveguide for guiding the signal out of the flat board. According to the present invention the flat board is perforated at the intersection between the flat board and the waveguide, a stand-alone piece of comprising a microstrip line termination and being adjusted over the perforation, the microstrip line termination coinciding with the extremity of one microstrip line on the flat board.