Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: The present invention proposes a novel structure of nonvolatile memory. The aspect of the present invention includes two serially connected PMOS transistor. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The present invention may “automatically inject” carrier into floating gate for programming the status of the device.

Abstract: A memory device that is free from problems resulted from the characteristics of nonvolatile memory chips. The problems are specifically those occurring at the time of data transfer between nonvolatile memory chips, e.g., data error or program error occurring after data transfer. In the memory device, an error correction code process unit applies error detection to data read from a nonvolatile memory chip to a data line for data transfer. For such detection, an error correction code for the data is referred to. At the time of data transfer between the nonvolatile memory chips, if the data is detected as containing a correctable error, a writing unit writes the corrected data to a nonvolatile memory, which is the transfer destination. In this manner, at the time of data transfer between the nonvolatile memory chips, the error never fails to be detected before data writing.

Abstract: Apparatus including a virtual ground array, mass storage non-volatile memory device, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. Methods for operating the mass storage device are also disclosed herein.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of the memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions, data latch circuits for holding the initial set-up data read out from the initial set-up data region, a controller for controlling data program and erase operations for the memory cell array, and a clock generator for generating a clock signal that is used to define an operation timing of the controller, wherein the controller is configured to perform such an initial set-up operation that sequentially reads out the plurality of initial set-up data stored in the initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, the initial set-up operation being so performed as to read out a clock cycle adjustment data within the plurality of ini

Abstract: System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.

Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

Abstract: A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

Abstract: A non-volatile memory cell (FIG. 3) is provided which includes three transistors, a floating gate non-volatile storage transistor (303) and two cascode connected select transistors (301-302). The two cascoded select transistors (301-302) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor (301) is set to prevent breakdown of the oxide in the first cascode transistor (301) as well as the second cascode transistor (302). A value of an unselect voltage applied to the gate of the second cascode connected transistor (302) can be selected so that the voltage passed to the floating gate storage transistor (303) will not result in a program drain disturb, or source disturb condition.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: Hardware having a selected storage capacity within a computer configuration is emulated by (a) representing to an operating system of the computer configuration the presence of the hardware having the selected storage capacity and addresses for reading data therefrom and writing data thereto, (b) writing data to an address of the hardware by (i) writing the data to an address of a data store with which the hardware address is associated, or (ii) writing the data to an address of the data store with which no hardware address is associated, and associating the hardware address with that data store address, and (c) reading data from a hardware address by (i) reading the data from a data store address with which the hardware address has been associated in the writing step, or (ii) returning data that has not been written to the hardware in the writing step.

Abstract: A volume having a selected storage capacity is emulated within a computer configuration by (a) representing to an operating system of the computer configuration the presence of the volume having the selected storage capacity and addresses for reading data therefrom and writing data thereto, (b) writing data to an address of the volume by, (i) writing the data to an address of a data store with which the volume address is associated, or (ii) writing the data to an address of the data store with which no volume address is associated, and associating the volume address with that data store address, and (c) reading data from a volume address by, (i) reading the data from a data store address with which the volume address has been associated in accordance with the writing step, or (ii) returning data that has not been written to the volume in the writing step.

Abstract: A computer configuration having an original volume with a first storage capacity is altered to appear as a computer configuration having the original and an additional, readable/writable volume by (a) representing to an operating system of the computer configuration the presence of the additional volume, (b) writing data to an address of the volume by (i) writing the data to an address of a data store with which the volume address is associated, or (ii) writing the data to an address of the data store with which no volume address is associated, and associating the volume address with that data store address, and (c) reading data from a volume address by (i) reading the data from a data store address with which the volume address has been associated in the writing step, or (ii) returning data that has not been written to the volume in the writing step.

Abstract: Hardware having selected storage characteristics is emulated within a computer configuration by, (a) representing to an operating system of the computer configuration the presence of the hardware having the selected storage characteristics and addresses for reading data therefrom and writing data thereto, (b) writing data to an address of the hardware by (i) writing the data to an address of a data store with which the hardware address is associated, or (ii) writing the data to an address of the data store with which no hardware address is associated, and associating the hardware address with that data store address, and (c) reading data from a hardware address by (i) reading the data from a data store address with which the hardware address has been associated in the writing step, or (ii) returning data that has not been written to the hardware in the writing step.

Abstract: A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present invention, two address bits are provided to a binary logic function device. The binary logic function device uses the two address bits and predetermined logic functions (i.e., functions that represent a plurality of read-only data values) to produce a binary value—which is the requested read-only data. In another embodiment, the binary values produced by the binary logic function device are provided to at least one multiplexer. The at least one multiplexer uses at least a portion of the remaining bits (i.e., the address bits not being provided to the binary logic function device) to select (or narrow down) which binary values may be the read-only data requested. If the output of the at least one multiplexer contains more than one binary value, then those values are provided to at least one other multiplexer.

Abstract: The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored.

Abstract: A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, which are organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays; row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: An optical disc is constituted by a recording region for recording contents data, a readout region, and a protect region for recording copyright data of the contents data in this order from an inside. Access cannot be obtained to a groove track outside the readout region except that legal reproduction and recording is performed, and the groove track records a part of contents key data used for encrypting and decoding contents data.

Abstract: An apparatus and method implemented in embedded software that provides instant startup functionality to host computers. The apparatus consists of an embedded controller with microprocessor and interface logic and a large amount of cache memory that is battery protected. The method detects data requested by the host during boot sequences, and saves that and associated meta-data in non-volatile memory. The boot process optimizer can then use this information on subsequent starts to provide the data from the faster cache memory instead of a relatively slower mechanically spinning hard disk drives or other mass memory devices. By utilizing locked in memory indicators, the boot data stored in cache memory will be preserved during subsequent accesses by post-boot operations of the host.

Abstract: A magnetoresistive tunnel element includes first and second electrodes and a tunnel barrier disposed between the two electrodes, the tunnel barrier having at least two barrier layers made of different barrier materials, the profile of a quantum mechanical barrier height within the tunnel barrier being asymmetrical and the conductivity of the tunnel element, therefore, being dependent on the polarity of a voltage Um between the two electrodes. Also provided is a magnetoresistive memory cell, a cell array of magnetoresistive memory cells, and a memory device having cell arrays.

Abstract: In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.

Abstract: A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract: Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. The method includes forming a first layer of insulating material on the first layer of the electrically conductive material. The first layer has a thickness of less than 1.0 micrometers (&mgr;m). A transmission line is formed on the first layer of insulating material. The transmission line has a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is formed on the transmission line.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

Abstract: The output of a ring oscillator that receives an internal power supply potential as an operating power supply potential to conduct an oscillation operation is counted by a counter that receives an external power supply potential as an operating power supply potential, and reset is canceled. The circuit that operates with an internal power supply potential can be reliably reset even when the rise of the internal power supply potential is delayed. By adjusting the number of stages of the inverter of a ring oscillator and the number of bits of the counter, the power-on reset time can be adjusted while suppressing increase of the area. An appropriate power-on reset signal can be generated to prevent erroneous operation even in the case where the rise of the internal power supply potential lags behind the rise of the external power supply potential.

Abstract: A memory system having power backup having memory circuits that may be set to a low power mode by means of volatile control registers, disconnects the memory circuits from the battery when low voltage conditions are detected so as to prevent reversion of the memory circuits to high current consumption modes such as would drain batteries after replacement.

Abstract: Battery backed memory for use in an industrial controller allows software disconnect of the battery and memory so that unplanned power outages may receive the benefit of battery backup, but battery power is not unduly wasted during planned power outages when data loss may be accommodated or other provisions may be made for saving data in nonvolatile memory.

Abstract: A hole driver for driving a hole in a semiconductor memory device, including a first bank controller for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank, a second bank controller for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank, a block address enable means for generating a common block address enable signal in response to output signals of the first and the second bank control means and a common block address predecoder for predecoding block address signal for each bank in response to the common block address enable signal.

Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.

Abstract: A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: Provided herein are combinations of equipment capable of providing the continuous fabrication of road surfaces and the like, by virtue of the continuous manufacture of the concretes used in making the road surface at their point of use. The invention also includes a process for fabricating a road surface or the like. By the present invention it is now possible to provide a greater quantity of road surface in a shorter amount of time as provided for in the prior art, wherein the road surface has a quick-cure time owing to the use of quick-setting cements. Such quickly laid roads are capable of handling loads of about 100,000 lbs. within about 2 hours of its being fabricated and laid in place.

Abstract: A container of liquid color material has a diaphragm liquid color pump located therewithin for providing liquid color from the container and non-drip apparatus for releaseably connecting the container with a blender for supply of liquid color thereto and methods for pumping and supplying liquid color incorporating the same.

Abstract: A fully automatic electronic milkshake mixer (10, FIG. 1) in which an operator sets scoop dial control (34, FIG. 1), based upon the number of scoops of ice-cream or related products placed in mixer cup. The mixer cup (28, FIG. 2) rotates automatically by motorized lower drive wheels (48, FIG. 1), and a top cup rim container guide/wheel assembly (54, FIG. 1) engages mixer cup upper lip (56, FIG. 2). Different sized mixer cups rotate perfectly, for faster, more complete mixing. The mixer automatically shifts from low to high speed (anti-splash feature), and turns off automatically when milkshake is done. A “ready” light (42, FIG. 1) illuminates, and a chime (68, FIG. 3) sounds—volume control and on/off being adjustable. “Manual” momentary pushbutton (32, FIG. 1) allows manual control of mixing speed and time, if desired, while cup rotates. For next milkshake, electronic mixer returns to fully automatic mode.

Abstract: An extensional flow mixer especially for viscous liquids has a housing with an end inlet connectable to a pressurized source of the liquids, and an outlet at an opposite end of the housing. A mandrel located in the cavity has protrusions with sloping side surfaces, the outer edges of which cooperate with the internal surface of the cavity to divide the cavity into a series of chambers separated by slits, such that liquid passes successively through all the chambers and slits in moving from the inlet to the outlet. The slits have cross-sectional areas which decrease in the liquid flow direction. The mandrel sides have helical grooves forming passageways with the housing wall which allow liquid to be distributed evenly around the edges of the mandrel to the inlet end or upstream chamber. The mandrel may rotate to provide additional shear mixing.

Abstract: An improved adapter bucket for a mixing apparatus adapted for mixing paints or other fluids can selectively receive either conventional cylindrical containers or non-conventional, non-cylindrical containers therein and restrain either of such container types on the apparatus during mixing operations. The adapter bucket is configured to properly register either of such containers types so that its center of gravity axis is colinearly aligned with the rotation axis of the bucket and the mixing apparatus, regardless of whether the containers' center of gravity axes and central geometric axes are coincident and colinear with each other or laterally offset with respect to each other.

Abstract: An apparatus for providing a secondary seal on mixers and similar rotating equipment that includes a stop assembly and a collar which cooperate to minimize translational movement of a mixer shaft during shutoff and to form a reversible seal between the vessel and the shaft. The apparatus provides a sealing engagement between the mixing vessel and the rotatable shaft of a mixer offering improved safety during mechanical seal replacement.

Abstract: An apparatus for providing a secondary seal on mixers and other rotating equipment that includes a stop assembly and a collar which cooperate to minimize translational movement of a mixer shaft during shutoff and to form a reversible seal between the vessel and the shaft. The apparatus provides a sealing engagement between the mixing vessel and the rotatable shaft of a mixer offering improved safety during mechanical seal replacement.

Abstract: An acoustic telemetry system for use in a borehole achieves both bi-directional and multi-hop communications without need for a wireline. Each step in the communications link comprises a processor and transceiver, which communicate with adjacent transceivers to achieve self-optimization. During operation, if communications deteriorate, each pair of transceivers can re-initiate optimization and attempt to reset parameters to achieve improved communications. Similarly, the system can also re-calibrate periodically to assure that optimal conditions are maintained.

Abstract: A two-way ultrasonic positioning and navigation system and method involve a plurality of objects each capable of transmitting and receiving ultrasonic signals. A first object transmits an initiating ultrasonic signal and identifies a second object for responding to the initiating ultrasonic signal. The second object transmits a responding ultrasonic signal after a predetermined time delay from receiving the initiating ultrasonic signal. The first objectives the responding ultrasonic signal, and determines a distance between the first object and the second object based on a time period starting at the transmission of the initiating ultrasonic signal and ending at the reception of the responding ultrasonic signal, and on knowledge about the predetermined time delay and other known in advance time delays.

Abstract: A measuring system includes a measuring apparatus (2) for obtaining pulse data and identification data related to the pulse data, and a central controlling apparatus (1, 3) for receiving the pulse data and the identification data from the measuring apparatus. The central controlling apparatus includes a data processing unit (1) for performing data processing based on the pulse data and the identification data.

Abstract: An electronic timepiece adapted to minimize a horizontal slippage of contact terminals when a display unit housing is diagonally fitted in a case. A liquid crystal panel, and an electroluminescence panel adapted to illuminate and secured to a rear surface of the liquid crystal panel are provided. A display unit housing retains the liquid crystal panel and electroluminescence panel. The display unit housing has guide holes for inserting electric terminals thereinto and holding the same therein. The electric terminals are inserted into the guide holes. Each of the electric terminals is connected at one end thereof to a rear surface of the electroluminescence panel, and at the other end thereof to a circuit board.

Abstract: The present invention provides for a programmable, period-based, time-interval monitoring system, and method, for the managed reduction of cigarette smoking over time. The purpose of the method and device is to assist and provide information for a user to manage cigarette consumption over time, at a rate set by the user, to a goal value set by a user.