Patents Issued in August 12, 2003
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Patent number: 6605482Abstract: A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device.Type: GrantFiled: October 11, 2001Date of Patent: August 12, 2003Assignee: Texas Instruments IncorporatedInventors: Francis G. Celii, Maureen A. Hanratty, Katherine E. Violette, Rick L. Wise
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Patent number: 6605483Abstract: Described is a process for manufacturing a light emitting polymer device comprising, in one embodiment, the steps of providing a transparent or non-transparent electrode-containing substrate adapted to act as a first electrode, screen printing a light emitting polymer layer, which is composed of a light emitting polymer dissolved in a solvent, onto the hole injection layer and screen printing a hole injection layer onto the transparent electrode-containing substrate on one side of the light emitting polymer layer.Type: GrantFiled: April 27, 2001Date of Patent: August 12, 2003Assignee: Add-Vision, Inc.Inventors: John G. Victor, Matthew Wilkinson, Sue Carter
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Patent number: 6605484Abstract: A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively reduces charge buildup that occurs in the manufacture of integrated circuits.Type: GrantFiled: November 30, 2001Date of Patent: August 12, 2003Assignee: Axcelis Technologies, Inc.Inventors: Alan C. Janos, Anthony Sinnot, Ivan Berry, Kevin Stewart, Robert Douglas Mohondro
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Patent number: 6605485Abstract: A p-i-n structure for use in photo laser diodes is disclosed, being formed of an GaxIn1−xN/GaN alloy (X=0→1). In the method of the subject invention, buffer layers of GaN are grown on a substrate and then doped. The active, confinement and confinement layers of p-type material are next grown and doped, if desired. The structure is masked and etched as required to expose a surface which is annealed. A p-type surface contact is formed on this annealed surface so as to be of sufficiently low resistance as to provide good quality performance for use in a device.Type: GrantFiled: May 16, 2002Date of Patent: August 12, 2003Assignee: MP Technologies, LLCInventor: Manijeh Razeghi
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Patent number: 6605486Abstract: In a GaAs type semiconductor device, InpGa1−pN (0<p≦1) is used to thereby form heterojunction having a large difference in energy gap, thereby providing a high performance semiconductor device.Type: GrantFiled: October 31, 2002Date of Patent: August 12, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Hidetoshi Fujimoto
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Patent number: 6605487Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.Type: GrantFiled: December 20, 2001Date of Patent: August 12, 2003Assignee: Infineon Technologies AktiengesellschaftInventors: Martin Franosch, Reinhard Wittmann, Catharina Pusch
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Patent number: 6605488Abstract: A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.Type: GrantFiled: October 12, 2000Date of Patent: August 12, 2003Assignee: Micron Technology, Inc.Inventor: Anders Andersson
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Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
Patent number: 6605489Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.Type: GrantFiled: May 29, 2002Date of Patent: August 12, 2003Assignee: Micron Technology, Inc.Inventor: James M. Wark -
Patent number: 6605490Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.Type: GrantFiled: July 12, 2002Date of Patent: August 12, 2003Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
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Patent number: 6605491Abstract: A method for bonding an IC chip by a non-conductive adhesive that contains between about 5 weight % and about 25 weight % of a non-conductive filler is described. The filler particles in the filler material must have a hardness that is higher, and preferably at least two times higher, than the metal material forming the bump. Moreover, the filler particles must be non-electrically conductive such that electrical shorts between a plurality of bumps on the IC chip do not occur. The concentration of the filler in the adhesive must be high enough so as to reduce the CTE of the adhesive to match that of the IC chip and the substrate, and low enough so as not to impede the electrical communication between the bumps on the IC chip and the bond pads on the substrate.Type: GrantFiled: May 21, 2002Date of Patent: August 12, 2003Assignee: Industrial Technology Research InstituteInventors: Yu-Te Hsieh, Shyh-Ming Chang, Wen-Ti Lin
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Patent number: 6605492Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.Type: GrantFiled: March 17, 2000Date of Patent: August 12, 2003Assignee: Intel CorporationInventor: Joseph C. Barrett
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Patent number: 6605493Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.Type: GrantFiled: August 29, 2001Date of Patent: August 12, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Ta-Lee Yu
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Patent number: 6605494Abstract: In the method of fabricating a TFT in accordance with the present invention, a first semiconductor layer 37 to be used as a channel is formed on a portion of an insulating layer 35 in correspondence with an underlying gate electrode 33. A second semiconductor layer 34, ohmic contact layer 41 and metal layer 45 are then successively formed on the insulating layer 35 and first semiconductor layer 37. A photoresist pattern is next formed on a portion of the ohmic contact layer other than a portion corresponding to the gate electrode. The metal layer is patterned using the photoresist pattern to form source 43 and drain 45 electrodes, and the ohmic contact layer 41 and second semiconductor layer 39 are removed using the photoresist pattern as a mask, or using the source and drain electrodes as a mask, to expose portions of the insulating layer and first semiconductor layer. A passivation layer 47 is formed to cover the insulating layer, first semiconductor layer, and source and drain electrodes.Type: GrantFiled: June 22, 2000Date of Patent: August 12, 2003Assignee: LG Electronics Inc.Inventors: Jae-Yong Park, Jae-Kyun Lee, Jung-Hoan Kim
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Patent number: 6605495Abstract: A method of forming a thin film transistor liquid crystal display includes forming a gate, a scan line and two first repair pads on a substrate first. A dielectric layer, a semiconductor layer, an etching stop layer and a metal layer are thereafter formed. After that, the metal layer and the semiconductor layer are etched to form a signal line and a source/drain. A passivation layer is formed and portions of the drain are exposed. Finally, a pixel electrode is formed and a second repair pad on top of each of the first repair pads is formed to form a repair circuit.Type: GrantFiled: January 21, 2003Date of Patent: August 12, 2003Assignee: Au Optronics Corp.Inventor: Tai-Yu Kuo
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Patent number: 6605496Abstract: Provided is a constitution for forming a polysilicon film having uniform crystallinity. To construct a structure of a bottom-gate-type TFT, a heat relaxation layer is formed to cover a gate electrode. The heat conductivity of the heat relaxation layer is lower than that of the gate electrode, and it acts to inhibit heat propagation to the gate electrode. In the step of laser crystallization of an amorphous silicon film into a polysilicon film, the heat relaxation layer prevents local temperature gradation in the film owing to the heat-absorbing effect of the underlying gate electrode. The polysilicon film formed has extremely excellent uniformity and crystallinity.Type: GrantFiled: September 14, 1998Date of Patent: August 12, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6605497Abstract: When a crystalline semiconductor thin film formed by using a catalytic element for facilitating crystallization is subjected to a heat treatment in an atmosphere containing a halogen element at a temperature exceeding 700° C., a crystal structure in which crystal grain boundaries do not substantially exist can be obtained. In the present invention, the foregoing crystalline semiconductor thin film is formed on a crystallized glass substrate which is inexpensive and has high heat resistance, so that an inexpensive semiconductor device can be provided.Type: GrantFiled: October 16, 1998Date of Patent: August 12, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Patent number: 6605498Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.Type: GrantFiled: March 29, 2002Date of Patent: August 12, 2003Assignee: Intel CorporationInventors: Anand S. Murthy, Brian S. Doyle, Brian E. Roberds
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Patent number: 6605499Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.Type: GrantFiled: November 1, 2000Date of Patent: August 12, 2003Assignee: Hyundai Electronics America, Inc.Inventor: Harold S. Crafts
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Patent number: 6605500Abstract: A method and apparatus for component to substrate assembly permits in situ reflow of a flip chip (or other suitable component) in a manner which promotes proper settling of the component as solder begins to flow at the contact points between the component and the substrate. The component is heated and held by a pick-up head while applying downforce that serves to level the component. The initiation of solder reflow can be detected with the pick-up head by sensing a decrease in the downforce. Downforce applied to the component with the pick-up head is then decreased and the retention mechanism holding the component is released, freeing the component from the pick-up head and permitting the component to properly self-center using the liquid solder's surface tension.Type: GrantFiled: March 7, 2001Date of Patent: August 12, 2003Assignee: Infotech AGInventors: Edison T. Hudson, Ernest H. Fischer
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Patent number: 6605501Abstract: A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar.Type: GrantFiled: June 6, 2002Date of Patent: August 12, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew-Hoe Ang, Eng-Hua Lim, Cher-Liang Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou
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Patent number: 6605502Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.Type: GrantFiled: June 17, 2002Date of Patent: August 12, 2003Assignee: Micron Technology, Inc.Inventors: Ravi Iyer, Steven M. McDonald, Thomas R. Glass, Zhiping Yin
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Patent number: 6605503Abstract: In the manufacture of a semiconductor memory device having a capacitor formed by arranging a dielectric film including two layers of a silicon oxide film and a silicon nitride film between two electrode films, a thin dielectric film is formed by forming the silicon nitride film on a silicon conductive film by thermally nitriding said silicon conductive film using NO gas, then laminating a silicon oxide film on said silicon nitride film by a CVD method. The erasing/writing speed of semiconductor memory devices, in particular of flash memories or the like, is improved.Type: GrantFiled: August 13, 2002Date of Patent: August 12, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tatsunori Kaneoka
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Patent number: 6605504Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.Type: GrantFiled: June 28, 2002Date of Patent: August 12, 2003Assignee: Infineon Technologies AGInventors: Venkatachalam C. JaiPrakash, Rajiv Ranade
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Patent number: 6605505Abstract: A process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.Type: GrantFiled: June 15, 2001Date of Patent: August 12, 2003Assignee: Siemens AktiengesellschaftInventors: Frank Hintermaier, Carlos Mazure-Espejo
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Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays
Patent number: 6605506Abstract: A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices; the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using a shallow-trench-isolation (STI) structure so that the applied control-gate voltage for programming and erase can be reduced; the third spacer technique is used to define the gate length of a scalable stacked-gate structure; and the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.Type: GrantFiled: January 29, 2001Date of Patent: August 12, 2003Assignee: Silicon-Based Technology Corp.Inventor: Ching-Yuan Wu -
Patent number: 6605507Abstract: To provide a non-volatile semiconductor memory device in which the word line resistance can be decreased in resistance without being accompanied by increase in chip area, and a manufacturing method for the non-volatile semiconductor memory device. In a non-volatile semiconductor memory device having a floating gate (203 of FIG. 2) and a control gate (205 of FIG. 2), a contact groove (407 of FIG. 4a) extending in the direction of a word line (102 of FIG. 1) is provided on an interlayer insulating film (404 of FIG. 4a) formed as an upper layer of the control gate, and an electrically conductive member of, for example, tungsten, is embedded in the contact groove to establish electrical connection between the wiring metal (409 of FIG. 4d) formed as an upper layer of the interlayer insulating film and the control gate with a large contact area.Type: GrantFiled: May 29, 2002Date of Patent: August 12, 2003Assignee: NEC Electronics CorporationInventors: Masato Kawata, Kuniko Kikuta
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Patent number: 6605508Abstract: The disclosed semiconductor device includes a semiconductor substrate, a logic circuit area formed on the semiconductor substrate, the logic circuit area includes transistors for driving bit lines, and a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area. Also the disclosed method of fabricating the semiconductor device includes the steps of forming a logic circuit area on a semiconductor substrate, the logic circuit area includes interconnection wirings connected to transistors for driving bit lines, forming bit lines electrically connected to the interconnection wirings at the upper side thereof, forming a silicon film connected to the bit lines at the upper side thereof and defining a cell forming area, forming transistors on the silicon film, each transistor including a gate electrode, a source electrode, and a drain electrode, and forming capacitors electrically connected to the source electrodes at the upper side of the transistor.Type: GrantFiled: June 26, 2002Date of Patent: August 12, 2003Assignee: Dongbu Electronics Co., Ltd.Inventor: Jae Kap Kim
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Patent number: 6605509Abstract: A method for forming a smooth floating gate structure for a flash memory is disclosed. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a second conductive layer are sequentially formed on the substrate. A first dielectric layer is then formed on the second conductive layer. A first hard mask layer and a second hard mask layer are formed sequentially on the first dielectric layer. A floating gate pattern is then transferred into the second hard mask layer to expose the first hard mask layer. The first hard mask layer is then etched to form a pattern and expose the first dielectric layer. A second dielectric layer is conformally formed over the second hard mask layer and the pattern; The second dielectric layer is etched back to form a spacer and expose the first dielectric layer.Type: GrantFiled: September 23, 2002Date of Patent: August 12, 2003Assignee: Winbond Electronics CorporationInventor: Wen-Kuei Hsieh
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Patent number: 6605510Abstract: A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and extends to the surface of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.Type: GrantFiled: June 6, 2002Date of Patent: August 12, 2003Assignee: Fujitsu LimitedInventor: Hirofumi Watatani
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Patent number: 6605511Abstract: A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.Type: GrantFiled: November 15, 2002Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Tuan Duc Pham, Mark T. Ramsbey, Yu Sun, Chi Chang
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Patent number: 6605512Abstract: The invention provides a non-destructive inspection method for a selectively grown film and a manufacturing method of a semiconductor device for providing a simple and convenient process control and throughput improvement. The method comprises forming a pattern in which selectively grown areas are closely arranged on a wafer for manufacturing an LSI, determining the film thickness and the composition of the selectively grown layer by analyzing optical constant data for the entire pattern, and feeding back the result to the next batch thereby conducting process control.Type: GrantFiled: December 27, 2001Date of Patent: August 12, 2003Assignee: Hitachi, Ltd.Inventor: Yukihiro Kiyota
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Patent number: 6605513Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.Type: GrantFiled: December 6, 2000Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Eric N. Paton, Ercan Adem, Jacques J. Bertrand, Paul R. Besser, Matthew S. Buynoski, John Clayton Foster, Paul L. King, George Jonathan Kluth, Minh Van Ngo, Christy Mei-Chu Woo
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Patent number: 6605514Abstract: An exemplary embodiment relates to a method of finFET patterning. The method can include patterning a fin structure above a substrate, forming amorphous carbon spacers along lateral sidewalls of the fin structure, depositing an oxide layer and polishing the oxide layer to expose top portions of the fin structure and the amorphous carbon spacers, removing amorphous carbon spacers, and depositing polysilicon where the amorphous carbon spacers were located.Type: GrantFiled: September 9, 2002Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Cyrus E. Tabery, Scott A. Bell, Srikanteswara Dakshina-Murthy
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Patent number: 6605515Abstract: In a method for manufacturing a thin-film capacitor for performing temperature compensation by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={∈0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, ∈0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, andType: GrantFiled: March 18, 2002Date of Patent: August 12, 2003Assignee: Alps Electric Co., Ltd.Inventors: Hitoshi Kitagawa, Makoto Sasaki
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Patent number: 6605516Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.Type: GrantFiled: February 13, 2001Date of Patent: August 12, 2003Inventors: Mark E. Jost, David J. Hansen, Steven M. McDonald
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Patent number: 6605517Abstract: A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer.Type: GrantFiled: May 15, 2002Date of Patent: August 12, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jayendra D. Bhakta, Krishnashree Achuthan, Angela Hui
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Patent number: 6605518Abstract: To cause a crack at a fixed position in a separation layer, a method of separating a composite member includes the steps of forming a separation layer inside a composite member, forming inside the separation layer a stress riser layer in which an in-plane stress has concentratedly been produced to an extent that does not cause separation by the in-plane stress, and enlarging the in-plane stress to cause a crack in the stress riser layer, thereby separating the composite member.Type: GrantFiled: April 26, 2000Date of Patent: August 12, 2003Assignee: Canon Kabushiki KaishaInventors: Kazuaki Ohmi, Katsumi Nakagawa, Nobuhiko Sato, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takao Yonehara
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Patent number: 6605519Abstract: A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.Type: GrantFiled: May 2, 2001Date of Patent: August 12, 2003Assignee: Unaxis USA, Inc.Inventor: David G. Lishan
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Patent number: 6605520Abstract: A method of forming a silicon-germanium (SiGe) film for a gate electrode. In a metal gate manufacture process, as the content of germanium (Ge) is increased, the surface roughness of the silicon-germanium (SiGe) film is increased, which makes difficult to secure an acceptable electrical characteristic as well as a set-up. In order to solve these problems, a method includes the spraying with a high density silicon micro-crystallite capable of increasing the nucleus creation efficiency on a gate oxide using a plasma or a tungsten (W) filament before depositing a silicon-germanium (SiGe) film. Thus, as micro-crystalline grains are formed during a preliminary stage of the silicon-germanium (SiGe) film deposition, a silicon-germanium (SiGe) film can be deposited with a reduced surface roughness.Type: GrantFiled: December 27, 2001Date of Patent: August 12, 2003Assignee: Hynix Semiconductor IncInventor: Woo Seock Cheong
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Patent number: 6605521Abstract: In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.Type: GrantFiled: October 8, 2002Date of Patent: August 12, 2003Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Atul C. Ajmera, Karanam Balasubramanyam, Tomio Katata, Shang-Bin Ko
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Patent number: 6605522Abstract: A present semiconductor device includes a plurality of bump electrodes formed over a semiconductor substrate to allow signals to be input and output to and from a semiconductor element. After the formation of the bump electrodes an organic insulting film is coated on the whole surface of a resultant wafer structure, followed by a drying, a solidifying and an etch-back step. By so doing, a top area of the bump electrode is more projected than a top area of the organic insulating film. A lead is connected by a pressure and heat to the top area of the bump electrode.Type: GrantFiled: July 27, 2000Date of Patent: August 12, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Ezawa, Masahiro Miyata
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Patent number: 6605523Abstract: A semiconductor device and a manufacturing method thereof are provided, wherein both bumps of a semiconductor chip and leads on a tape substrate can be accurately connected at the time of performing thermocompression bonding of the two using a heating tool. The film tape carrier and semiconductor chip expand due to heat applied from the heating tool of the gang bonding apparatus, so setting the pitch of the bumps and the pitch of the inner leads, taking into consideration beforehand the difference in linear expansion coefficient of the two at the time of gang bonding, solves the problem.Type: GrantFiled: March 12, 2001Date of Patent: August 12, 2003Assignee: Seiko Epson CorporationInventor: Michiyoshi Takano
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Patent number: 6605524Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.Type: GrantFiled: September 10, 2001Date of Patent: August 12, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Cheng-Yu Chu, Fu-Jier Fan, Shih-Jane Lin, Chiou-Shian Peng, Yen-Ming Chen, Kuo-Wei Lin
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Patent number: 6605525Abstract: A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process used for forming the metal vias. The metal lines are subsequently removed by either a mechanical method such as dicing with a diamond saw or by a chemical method such as wet etching. The method allows the fabrications of a wafer level package that has a multiplicity of elastomeric blocks formed on top as stress buffering layer without the CTE mismatch problem with other layers on the wafer.Type: GrantFiled: May 1, 2001Date of Patent: August 12, 2003Assignee: Industrial Technologies Research InstituteInventors: Szu-Wei Lu, Ming Lu, Jyh-Rong Lin
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Patent number: 6605526Abstract: A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.Type: GrantFiled: March 16, 2000Date of Patent: August 12, 2003Assignee: International Business Machines CorporationInventors: Wayne John Howell, Ronald Lee Mendelson, William Thomas Motsiff, Jean-Guy Quintal, Sylvain Ouimet
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Patent number: 6605527Abstract: A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.Type: GrantFiled: June 30, 2001Date of Patent: August 12, 2003Assignee: Intel CorporationInventors: Charles H. Dennison, Alice T. Wang, Patel Kanaiyalal Chaturbhai, Jenn C. Chow
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Patent number: 6605528Abstract: A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like.Type: GrantFiled: October 24, 2001Date of Patent: August 12, 2003Assignee: Megic CorporationInventors: Mou-Shiung Lin, Ming-Ta Lei, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 6605529Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.Type: GrantFiled: May 11, 2001Date of Patent: August 12, 2003Assignee: Agere Systems Inc.Inventors: Sundar Chetlur, Jennifer M. McKinley, Minesh A. Patel, Pradip K. Roy, Jonathan Zhong-Ning Zhou
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Patent number: 6605530Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.Type: GrantFiled: November 5, 2002Date of Patent: August 12, 2003Assignee: Hitachi, Ltd.Inventors: Yoshitaka Nakamura, Tsuyoshi Tamaru, Naoki Fukuda, Hidekazu Goto, Isamu Asano, Hideo Aoki, Keizo Kawakita, Satoru Yamada, Katsuhiko Tanaka, Hiroshi Sakuma, Masayoshi Hirasawa
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Patent number: 6605531Abstract: The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.Type: GrantFiled: July 31, 1998Date of Patent: August 12, 2003Assignee: Applied Materials, Inc.Inventors: Ted Guo, Wei Shi, Liang-Yuh Chen