Abstract: A fast-locking phase detector includes a first input that receives a first signal, a second input that receives a second signal, and a comparison circuit that generates an output current in proportion to a phase difference between the first signal and the second signal. An operating point circuit selectively maintains a first operating point of the phase detector when a phase of the first signal leads a phase of the second signal, and maintains a second operating point of the phase detector when the phase of the first signal lags the phase of the second signal. The first and second operating points are different from one another. Each of the first and second operating points causes the output current to vary substantially linearly for a predetermined range of both positive and negative phase differences between the first signal and the second signal.

Abstract: This invention provides a current detecting apparatus including three conductors disposed radially from a branch point such that they are branched, three hall devices disposed between conductors adjacent of the three conductors, and an operation processing circuit for detecting a current flowing through each of the three conductors based on an operation output obtained by a predetermined operation based on electric signals from the respective hall devices.

Abstract: A base barrier for an electronic meter assembly including a base assembly having a plurality of wire leads extending therefrom and a revenue guard board for monitoring phases of a meter power supply. The base barrier includes a body configured for mounting to the base assembly and further configured for retaining the revenue guard board thereto. In her aspect, the base barrier includes at least one wire management member therein.

Abstract: This ring speed detector is constructed of a magnetic sensor and a magnetic ring and is integrated with the inside of a seal device. The magnetic ring constitutes a part (core bar) of the seal device. This arrangement can enable the compacting and reduction in the number of components and improve space saving and assembling workability.

Abstract: A sensor system includes a coil positioned on a thin substrate sandwiched to a layer of mumeta, a high magnetic permeability material. The mumetal acts as an amplifier for the inductance L measured at the terminals of the coil. When a magnet passes in front a sheet of mumetal, its magnetic field locally saturates the mumetal whose magnetic permeability collapses on the saturated surface. The result is a reduction of the inductance factor (L) in proportion with that area of the coil covered by the saturated mumetal. This reduction in inductance is measured at the coil terminals to provide an estimation of that area of the coil that has been covered. By determining a particular layout of the coil, mumetal, and magnet, a predetermined electrical signal of inductance or coupling variations corresponding to movement of the magnet is provided.

Abstract: A linear variable differential transformer (LVDT) assembly comprises a housing. A tube extends into the housing. An armature mounts inside of the tube and can move longitudinally within the tube. A coil assembly, which includes a primary coil and two secondary coils mounts on the outside of the tube. The coil assembly has adjustable connection with the housing. Consequently, the coil assembly can be adjusted longitudinally with respect to the armature until the LVDT is in the null position. That occurs when the differential voltage from alternating current through the secondary coils is zero.

Abstract: An apparatus for measuring a characteristic of a specimen, includes a probe for scanning a surface of the specimen in a noncontacting state, a vibrating unit for vibrating the probe, an excitation field generating unit for generating an amplitude modulation signal which is amplitude-modulated with a modulation frequency and a carrier frequency and producing an excitation field at the surface of the specimen on the basis of the generated amplitude modulation signal, and a measuring unit for measuring a force interaction between the probe and the specimen caused by the excitation field generated at the surface of the specimen.

Abstract: An improved method for magnetic resonance imaging of a sample includes the following steps: producing a magnetic field to orient the magnetic dipoles of a sample along the z axis of an x,y,z Cartesian coordinate system; applying a first radio frequency (rf) pulse along a different axis, near the resonance frequency of the magnetic dipoles (for example, the hydrogen atoms in water); applying a gradient pulse for a time tg in order to modulate the magnetization along a preferred axis in space (for example, the z axis); allowing the magnetization to evolve for a time \zq, during which time the local variations in the susceptibility affect the excited spins; applying a second radio frequency pulse near the resonance frequency of the magnetic dipoles; allowing the sample to evolve for a second time interval TE to create observable magnetization; then detecting this magnetization, using gradients to spatially resolve the signal.

Abstract: A method of generating a map or distribution of parameters that are a function of proton transverse relaxation time (T2) constant in a target subject to localised movement (such as in abdominal tissue) by using nuclear magnetic resonance imaging. The method compensates for localised movement, (e.g. breathing artefacts) in the imaging by spatial neighboring averaging of image intensities over a region of interest subject to the localised movement. A map or distribution of T2 parameters is then calculated over the entire region of interest. To ensure accuracy and position of the T2 values, the effects of signal level off set, instrumental drift, and noise level is incorporated into the calculations.

Abstract: A probehead for nuclear magnetic resonance measurements has a network. The network comprises in series an NMR coil for receiving a sample, a line resonator as well as a probehead terminal. The line resonator is configured as a delay line.

Abstract: An NMR resonator for receiving RF signals at desired resonance frequencies from a measuring sample in a volume under investigation disposed about a coordinate origin (x,y,z=0), with a means for producing a homogeneous magnetic field B0 in the direction of a z axis, wherein superconducting conductor structures are disposed between z=−|z1| and z=+|z2| on a surface which is translation-invariant (=z-invariant) in the z direction at a radial separation from the measuring sample, is characterized in that a compensation arrangement is additionally provided on the z-invariant surface, which extends to values of at least +|z2|+0.5|r|>z>−|z1|−0.

Abstract: An abnormality detection apparatus for a power supply circuit associated with an internal combustion engine detects an abnormality that may occur in a power supply circuit, and controls the automatic stop and the automatic start of the engine based on the state of the power supply circuit. The state of charge/discharge of a battery determined based on the electric potential of a terminal located between the battery and a generator-motor or a load is compared with the current through the battery detected by an ammeter. If there is a contradiction therebetween, it is determined that an abnormality has occurred somewhere in the power supply circuit including the battery. When it is determined that the power supply circuit has an abnormality, the apparatus performs such a control as to prevent the automatic stop/start control in which the engine is automatically stopped if a predetermined condition is met, and in which the engine is automatically restarted when the condition is unmet after being met.

Abstract: A sensible container for measuring conductive parameters in the liquid and acquiring properties of water in the liquid, consists of: a seat; a cup body installed at the seat, at least one probe being installed at a bottom of the cup body for contacting the liquid for measuring the resistance parameters of the liquid, such as concentration, pH value, salty and sugariness in the liquid; a measuring body at an interior of the seat and electrically connected to the probe for measuring the conductive parameters of the liquid; a display installed at an outer surface of the seat; and connected to the measuring body for displaying the measuring result.

Abstract: A test system for testing the wiring configuration of a programming plug 10 for a gas turbine engine control unit 16 includes an array of multiplexers 28. The multiplexers concurrently acquiring one data bit from a prescribed data pin in each of several groups of data pins projecting from the plug. A computer operating under the authority of an executable computer program produces an incrementable selection signal to successively prescribe the individual data pins from which data is to be acquired. The system also includes standards against which the condition or validity of the wiring configuration is assessed. A display system, such as a video monitor reports the condition of the programming plug.

Abstract: In a quasi-hemispherical Fabry-Perot resonator for the non-destructive determination of the surface resistance Rs of electrically conductive thin material films, spherical and planar mirrors are disposed opposite each other in a double shielded cooled resonator space structure supported on individual base plates and the planar mirror, on which a wafer with the thin material film is supported, is mounted on a support arm which extends through the double shield structure. Shield sections through which the support arm extends are supported on pivot arms which are pivotally mounted in the center of the base plates and the shield sections are engaged by the support arm so that they move along with the support arm when the support arm is moved sidewardly for a positioning change of the planar mirror thereby preventing radiation leakage from the resonator space.

Abstract: A method for measuring the film thickness with the help of a measuring head (12), which is held with a holding device (14) against the film (10), so that the latter is deflected, wherein the reaction force (F), exerted by the film (10) on the measuring head (12), is measured and controlled to a specified nominal value by the movement of the measuring head.

Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.

Abstract: In order to make a connection to a test bus on a printed circuit board within a system or platform for the purpose of testing circuits within the system, a regular pattern of contact points which are coupled to the circuits to be tested are formed on the printed circuit board. The contact points are contacted with a plurality of spring loaded contacts, supported in a pattern which is the same as the pattern of contact points, with the spring loaded contacts being coupled to test equipment for testing the circuits.

Abstract: A method and apparatus of interconnecting with a system board is presented. A system board having a metal stiffener mounted thereon is provided with an opening in the stiffener to provide access to an area of interest on the system board. A probe test assembly is positioned a the opening and secured to the stiffener when testing is desired to provide access to the pins of the device under test (e.g., a Multi Chip Module (MCM) on the system board). Alternatively, a system enhancement device, such as an MCM or Single Chip Module (SCM) having additional Central Processing Units (CPU's) or other features, may be installed on the system board at the opening in the stiffener to enhance the function of the system board. Another alternate includes an interface assembly positioned at the opening in the stiffener. A cover is positioned at the opening and secured to the stiffener at all other times.

Abstract: An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.

Abstract: A temperature-controlled semiconductor wafer chuck system, the chuck being configured for mounting on a prober stage of a wafer probe test station. The chuck having a top surface and a bottom surface including a heat sink configuration for removal of thermal energy from the chuck. A primary heater configured to add heat to the chuck is adjacent the top surface of the chuck. A secondary heater is adjacent to the bottom of the chuck, whereby the temperature of the top surface of the chuck and the bottom of the chuck can be independently controlled. The chuck may include a plurality of layers above the heat sink which may be connected to accommodate differential expansion and contraction, thereby minimizing distortion of the chuck due to thermal effects. The heat sink and associated layers are integrally connected and are configured to stiffen the chuck to resist deformation due to forces applied to the chuck by probe pins.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: A logic input circuit for an industrial equipment automatic control system supplied by a DC voltage source, in particular a battery (16), comprises a voltage step-up energy converter (12) composed of an inductance coil (L) and a switching transistor (TR), connected to the input (E1) of the circuit (10); a logic level detector (DL) having a optocoupler; and a clock circuit (H) controlling the transistor (TR) by adjusting the frequency or the duty cycle to perform voltage matching with the signals applied to the input (E1), and also the value of the voltage surge generated in logic high state (1) by the inductance coil (L) when switching of the transistor (TR) to the off state takes place.

Abstract: Methods and apparatus for providing precision on-chip termination of transmission lines are provided which enable the termination of transmission lines using on-chip resistors configured into networks, which have resistances related to the resistance of an external reference resistor. The external reference resistor is used to configure an on-chip reference resistor network so that it has a resistance related to the resistance of the external reference resistor. Termination resistor networks are then configured so that their resistances bear a predetermined relationship to the resistance of the on-chip reference resistor network. In one embodiment the resistance of each of the termination resistor networks is substantially the same as the characteristic impedances of each of the transmission lines.

Abstract: A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding multiplexer with less number of input signals. In one embodiment, each of a number of 8-input multiplexers shares both common input signals and common selection signals with a neighboring multiplexer. Even wider multiplexers can be achieved by cascading the multiplexers in a conventional manner.

Abstract: A programmable logic configuration device is disclosed having a configuration memory accessible by a controller of the configuration device and by a second device. Arbitration circuitry is provided for arbitrating access to the configuration memory between the configuration controller and the second device.

Abstract: Systems and methods for programmable logic arrays having depletion mode, non volatile p-channel floating gate transistors with ultra thin tunnel oxides are provided. The programmable logic arrays of the present invention can be programmed with voltages of 2.0 to 3.0 Volts and the normal operating voltages on the control gates are of the order 1.0 Volt. The depletion mode, non volatile p-channel floating gate transistors the present invention, include a range of floating gate potentials over which charge can not leak on to or off of the floating gate. The non volatile p-channel floating gate transistors in the programmable logic array include an oxide layer of less than 50 Angstroms (Å) which separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: A window voltage comparator, which determines whether a difference between two voltages is greater or smaller than a set value, is equipped with a first differential pair including a first transistor to which a first input voltage is applied and a second transistor to which a second input voltage is applied, a second differential pair including a third transistor to which a first reference voltage is applied and a fourth transistor to which a second reference voltage is applied, and a comparison circuit that compares the sum of drain currents of the first and fourth transistors with the sum of drain currents of the second and third transistors and thereby determines whether a difference between the first input voltage and the second input voltage is greater or smaller than a set value.

Abstract: A window comparator is disclosed having a 1st and a 2nd voltage input wherein the window comparator is fully differential with respect to the 1st and 2nd voltage inputs. Two differential pairs control the state of a zero-crossing comparator in response to the difference between the 1st and 2nd voltage inputs.

Abstract: An apparatus and method for processing a differential-type signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic pattern are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle.

Abstract: A semiconductor device has a transistor that controls, according to the resistance of the load externally connected to the output terminal thereof, the current fed to the base of an output-stage transistor for driving the load to turn it on. In this circuit configuration, even if a base current of the output-stage transistor is so determined as to permit the semiconductor device to drive the heaviest permissible load, only a reduced amount of extra current is fed to the base of the output-stage transistor when it is turned on with a light load connected to the semiconductor device.

Abstract: A method and apparatus for supporting a voltage in an output driver circuit and smoothing the response of the voltage to switching operations in the output driver circuit. A capacitive element, such as a capacitor or transistor, is coupled to the gate of a drive transistor in an output driver leg circuit of an output driver and to a switched signal voltage. By coupling the capacitive element to a signal voltage other than ground, a smaller capacitive element is required than that required for coupling the capacitive element to ground. An embodiment of the invention further includes a plurality of capacitive elements configured such that the voltage support is applied to the gate of the drive transistor in phases rather than all at once to smooth voltage response to drive transistor switching. Transistors having relatively longer effective channel lengths may be used as the capacitive elements to allow for additional phasing-in of the voltage support due to signal delay through the longer channels.

Abstract: A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

Abstract: Disclosed is a method and apparatus for converting an unstable receiver enable signal RXEN, which is based on a master clock which undergoes timing adjustments, to a stable receiver enable signal RXEN′ which is based on an externally applied clock signal. An externally applied clock signal at a frequency fc is divided by a factor N to produce N uniformly phase spaced clock signals. A clocking edge of a master clock signal which generates the receiver enable signal RXEN is associated with one of the N clocking signals which has a pulse which substantially envelopes the edge of the master clock signal which generates the RXEN signal. A new receiver enable signal RXEN′ is generated by the associated new clock signal. The receiver enable signal RXEN is therefore converted from a signal which has adjusted timing to RXEN′ which has no timing adjustment.

Abstract: Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. Using the method and structure of the invention, the voltage scalability of the latch is significantly increased. One embodiment of the invention allows for minimum supply voltages of around 120 millivolts, an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.

Abstract: This invention provides a circuit and a method for discharging a high voltage to ground level from a circuit node especially in intergrated circuits. The invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process. In addition, the discharge process takes a short amount of time. A feedback mechanism from the drains of the FETs through inverters back to gate #2 of the dual-gated FETs causes the individual drains of series connected FETs to discharge rapidly. The discharge mechanism of this invention minimizes the voltage times current power and therefore protects the integrated devices from damage.

Abstract: A level shifting circuit for level shifting a control signal which sets a Gate voltage of a power amplifier includes circuitry for adding gain to the level shift. The addition of gain to the level shift causes the gate voltage to change faster than the control voltage, and this, in turn, makes it possible to get higher dynamics to control the Gate voltage of the power amplifier. When the circuitry is utilized in a power amplifier including a plurality of amplifier stages, problems associated with the output stage showing non-monotonic behavior can be avoided. The level shifting circuit is particularly useful in power amplifiers using MESFET transistors such as power amplifiers used in cellular telephones.

Abstract: In a level shift circuit for converting a level signal of several volts into a signal of a high level and transmitting the high-level signal, as a voltage reduction unit for reducing an overvoltage applied across the gate and the source of a high-withstand-voltage element used in a signal level conversion unit, a zener diode is connected between the gate and the source such that the anode of the zener diode is on the source side, so that an overcurrent is prevented from flowing in the high-withstand-voltage element.

Abstract: A half-bridge circuit including a low-side drive module (110) and a high-side drive module (210) for driving respective lower (T1) and upper (T2) transistors. Each drive module (110, 210) is a charge trap circuit in that the low-side drive module (110) drives the low-side transistor (T1) with the charge on a capacitive load (C), and the high-side drive module (210) alternately recharges the capacitive load (C) as it is driven by a high-voltage supply. Each charge trap circuit (110, 210) also includes a diode (D1, D2) that prevents unintentional loss of charge on a gate of a driven transistor (T1, T2), and a zener diode (Z1, Z2) that clamps the gate voltage at a safe level. In this manner, the half-bridge circuit is efficiently driven without the need of an auxiliary power supply.

Abstract: The present invention refers to a circuit for current injection control comprising a first transistor having an input terminal, an output terminal and a control terminal, having the characteristic of comprising a second transistor having an input terminal connected to said output terminal of said first transistor, an output terminal and a control terminal and also comprising coupling means placed between said input terminal and said control terminal of said second transistor, said coupling means being active when said first and second transistor are in cut-off zone.

Abstract: A voltage detection device (10, 30) utilizes grounded gate J-FET transistors (16,17,18) to detect desired input voltage values. The grounded gate J-FET transistors (16,17,18) function in different modes as the input voltage varies to facilitate detecting the desired input voltage values.

Abstract: A trim bit circuit is provided that uses a cascoded differential PMOS EPROM with a fixed offset cross-coupled latch. The output sense signal is transferred by transmission gates to NMOS latched inverters. The output is buffered by another inventor. Programming is performed by a NMOS current sink that pulls the drain of the programmed (trimmed) PMOS EPROM device to ground. This places the full positive supply across the short channel trimmed device, the punchthrough inducing a trapped charge on the device. The reference (untrimmed) PMOS EPROM device is uncharged. Thus, the two PMOS EPROM transistors have unequal current. During the read mode, a replication bias voltage is induced by an external “read” power-on-reset circuit, thereby placing a few volts below positive supply on the gates of the cascode devices. This allows the Vds of the PMOS EPROM devices to increase to a little less than a volt.

Abstract: The present invention relates to a synchronous rectifier circuit having a transformer (Ü) in single-phase center-tap connection. MOSFETs containing a body diode are used as switches. The MOSFETs are connected up in such a way that a current flows only from source to drain. The channel of the MOSFETs is always switched on if current would flow through the body diode.

Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

Abstract: An integrated circuit includes storage circuits comprising isolation transistors to which a certain bias voltage may be applied. The bias voltage is generated by a bias voltage generator. A boost circuit responds to initial bias voltage transition by generating a boost current that is applied to the isolation transistors with the transitioning bias voltage.

Abstract: A voltage conversion circuit incorporate many of what were previously discrete components into a single IC, whereby the number of externally disposed discrete components is reduced as much as possible to reduce the overall size while maintaining high power conversion efficiency. This is achieved by using multiple wells within wells, and coupling the wells to specific voltage potentials to protect the circuit from failure.

Abstract: Circuits reduce the ripple in charge pump output by staggering the times at which charge is drawn from the pump. In one embodiment, the outputs of a two-array high current pump are staggered by multiplexing two pairs of clock inputs, the second pair being 180 degrees out of phase with the first clock input pair. When an EEPROM is in a programming or erase algorithm, multiplexers switch the clock inputs to the second array, effectively inverting the input clock signals. After switching, the output from the second array is 180 degrees out of phase with the output from the first array. The peak-to-peak ripple in the charge pump output is thereby reduced to about 400 mV or less.