Abstract: A ferroelectric memory device has a lower electrode, ferroelectric layer and a first portion of an upper electrode that are formed as a stack over a semiconductor substrate. Sidewalls of the stack are covered with a second portion of the upper electrode. An insulating spacer is disposed between the lower electrode and the second portion of the upper electrode. The second portion of the upper electrode is electrically connected to the first portion of the upper electrode yet electrically insulated by the insulating spacer from the lower electrode. At least one of the first and second portions of the upper electrode is formed of a hydrogen barrier layer to protect the ferroelectric layer of the stack from hydrogen ions.

Abstract: Magnetoresistance effect devices for attaining magnetically stability and for reducing a switching magnetic field. One of the ferromagnetic layers of the magnetoresistance effect device has a plane shape in which a width of an end portions is wider than a center portion sandwiched by two end portions. The end portions are not symmetrical with respect to an easy magnetization axis or longer axis of the plane shape of ferromagnetic material layer, but are substantially rotationally symmetrical with a center of the plane shape as a pivot. The plane shape may have an S-shape where its magnetic domain is stabilized and the switching magnetic field is reduced. The magnetoresistance effect devices may be used in a magnetic memory apparatus, such as a random access memory, a personal digital assistance, a magnetic reproducing head, and a magnetic information reproducing apparatus.

Abstract: A memory cell configuration includes a magnetoresistive element with an annular cross-section in a layer plane, a first line and a second line. The first and second lines crossing each other. The magnetoresistive element is disposed in the crossing region between the first line and the second line. The first line and/or the second line include at least one first portion, in which the predominant current component is oriented parallel to the layer plane, and one second portion, in which the predominant current component is oriented perpendicular to the layer plane.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode.

Abstract: The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.

Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: A fully depleted field effect transistor formed in a silicon on insulator (SOI) substrate includes a body region formed in a silicon device layer over an isolation layer of the SOI substrate. A gate is positioned above the body region and includes a base gate region adjacent the body region and a wide top gate region formed of tungsten damascene and spaced apart from the body region. An inverted T-shaped central channel region is formed between adjacent source regions and drain region in the body region.

Abstract: A semiconductor device includes an active layer of a first conductive type. A base layer of a second conductive type is selectively formed on a surface region of said active layer. A source layer of the first conductive type is selectively formed on a surface region of the base layer. An anode layer of the second conductive type is selectively formed on a surface region of the active layer, the anode layer being spaced from the base layer. A drain layer of the first conductive type is formed on a surface region between the base layer and the anode layer. A resistive layer of the first conductive type is formed on a surface region between the base layer and the drain layer. And, a gate electrode is formed above a region of the base layer between the source layer and the active layer, a gate insulating film being disposed between the base layer and the gate electrode.

Abstract: A field effect transistor including a semiconductor substrate having a first doped region and a second doped region wherein the first doped region and the second doped region are defined by an implantation property. The implantation property of the first doped region has a first implantation characteristic and the implantation property of the second doped region has a second implantation characteristic, and the first implantation characteristic are different from the second implantation characteristic.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: A semiconductor device including a semiconductor substrate; a metal gate electrode; and a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. In one embodiment, the silicon oxynitride spacer includes a first portion and a second portion, in which the first portion is formed under starving silicon conditions.

Abstract: The present invention provides an analog frequency divider structure that receives an input signal at a selected frequency and generates an output signal at a fraction, e.g. one-half, of the input frequency. In one embodiment, the analog frequency divider structure is implemented as a MEMS device having a vibratory beam extending along a longitudinal axis between two fixed ends and a piezoelectric transducer coupled to the beam. The MEMS structure further includes a conductive layer disposed on at least a portion of the vibratory beam, which is capacitively coupled to a conductive electrode. A longitudinal excitation of the piezoelectric transducer can effect application of a periodic longitudinal deformation force to the vibratory beam. This deformation force causes the beam to vibrate in a transverse direction at its natural transverse vibrational frequency, which is selected to be a fraction of the input frequency.

Abstract: To achieve a high density, high resolution, or size reduction, there is provided a solid-state image pickup device having a plurality of photoelectric conversion elements formed in a semiconductor substrate, conductive layers formed on the semiconductor substrate between the neighboring photoelectric conversion elements via an interlayer layer, a first interlayer layer formed on the photoelectric conversion elements and conductive layers, a second interlayer layer formed on the first interlayer layer, and microlenses formed above the photoelectric conversion elements, wherein the refraction index of the first interlayer layer located above the photoelectric conversion elements is different from that of the second interlayer layer.

Abstract: A solid state image sensor having micro-lenses connected to each other by filling separations between trapezoidal separated sections of a protection layer with photoresist and a manufacturing method thereof comprises trapezoidal separated sections of the protection layer which is formed on a predetermined lower layer of a semiconductor substrate and convex micro-lenses having a predetermined radius of curvature that are connected to each other by filling the separations between the separated sections of the protection layer with photoresist.

Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.

Abstract: A semiconductor device has plural output circuits. Each of the plural output circuits has a semiconductor switching element and a heat protection circuit including a diode. When the heat protection circuit in a predetermined output circuit detects that heat emitted from the semiconductor switching element in the predetermined output circuit, the heat protection circuit turns off the semiconductor switching element in the predetermined output circuit. The plural output circuits are thermally isolated from each other by a trench and an insulation film. The trench and the insulation film prevent the heat from being transmitted from the predetermined output circuit to an adjacent output circuit. Therefore, even if the heat, by which the semiconductor switching element in the predetermined output circuit is turned off, is generated at the predetermined output circuit, the semiconductor switching element in the adjacent output circuit is not turned off by the heat.

Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.

Abstract: The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.

Abstract: A resistor element has a ceramic body with a first outer electrode and a second outer electrode formed on its mutually opposite externally facing end surfaces and a plurality of mutually oppositely facing pairs of inner electrodes inside the ceramic body. Each of these pairs has a first inner electrode extending horizontally from the first outer electrode and a second inner electrode extending horizontally from the second outer electrode towards the first outer electrode and having a front end opposite and separated from the first inner electrode by a gap of a specified width, these plurality of pairs forming layers in a vertical direction. The gap of at least one of these plurality of pairs of inner electrodes is horizontally displaced from but overlapping with the gaps between the other pairs of inner electrodes. For producing such a resistor element, the distance of displacement is set according to a given target resistance value intended to be had by the resistor element.

Abstract: An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic coupling between integrated inductors associated with the same integrated circuit.

Abstract: A p type base layer is formed in one surface region of an n type base layer. An n type emitter layer is formed in a surface region of the p type base layer. An emitter electrode is formed on the n type emitter layer and the p type base layer. A trench is formed in the n type emitter layer such that extends through the p type base layer to the n type base layer. A trench gate electrode is formed in the trench. The n type base layer has such a concentration gradient continuously changing in a thickness direction thereof that its portion in contact with the p type base layer has a lower concentration than its portion in contact with the p type collector layer, with the p type collector layer having a thickness of 1 &mgr;m or less.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane.

Abstract: Chip element formation areas and scribe line areas dividing the chip formation areas are formed on a wafer. On each scribe line area, an interconnection surrounds each chip formation area, and extends to near an edge of a wafer. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method which can reduce a difference in the depositing rate of plating between the center and the periphery of the wafer.

Abstract: A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41).

Abstract: Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

Abstract: Support matrices for semiconductors are often disposed with spacers on the semiconductor chip. The spacers are composed of silicone that flows into the region of the bonding leads and prevents reliable electrical connection of the bonding leads to the semiconductor chip. In order to prevent the flow, the support matrix for integrated semiconductors has a frame, conductor track structures and at least one bonding lead for connecting the conductor track structures to the integrated semiconductor. The bonding lead has, between a bonding region and the conductor track structures, at least one barrier for preventing the flow of flowable material onto the bonding region. A method for producing such support matrices is likewise described.

Abstract: A semiconductor package including a sealing part which is bonded to a lead frame. The lead frame is formed to include portions of reduced thickness for purposes of providing maximum crack prevention during a singulation process involved in the manufacture of the semiconductor package. Additionally, the lead frame and the sealing part are sized and configured relative to each other so as to maximize the contact area therebetween, thus having the effect of improving the bonding strength between the lead frame and the sealing part. This increased contact area between the sealing part and the lead frame also maximizes the lengths of those passages susceptible to moisture permeation, thus minimizing such moisture permeation potential.

Abstract: Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: A conductive layer is formed on a dielectric substrate on which a semiconductor chip is mounted, and holes are formed passing through the layer and the substrate. After this, before the through-holes are filled with a conductive material, the conductive layer is patterned by patterning. By patterning, conductive patterns are formed from the conductive layer. After the conductive patterns are formed, the through-holes are filled with a conductive material while both ends of the holes are open, to form conductors. In the above process, one open end of each through-hole is used as a leak hole to discharge air bubbles, thus suppressing the occurrence of voids caused by bubbles, and an increase in electrical resistance in the conductors by voids can be prevented.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: The present invention provides a semiconductor device comprising: a tape wiring substrate; a semiconductor element mounted one main surface of the tape wiring substrate; a solder ball or pump electrode provided on the other surface of the tape wiring substrate while electrically connected with a predetermined position of the main surface of the tape wiring substrate including the semiconductor element; and a hollow pipe-shaped substrate; wherein the tape wiring substrate is wound around the hollow pipe-shaped substrate with the main surface arranged toward the hollow pipe-shaped substrate.

Abstract: A pressure-contact type semiconductor device comprises a plurality of semiconductor elements (IGBTs) which are in pressure contact with one another, and in which first main electrodes are electrically connected to a first common main power source plate (pressure-contact type emitter electrode plate), and second main electrodes are electrically connected to a second common main power source plate (pressure-contact type collector electrode). The pressure-contact type semiconductor device also includes a common control signal board which is constituted by a printed circuit board or a multi-layered printed circuit board, and extends over spaces between rows of semiconductor elements, thereby forming a path for sending a control signal.

Abstract: To eliminate variations in measurement of the chip characteristics an MMIC chip has a pad main portion having the same width as a main line at an end of the main line The main line is located on a GaAs substrate. Pad auxiliary islands are adjacent to the pad main portion on one or both sides. A grounding wiring layer is on at least one side of the pad main portion with the pad auxiliary island interposed in between. The pad main portion and the pad auxiliary portions secure a sufficient bonding area. The electrical characteristics are measured by bringing probes into contact with the pad main portion and the grounding wiring layer(s). The electrical characteristics of the MMIC chip can be evaluated without an increase in bonding pad capacitance.

Abstract: Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the conductive layer patterns, the semiconductor device including: conductive layer patterns formed on a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and the conductive layer patterns; well regions formed in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and gate and source/drain electrodes formed on the well regions, and a method for fabricating the semiconductor device including the steps of: forming conductive layer patterns on a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate including the conductive layer patterns; forming well regions in the semiconductor layer and the semiconductor subs

Abstract: The integrated electronic device comprises a protection structure of metal, extending vertically and laterally to and along a predominant part of the periphery of an electronic component integrated underneath the pad region. The protection structure comprises a substantially annular region formed from a second metal layer and absorbing the stresses exerted on the pad during wire bonding. The annular region may be floating or form part of the path connecting the pad to the electronic component.

Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.

Abstract: Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond to two adjacent edges of the lower die. The lower die has bond pads within the keep out areas. An upper die is stacked on the top surface of the lower die such that the bond pads within the keep out areas of the lower die are exposed to accept wire bonds. The configuration of the keep out areas next to adjacent edges of the lower die thus provides flexibility in the design of stacked chip packages because the size of the upper die is not limited by the bond pad configuration of the lower die.

Abstract: An electrical connection structure for electrically connecting a semiconductor chip to an external circuit device is provided. The connection structure comprises a ground conductive plate connected to ground power of the semiconductor chip; an insulating layer formed on the ground conductive plate; a signal pattern layer formed on the insulating layer and having signal patterns in electrical communication with the semiconductor chip. The ground conductive plate includes a projected blank pattern that is the complement of the signal pattern layer. With the present invention, self inductance and mutual inductance of the connection structure is reduced. Further, because of the blank patterns formed in the proximal ground plate, the capacitance is also reduced.

Abstract: An improved vehicle restraint system includes a seat belt tension sensor and an occupant detection control module for characterizing the occupant of a vehicle seat to determine whether to allow or suppress deployment of supplemental inflatable restraints for the occupant. The belt tension sensor includes on-board signal processing circuitry and is coupled to occupant detection control module via a two wire interface that both powers the sensor and its signal processing circuitry and supports communication of belt tension data to the occupant detection control module. The sensor produces an electrical signal responsive to seat belt tension, and the processing circuitry generates one of a specified number of messages pertaining to the range of the measured tension, and then modulates the current through the two wire interface to communicate the generated message to the occupant detection control module.

Abstract: A power failure transfer switching system for monitoring incoming line voltages and switching to auxiliary sources as required. The power failure transfer switching system includes a voltage monitoring assembly designed for monitoring the levels of an incoming ac supply circuit, a power generating assembly for supplying an auxiliary source of ac power when the voltage monitoring assembly detects an inadequacy in supply from the incoming ac supply circuit, and a control assembly operationally coupled to the voltage monitoring assembly and to the power generating assembly for operating the power generating assembly when the voltage monitoring assembly detects an inadequacy in supply.

Abstract: A charging control circuit for severe battery conditions and an uninterruptible power supply (UPS) system including same are presented. The charging control circuit utilizes both hardware and microprocessor control to allow the UPS to start with depleted or no batteries installed. Initially, the hardware control loops regulate DC bus voltage generation to charge the batteries to a safe level to allow the UPS housekeeping circuitry to wake up and assume control of the UPS operation. Once the microprocessor has awoken, it assumes control of the DC bus and charging of the batteries. If no batteries are installed, the hardware control loop utilizes a fast responding voltage mode control to regulate the DC bus, while a microprocessor-based current mode control is used when batteries are installed. Hardware over voltage control and microprocessor shut off control is also provided.

Abstract: The process provides constant electric power from a combination of a wind energy generator and a firm secondary generator. The wind energy generator and the secondary generator supply electricity directly to a utility transmission system. The secondary generator must be able to provide power on demand that will meet a utility's needs. The secondary generator is preferably a natural gas turbine, but may be a hydrogen fuel cell, a diesel internal combustion engine, or any other similar technology.

Abstract: An AC interconnection apparatus has an input terminal for a commercial power system, a connection terminal to a solar cell, an output terminal connected to a load, an inverter for converting the output voltage of the solar cell into an AC voltage, and a current detector arranged on the load side of an AC connection point for connecting the AC output from the inverter and the commercial power. When a power value calculated on the basis of a current detection value by the current detector and the voltage of the commercial power system is less than the output power of the inverter, the output of the inverter is suppressed, thereby suppressing reverse power flow to the commercial power system. When the current value detected by the current detector exceeds a predetermined value, power supply to the load is stopped using a breaker.

Abstract: An integral harmonic mitigation device and distribution panel(s) are configured as a power center unit for non-linear electrical loads. The power center unit performs harmonic mitigation to reduce the presence of upstream electrical disturbances in a source current. The power center unit is located close to the non-linear loads to isolate the loads and facilitate load balancing to improve harmonic mitigation. The power center unit is also ideally suited for mobile or semi-mobile applications.

Abstract: Disclosed is a multi-phase flat-type PM stepping motor comprising a first motor unit having a first stator unit and a first rotor unit, and a second motor unit having a second stator unit and a second rotor unit. The first stator unit has a plurality of air-core coils that are radially arranged on a first isolating magnetic disc. The first rotor unit has a plurality of permanent magnets that are alternatively magnetized in N-pole and S-pole and radially arranged on a second magnetic disc with a predetermined air gap with respect to the coil surface of the first stator unit. In the same manner, the second stator unit has a plurality of air-core coils that are radially arranged on a third isolating magnetic disc, and the second rotor unit has a plurality of permanent magnets arranged on a fourth magnetic disc. The first and second motor units are coaxial and symmetric with each other about a non-magnetic disc arranged therebetween.

Abstract: A bicycle dynamo hub axle assembly that includes an axle having opposite ends, a smaller diameter portion located at one of said opposite ends, and a larger diameter portion, an electricity generating device disposed on the larger diameter portion of the axle, a bearing race disposed on the larger diameter portion, an electric wire extending from the electricity generating device, through one of the grooves and through the bearing race, a spacer disposed on the larger diameter portion, and a lock nut disposed on the smaller diameter portion for securing the bearing race and the spacer in position. The smaller diameter portion has a smaller diameter than the larger diameter portion and the larger diameter portion has at least two grooves defined therein. The larger diameter portion also includes a stepped portion extending radially outwardly therefrom. The spacer has an opening defined therethrough, and has at least one tongue extending inwardly into the opening.