Abstract: Circuits, apparatuses, electrochemical device charging methods, and lithium-mixed metal electrode cell charging methods are provided. According to one aspect, a circuit includes charging circuitry adapted to apply electrical energy to an electrochemical device to charge the electrochemical device, and the electrochemical device being configured to assume an open-circuit condition in a substantially charged state; shunting circuitry electrically coupled with the charging circuitry and configured to shunt the electrical energy around the electrochemical device responsive to the electrochemical device reaching the substantially charged state; and indication circuitry configured to output a signal responsive to the shunting of the electrical energy to indicate a charge status of the electrochemical device.

Abstract: Power supply apparatuses and methods of supplying electrical energy are provided. According to one aspect, a power supply apparatus includes an electrochemical device configured to store electrical energy, a first interface coupled with the electrochemical device and adapted to couple with a supply configured to provide electrical energy and a first load configured to receive electrical energy, and charge circuitry coupled intermediate the first interface and the electrochemical device, wherein the charge circuitry is configured to monitor a quantity of electrical energy supplied from the supply to the first load and to control a supply of electrical energy to the electrochemical device responsive to the monitoring and to charge the electrochemical device.

Abstract: A battery pack includes a simple circuitry that improves the life cycle characteristic of the battery. The battery pack includes a plurality of cells connected in series. One of the cells is a lower rated capacity cell having a smaller capacity than the other cells. The lower rated capacity cell is disposed in a first tier of the plurality of cells from a negative terminal of the battery. Temperature and voltage of the lower rated capacity cell are detected to determine whether the lower rated capacity cell has reached the fully charged condition. When the fully charged condition is detected, charging of the battery is stopped. Similarly, based on the temperature and voltage detected, whether the lower rated capacity cell will soon be over-discharged is determined. If so, the use of the battery is stopped.

Abstract: A device (100, 200) is described for generating an electric voltage by which a body of a capacitive and/or inductive sensor capable of vibration, such as a capacitive micromechanical rotational rate sensor in particular, is induced to vibrate.

Abstract: The invention relates to a DC/DC converter or power supply with a switched-mode regulator (2), said regulator (2) being provided or associated to a feedback comparator (1) of a feedback voltage (Vact) for improving the stability of the output signal. It is further provided or associated to a means (3, D) for adding an offset voltage (Voff) to the feedback voltage (Vact) during at least one phase (&phgr;1) of the switched-mode regulator (2) or at least a portion thereof.

Abstract: Disclosed is current driver circuit comprising a bandgap reference circuit for generating a fixed current and a current proportional to absolute temperature (PTAT), a temperature compensator for combining the fixed and PTAT currents and forming first and second temperature compensated currents, a current control circuit for modifying said first and second temperature compensated currents in response to signals representing the characteristics of a load device and a driver circuit for amplifying and supplying a selected one of said first and second temperature compensated currents to said load device. Also disclosed is a method of supplying a precisely controlled current by generating a constant current and a current proportional to absolute temperature (PTAT), combining these two currents and providing temperature compensated currents, modifying the temperature compensated currents with a programmed reference signal and supplying a precisely controlled current to a load device.

Abstract: A lightning detection and data acquisition system. A plurality of remote programmable sensor is utilized to detect cloud to ground and IC lightning strikes. Analog representations of the lightning strikes are converted to digital signals. The digital signals are classified according to user changeable criteria. The classified digital signals are compressed and optionally decimated. The compressed information is transmitted to a central location where it is decompressed and used to correlate the location, magnitude, and travel path of the detected lightning strikes.

Abstract: A lightning detection and data acquisition system. A plurality of remote programmable sensor is utilized to detect cloud to ground and IC lightning strikes. Analog representations of the lightning strikes are converted to digital signals. The digital signals are classified according to user changeable criteria. The classified digital signals are compressed and optionally decimated. The compressed information is transmitted to a central location where it is decompressed and used to correlate the location, magnitude, and travel path of the detected lightning strikes.

Abstract: A measuring device (1), for measuring the spectrum of a measured signal in several neighbouring channels (15−9-159) of a working channel (14), comprises a selective filter (9) which damps the working channel (14) more strongly than the neighbouring channels (15−9-159). Furthermore an analogue/digital converter (5) is provided which detects the filtered measured signal from all the channels to be measured (15−9-159, 14) in a parallel and broadband manner and converts the above to a digital signal. An equaliser (11) in series with the analogue/digital converter (5), equalises the digital signal with a frequency response which is the reciprocal of the frequency response of the selective filter (9).

Abstract: A sensor readout circuit which provides a frequency signal output including a phase detector circuit responsive to an output signal from a sensor and an input signal to the sensor and configured to detect the phase difference between the input signal and the output signal, and a drive circuit responsive to the phase detector circuit and configured to maintain a fixed phase difference between the input signal and the output signal.

Abstract: Method for determining the position or the orientation of an object using a magnetic field and corresponding device.

Abstract: The invention relates to a device (10) for contactless measurement of a displacement path, especially for the detection of position and movement, comprising a sensor electronics system for the provision of an alternating current and the evaluation of alterations therein, in addition to an inductive sensor (13) comprising at least one flat coil (15), whereby each coil (15) is configured with a helicoidal conductor (22) disposed on a plane and one of the two flat surfaces (19) thereof forms a measuring surface (14) which variously covers a measuring object (11), arranged at a distance, according to the movement thereof parallel to the measuring surface (14).

Abstract: The invention includes methods determining the presence of base line popping noise for a read head inside an assembled disk drive, as well as, determining read bias conditions for operating the read head free of base line popping noise. The invention further includes performance evaluation of the read head for read bias conditions free of base line popping noise. The invention also includes repairing the read head using DC write current and read bias current within the assembled disk drive.

Abstract: The invention relates to a device for measuring magnetic field(s). This device comprises at least one measurement acquisition pathway (221, 222, 223; 231, 232, 233) comprising a measurement current generator (24), a coil (25), a measurement resistor (26), at least one amplifier (27) and at least one antialiasing filter, delivering a measurement voltage.

Abstract: A magnetic field sensor relies on variations in permeability of magnetic material to detect an external field. An exemplary magnetic field sensor includes a magnetic material and two or more conductors, at least one of which is connected to an electrical energy source. Current flowing through at least one of the conductors establishes a magnetic field in the magnetic material at a magnitude at which there is a generally linear relationship between the magnetic field and the permeability of the material. An external field to be sensed influences the permeability of the material. Sensing variations in the permeability of the magnetic material allows the external magnetic field to be sensed.

Abstract: An integrated magnetic field sensing device includes at least two magnetoresistive elements which are biased in a first direction by an integral conductor and are sensitive to magnetic field components in a direction perpendicular to the first direction. The sensitivity of the device to a magnetic field is adjustable and is related to the level of the bias current. In a current measuring application, two of the magnetic field sensing devices are mounted on opposite sides of and perpendicular to a conductor carrying a current to be measured. In a portable current measuring apparatus, two of the magnetic field sensors are mounted in a housing that assists in locating the magnetic field sensors relative to the conductor carrying the current to be measured.

Abstract: A structure and method for forming a magnetic-field sensor device comprises depositing a first electrode onto a substrate. Then, an electrically insulating layer is deposited on the first electrode. Next, a portion of the insulating layer is removed to expose a region of the first electrode, thereby creating an empty space. After this, at least one layer of chemically-synthesized nanoparticles is deposited on the insulating layer and within the empty space. Next, a second electrode is deposited on both the layer of nanoparticles and the insulating layer. Alternatively, multiple layers of nanoparticles may be deposited, or only a single nanoparticle may be deposited. The substrate is either conducting or non-conducting, and the first and second electrodes are electrically conducting and may be magnetic or non-magnetic. Additionally, a metallic layer of magnetic material may be first deposited on the substrate.

Abstract: A loop-gap resonator for providing an excitation pulse in a down hole nuclear magnetic resonating (NMR) tool for determining a parameter of interest in a formation adjacent a borehole. The loop-gap resonator is constructed having one or more capacitive gaps formed in a nonmagnetic conductive loop. The loop-gap resonator may be deployed down a bore in a measurement while drilling (MWD) configuration or in a wire line configuration. The MWD configuration may utilize a non-rotating sleeve rotationally associated with the drill string.

Abstract: An NMR resonator with RF resonator for receiving RF signals at a resonance frequency from a measuring sample in a volume under investigation of an NMR apparatus with a means for producing a homogeneous magnetic field B0 in the direction of a z axis, wherein normally conducting conductor structures of the RF resonator which act inductively and partially also capacitively are disposed between z=−|z1| and z=+|z2| on a surface which is translation-invariant (=z-invariant) in the z direction at a radial (x, y) separation from the measuring sample, is characterized in that a compensation arrangement is additionally provided on the z-invariant surface, which extends to values of at least z<−|z1|−0.5|r| and z>+|z2|+0.

Abstract: This method of checking at least one operating parameter of an energizer supplying an electric fence with high-voltage shock pulses consists, on the one hand, in producing a measurement signal having a value representing the operating parameter to be checked and controlling the production of the shock pulses as a function of the measurement signal in such a way that a time interval between the shock pulses is a function of the value of the measurement signal, and, on the other hand, in performing the following steps in any zone along said electric fence, remotely from the energizer: picking up the shock pulses; evaluating the time interval between the picked up pulses; and operating an indicator so as to provide an indication about the operating parameters, as a function of the evaluated time interval.

Abstract: Methods and apparatus to detect terminal open circuits and short circuits to ground in inductive head write drivers are presented. A exemplary method is provided for detecting a short-circuit condition at at least one of a pair of write head terminals of a write driver, the write driver producing a write current that, when passed through a inductive head assembly coupled to the pair of write head terminals, polarizes the inductive head according to a direction of the write current. The method includes the step of generating a first current that is proportional to at least a portion of the write current that flows in a first direction into a first write head terminal of the write driver. A second current is generated that is proportional to at least a portion of the write current that flows in a second direction, opposite the first direction, into a second write head terminal of the write driver.

Abstract: A partial discharge detection test link (20) and system detect partial discharge of a power cable at a power cable accessory (6). The power cable accessory includes a first accessory component and a second accessory component connected to each other. The partial discharge detection test link (20) is a permanent or temporary substitute for a conventional service link, connects directly across the power cable accessory and includes a conductor member (22) and a partial discharge sensor (24). The conductor member (22) has an electrically conductive element (26) and an insulation (28) surrounding and extending along the electrically conductive element. The electrically conductive element (26) is electrically connected directly between the first and second accessory components.

Abstract: A tester for verifying the integrity of insulation in a branch circuit of a power distribution system. Two test circuits are included; the first providing an insulation test; and a second, a shared/grounded neutral test. In the insulation test, a 500-volt ac output limited to 5 milliamps is selectively applied to the pairs of wires of the branch circuit. If an output current of greater than 3 milliamps is recorded, an insulation failure is noted and the operator proceeds to the second test which applies a pulsed 3 volt, 1 ampere current-limited voltage across the suspected leads. One of the suspected leads is monitored with a portable ammeter to detect any pulse current.

Abstract: Arcing faults in an electric power system are detected by sensors powered by the light generated by the arcing even in the presence of background light. The sensors have one or more first photovoltaic cells energized by light passed through a first filter having a passband which includes a characteristic wavelength of the arcing material to generate a sensed light electrical signal. One or more second photovoltaic cells are energized by light filtered by a second filter having a passband not including the characteristic wavelength to generate a background light electrical signal. These two electrical signals are applied in opposition to an LED which is turned on when arcing is present. The light signal from the LED is transmitted through an optic fiber to a photoelectric circuit, which generates an arcing signal when energized. The LED may be biased toward the on condition by unfiltered additional photovoltaic cells.

Abstract: An electricity meter performs a self-calibration operation. According to an exemplary embodiment, the meter includes a measurement circuit for generating power information representative of measured power. A controller is operably coupled to the measurement circuit and includes an input for receiving reference standard information. The controller compares the power information generated by the measurement circuit to the reference standard information and generates a compensation signal in dependence upon the comparison. The compensation signal is used to calibrate the measurement circuit. Preferably, the meter is capable of being electrically connected to, and calibrated concurrently with at least one other meter.

Abstract: A device for measuring the probe impedance of a linear lambda probe of an internal combustion engine which is caused by an AC current measurement signal which is fed into the lambda probe, comprises a voltage amplifier for amplifying an AC voltage which drops across the probe impedance, and a rectifier for rectifying the amplified AC voltage, wherein the rectifier is a synchronous demodulator, by which in each case the upper and lower amplitude of the AC voltage signal is sampled with its frequency, filtered and stored, and by which the difference of the stored signals is amplified with a gain factor and made available as output signal at its output for controlling the temperature of the lambda probe.

Abstract: The present invention discloses a circuit used to couple an input signal to an amplifier circuit. The circuit may contain a diode bridge coupled to an adjustable bias circuit. The current through the bias circuit can be adjusted such that the resistance of the diode bridge can be dynamically configured to change the sensitivity of the diode bridge. The bias circuit may be configured to produce a variable amount of current based on a voltage signal. In another aspect of the present invention, the output from the diode bridge is coupled to an amplifier via a clamp circuit designed to prevent the amplifier from overloading.

Abstract: A circuit tester comprises a reference voltage source, an indicator with first and second response states, an indicator driver connected to the reference voltage source, an oscillator and a probe. The oscillator's output and the probe are both connected to the indicator driver's input. The indicator driver drives the indicator in the first response state when the voltage at the input is lower than the reference voltage, and in the second response state when the voltage at the input is higher than the reference voltage. The oscillator causes the indicator driver to cycle the indicator between the first and second response states when the probe is not connected to a circuit under test.

Abstract: A contact probe for a testing head is described. The probe has at least a pointed rod-shaped body having a crook-shaped section capable to contact mechanically and electrically at least one contact pad of an electronic device to be tested and defined form an elbow point on the rod-shaped body. The rod-shaped body comprises at least one additional elbow point spaced form the elbow point and defining a concave angle in the rod-shaped body.

Abstract: A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device.

Abstract: Method for burn-in testing of a wafer having a plurality of dies where the reliability of the fail rate is matched to meet a predetermined criteria. This is accomplished by selecting a subset of dies to be tested and tests are used to weed out the highest number of failures.

Abstract: An input voltage detecting circuit for detecting an input voltage is provided inside a PFM control charge pump circuit, and potential differences between potentials appearing at gate terminals and potentials appearing at source terminals are reduced by gate voltage controlling circuits for in response to a signal from the input voltage detecting circuit, suppressing gate voltages of switch transistors of a charge pump to suppress a rush current value to thereby reduce a current to prevent generation of a noise.

Abstract: The present invention provides a memory device with a N-MOS self-termination scheme which enables or disables the device to eliminate ringing and line reflections in a memory device such as a DDR SDRAM. The self-termination is achieved by using a weak N-MOS transistor. The N-MOS transistors are within the device and has an impedance of two to eight times of the characteristic impedance of a communication path in a memory device such as DRAM or SRDAM. The communication path is generally a read/write or command/address bus. The self-termination scheme terminates line reflections occurring in a device receiving data during non productive time duration of system clock. The present invention provides a method by which random access memories perform with faster settling time for data inputs and a high system performance.

Abstract: A serial poll request node and circuit are provided. The node includes a data token input and output, first and second acknowledge inputs, and an arbitrating switch. An acknowledge circuit is configured to receive as an input the first and second acknowledge inputs and at least one output of the arbitrating switch, and to generate an enable signal in response to at least the absence of a pending request signal and both the first and second acknowledge inputs simultaneously receiving acknowledge signals.

Abstract: A large scale integrated (LSI) or a very large scale integrated (VLSI) logic circuit. such as a fully progammable gate array (FPGA), comprises a plurality of polysilicon thin film transistors TFTs. The circuit, which may include a delay circuit, is asynchronous and does not comprise a clock. Thus, operations to be performed by the TFTs need not be performed within a single clock period—rather the operation of each stage of TFTs in the circuit is dependent on receiving a signal either from an input to the circuit or from a preceding stage in the circuit. Problems with variations in the threshold voltage between the TFTs are therefore avoided.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its input/output (I/O) node, while operating with a 3 volt power supply and is resistant to CMOS latchup. The 5 volt compatibility is achieved by inserting an additional p-channel transistor in series with the existing p-channel transistor and circuitry to control the additional p-channel transistor. The control circuit is comprised of 2 transistors. The CMOS latchup resistance is provided by a N-well bias generator that changes the N-well bias to be equal to the higher of the 2 voltages, VDD or the voltage present at the I/O pad. The N-well bias generator is comprised of 3 transistors.

Abstract: A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected(tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.

Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Abstract: An apparatus for effecting high speed switching of a communication signal between a first component and a second component includes: (a) a switching circuit configured for receiving the signal from the first component that includes a plurality of switch elements responding to the signal to produce an interim signal that is substantially a model of the signal; (b) a follower circuit having an input locus coupled with the switching circuit for receiving the interim signal; the follower circuit has an output locus configured for presenting an output signal that is substantially duplicating the interim signal; and (c) a control circuit coupling the follower circuit with the switching circuit and receives a feedback signal from the follower circuit representative of the output signal; the control circuit responds to the feedback signal to effect operation of the switching circuit to control at least one first parameter relating to the interim signal.

Abstract: The present invention refers to a charge pump system supplied by a direct voltage signal and supplying on the output terminal a voltage signal with a higher value of said direct voltage signal.

Abstract: Disclosed are a delay-locked loop circuit and a semiconductor integrated circuit device of reduced power consumption, the delay-locked loop circuit having a tCK/2 generating DLL and an input/output-compensating DLL. The tCK/2 generating DLL includes first and second delay lines for delaying a frequency-divided clock input thereto from a frequency dividing circuit; a first phase detector for detecting the phase difference between the frequency-divided clock and the output of the second delay line; and a counter for outputting a signal that changes over the output taps of the first and second delay lines depending upon an output from the first phase detector.

Abstract: High-resolution serial data can be obtained by using a costly, large-scale high-performance IC. A high resolution can be achieved without using any high-performance PLL or the like by a low-cost, simple system capable of generating a fundamental waveform on the basis of serial data synchronous with the leading and the trailing edges of a clock signal, of generating a delayed clock signals of a plurality of times by a delay device, and of superposing the fundamental waveform and the delayed clock signals.

Abstract: A duty cycle regulator derives from an input clock of arbitrary duty cycle an output clock having an adjustable duty cycle of similar frequency. The invention comprises a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set giving high signal to the delay unit, which after said delay interval resets the bistable circuit to give a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit comprises a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further comprises a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.

Abstract: A transmitter pre-driver utilizing discrete-time charge sharing between multiple capacitors to create intermediate voltages. The intermediate voltages are fed into an output driver to produce Class AB and Class A output current flow.

Abstract: Disclosed is an integrated circuit device in which a 90-degree phase shifter is implemented. The 90-degree phase shifter includes four input capacitors all having equal capacitance and four output capacitors all having equal capacitance. The input capacitors and the output capacitors are alternately arranged in a loop-shape array in plan view. Eight resistors of the 90-degree phase shifter are arranged inside the annular shape in which the capacitors are arranged.

Abstract: The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital data input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).