Abstract: The present invention is directed to methods for generating high titer, contaminant free, recombinant AAV vectors, methods and genetic constructs for producing recombinant AAV vectors conveniently and in large quantities, methods for the delivery of all essential viral proteins required in trans for high yields of recombinant AAV, recombinant AAV vectors for use in gene therapy, novel packaging cell lines which obviate the need for cotransfection of vector and helper plasmids, helper plasmids and vector plasmid backbone constructs, a reporter assay for determining AAV vector yield. Further provided are recombinant AAV vectors in a pharmaceutically acceptable carrier, methods of delivering a transgene of interest to a cell, compositions and methods for delivering a DNA sequence encoding a desired polypeptide to a cell, and transgenic non-human mammals that express a human chromosome 19 AAV integration locus.

Abstract: The present invention generally relates to nanocapsules and methods of preparing these nanocapsules. The present invention includes a method of forming a surfactant micelle and dispersing the surfactant micelle into an aqueous composition having a hydrophilic polymer to form a stabilized dispersion of surfactant micelles. The method further includes mechanically forming droplets of the stabilized dispersion of surfactant micelles, precipitating the hydrophilic polymer to form precipitated nanocapsules, incubating the nanocapsules to reduce a diameter of the nanocapsules, and filtering or centrifuging the nanocapsules.

Abstract: The present invention provides methods of site-specifically integrating a polynucleotide sequence of interest in a genome of a eucaryotic cell, as well as, enzymes, polypeptides, and a variety of vector constructs useful therefore. In the method, a targeting construct comprises, for example, (i) a first recombination site and a polynucleotide sequence of interest, and (ii) a site-specific recombinase, which are introduced into the cell. The genome of the cell comprises a second recombination site. Recombination between the first and second recombination sites is facilitated by the site-specific recombinase. The invention describes compositions, vectors, and methods of use thereof, for the generation of transgenic cells, tissues, plants, and animals. The compositions, vectors, and methods of the present invention are also useful in gene therapy techniques.

Abstract: The present invention relates to polynucleotide molecules comprising nucleotide sequences encoding an aveC gene product, which polynucleotide molecules can be used to alter the ratio or amount of class 2:1 avermectins produced in fermentation cultures of S. avermitilis. The present invention further relates to vectors, host cells, and mutant strains of S. avermitilis in which the aveC gene has been inactivated, or mutated so as to change the ratio or amount of class 2:1 avermectins produced.

Abstract: A method for testing gas detection instruments includes providing at least two reagents, immobilizing at least one of the reagents into a matrix material, heating the matrix material until the matrix permits movement of the reagent and generating a gas responsive to chemical reaction between the reagents. The gas is introduced into the sensor portion of the gas detection instrument to test the same. The reagents may each be immobilized on the matrix material with the heating serving to soften or melt the matrix material to permit chemical interaction. In a preferred embodiment, the heating is effected at about 90 to 150° C. The method may be employed to generate carbon monoxide or other gases of interest. Corresponding apparatus is provided. The apparatus may be structured to be inserted into or receive the gas detection instrument or have its output in communication therewith.

Abstract: Multi-analyte reference solutions having a stable partial pressure of oxygen (pO2) in zero headspace packaging and methods for preparing such solutions are disclosed. The solutions have long shelf and use lives when stored at room temperature and are packaged in laminated foil containers having low or no oxygen reactivity. Access devices are also disclosed.

Abstract: A novel reagent system for use with automated and semi-automated hematology analyzers including an essentially isotonic blood diluting reagent, a blood cell lysing and hemoglobin conversion reagent, and a second lysing reagent for differentiating white blood cells into classes by size and functional characteristics. The diluent reagent enhances properties for counting and sizing blood specimens, while stabilizing cellular volume and cellular integrity for many hours. The blood cell lysing reagent removes red blood cells and enables subsequent enumeration of white blood cells and simultaneous determination of hemoglobin without use of the toxic cyanide anion. The third lysing reagent and a companion quenching differentiates blood cells into classes by size and functional characteristics, based on d.c. impedance volume, conductivity/opacity and light scatter measurements. The companion quenching reagent adjusts pH and conductivity of the final measurement solution to match the analyzer system requirements.

Abstract: An air-barrier agent for an aqueous reagent or an aqueous specimen having as an effective component a mixture of a chain hydrocarbon and a silicone oil immiscible with the aqueous reagent as well methods of using and making the same.

Abstract: A coagulation test for determining the activated clotting time (ACT) of blood in the presence of heparin that produces test results that are substantially insensitive to the drug aprotinin. The activator is formulated to be a combination of celite and bentonite. The ACT results obtained with this formulation are similar to celite ACT tests on heparinized blood while simultaneously being unaffected by aprotinin. Additionally, a method for quantifying the aprotinin effect of different ACT formulations is disclosed.

Abstract: Method and apparatus to determine the speed of sedimentation of blood and other parameters connected thereto, said method being carried out by detecting the development over time of the optical density, or absorbance, of a sample of blood, said sample being sent in the form of a flow inside a capillary container (12), said detection being made in correspondence with a point of said capillary container (12) and the relative data acquired being processed to obtain said speed of sedimentation and said connected parameters, said method providing to instantly interrupt the flow of the blood sample flowing inside said capillary container (12), in order to determine a thickening of the red cells in said blood sample and their consequent sedimentation, said detection being made substantially simultaneously with said instant interruption.

Abstract: A method of determining the proportion of short-chain branching in an olefin copolymer process stream is disclosed. The short-chain branching may also be determined as a function of molecular weight in a sample having a range of molecular weights. In the method, at least two olefin copolymer training samples are provided. The respective samples have different, known proportions of short-chain branching. The infrared (e.g. FT-IR) absorbance spectra of the training samples in a wavenumber range are obtained. Calibration information is determined from the training samples by chemometrically correlating the differences in the infrared absorbance spectra of the training samples to the differences in the degree of short-chain branching in the training samples. This step generates calibration information that allows the degree of short-chain branching in a sample to be determined once its infrared absorbance spectrum is obtained.

Abstract: A device and method for filtering a biologically derived sample and for mixing the sample with a reagent, comprising a fluid container defining a reservoir compartment and including a container outlet, a filter and a fluid flow-through matrix disposed in a flow path between the reservoir compartment and the container outlet. Water-soluble, dried reagent is retained on the matrix. Means is provided for urging sample in an aqueous liquid in the reservoir compartment through the filter and matrix and out the container outlet. Pressure is applied to the sample in an aqueous liquid in the reservoir compartment to cause the sample to flow in liquid through the filter and matrix and out of the container for analysis.

Abstract: An immunochemical method for the determination of antibodies which are specific for an antigen and are of one of the immunoglobulin classes: A, M, D or E in a fluid, with this fluid being contacted with a solid phase to which the antibodies against this immunoglobulin class, or a fragment of an antibody of this type, are bound, which results in the immunoglobulin of this class being bound to this solid phase, and this solid phase being contacted with the antigen, which carries a labeling means where appropriate, and with a labeled antibody or a labeled fragment of an antibody against the antigen if the antigen is unlabeled and determination, from the amount of labeling means which is bound to the solid phase, of the amount of these antibodies which are specific for an antigen and are one of the immunoglobulin classes, which comprises the solid phase being simultaneously in contact with the fluid containing the antibody which is to be determined and with the antigen, which is labeled where appropriate, there b

Abstract: Methods for forming capacitors of semiconductor devices, and more specifically, to a method for forming a capacitor having a stacked structure of metal layer-insulating film-metal layer and having its storage electrode formed of ruthenium (hereinafter, referred to as ‘Ru’) and dielectric layer formed of tantalum oxide (Ta2O5) film, which provides improved formation of dense Ru film using a CVD method at high temperature, thereby improving electrical characteristics of the capacitor.

Abstract: There is disclosed an improved method of manufacturing of an optical device (40), particularly semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and optical detectors. The invention provides a method of manufacturing optical device (40), a device body portion (15) from which the device (40) is to be made including a Quantum Well (QW) structure (30), the method including the step of: processing the device body portion (15) so as to create extended defects at least in a portion (53) of the device portion (5). Each extended defect is a structural defect comprising a plurality of adjacent “point” defects.

Abstract: According to the present invention, an apparatus for determining various processes of wafer fabrication suitable for a plurality of various processes of wafer fabrication, having: a plurality of wafer cassettes, each having a distinct transparency, used in the various processes of wafer fabrication; a sensor-set, used to detect the distinct transparency of each of the wafer cassettes, and output a signal corresponding to the distinct transparency; and an amplifier, connected to the sensor-set to receive the signal, thus reading the distinct transparency, so as to determine the type of the wafer cassettes. Furthermore, a method for determining various processes of wafer fabrication includes the steps of: providing a plurality of wafer cassettes, each having a distinct transparency, used in the various processes of wafer fabrication; reading the distinct transparency of each of the wafer cassettes; and determining the type of the wafer cassettes according to the distinct transparency.

Abstract: A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.

Abstract: The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from a die to a predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies.

Abstract: A method for evaluating the concentration of impurities in gases used in depositing an epitaxial layer on a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels in an epitaxial reactor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A process for manufacturing semiconductors uses an enclosure (22) having an interior surface-that is intentionally-roughened by spraying quartz (44) onto the interior surface. The sprayed quartz (44) creates additional surface area for the purpose of trapping or capturing etched material in the enclosure during the process. The roughness of the interior surface is not significantly reduced during the semiconductor processing so that only chemical cleaning is required to maintain the interior surface for long-term use.

Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.

Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included and surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard also insulates the conductive tip from the semiconductor wafer.

Abstract: The present invention is directed to an automated method of controlling critical dimensions of features by controlling the stepper exposure dose, and a system for accomplishing same. In one embodiment, the method comprises measuring a critical dimension (FICD) of a plurality of features formed in a process layer, and providing the measured critical dimensions of the features to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer. In another embodiment, the method comprises measuring a critical dimension (DICD) of a plurality of features formed in a patterned layer of photoresist, providing the measured critical dimensions of the features in the patterned layer of photoresist to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer.

Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.

Abstract: A direct-wafer-bonded, double heterojunction, light emitting semiconductor device includes an ordered array of quantum dots made of one or more indirect band gap materials selected from a group consisting of Si, Ge, SiGe, SiGeC, 3C—SiC, and hexagonal SiC, wherein the quantum dots are sandwiched between an n-type semiconductor cladding layer selected from a group consisting of SiC, 3C—SiC, 4H—SiC, 6H—SiC and diamond, and a p-type semiconductor cladding layer selected from a group consisting of SiC, 3C—SiC, 4H—SiC, 6H—SiC and diamond. A Ni contact is provided for the n-type cladding layer. An Al, a Ti or an Al/Ti alloy contact is provided for the p-type cladding layer. The quantum dots have a thickness that is no greater than about 250 Angstroms, a width that is no greater than about 200 Angstroms, and a center-to-center spacing that is in the range of from about 10 Angstroms to about 1000 Angstroms.

Abstract: An organic light emitting device (and a method for producing the device) includes a multilayered structure with a substrate layer providing a first electrode layer, a second electrode layer and at least one layer of light emitting organic material between the first and second electrode layers. The second electrode layer includes at least two separate layers, a layer of a semi-transparent metal electrode and a layer of light transparent lateral conductor, is deposited onto the layer of light emitting organic material such as depositing the semi-transparent metal electrode layer onto the layer of light emitting organic material, depositing subsequently at least one protection layer thereupon and depositing the light transparent lateral conductor layer onto the protection layer.

Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.

Abstract: The present invention is a method of making an acceleration sensor chip. The sensor chip is prepared from a SOI wafer having a silicon substrate, a SiO2 layer and a silicon thin film. A dopant is ion implanted at a position corresponding to a semiconductor strain gauge on the silicon thin film to form a diffusion resistor, and for forming devices necessary for circuit construction on said silicon thin film. A protective film is provided on the entire surface of the wafer, and a plurality of through holes penetrating the silicon thin film are formed by patterning and etching to make a weight part and a beam part connected to a support frame part on the periphery. The SiO2 layer under the weight part and the beam part is removed by wet etching to form the through holes, while leaving the protective film in place. The protective film is removed and a resist coated over the entire surface of the wafer. A slit for dividing the chip is formed part way through the wafer by dicing.

Abstract: A microelectromechanical device (MEMD) defined within a substrate of a MEMS includes a mass element defining an area of interest. The device also includes a support beam supporting the mass element in spaced-apart relationship from the substrate. The support beam includes a first beam member defined by a first fixed end connected to the substrate, and a first free end connected to the mass element. The support beam further includes a second beam member defined by a second fixed end connected to the substrate, and a second free end connected to the mass element. The beam members are in spaced-apart relationship from one another. A first cross member connects the first beam member and the second beam member. Preferably, the support beam includes a plurality of cross members. Two such support beams can be used to support a mass element in a MEMD in a bridge configuration.

Abstract: A multiplicity of components form a photodiode array on a substrate. Each of the components consists of a transistor of the p-n-p type with the outermost p-doped layer being transformed into an optical filter by control of the anodic etching operation utilizing transistor characteristics of the respective transistor. The result can provide red, blue and green filters in a color camera.

Abstract: A new method to form color image sensor cells without damaging bonding pads in the manufacture of an integrated circuit device is achieved. The method comprises, first, forming cell electrodes and bonding pads on a semiconductor substrate. A passivation layer is formed overlying the cell electrodes but exposing the top surface of the bonding pads. The semiconductor substrate is then dipped in a hydrogen peroxide solution to thereby form a metal oxide layer overlying the bonding pads. A first transparent planarization layer is deposited overlying the passivation layer and the metal oxide layer. A color filter photoresist layer is deposited overlying the first transparent planarization layer. The color filter photoresist layer is patterned to form color filter elements to complete the color image sensor cells in the manufacture of the integrated circuit device. The presence of the metal oxide layer prevents damage to the bonding pads from an alkaline developer.

Abstract: A vertical color filter detector group according to the present invention is formed on a semiconductor substrate and comprises at least six layers of alternating p-type and n-typed doped regions. PN junctions between the layers operate as photodiodes with spectral sensitivities that depend on the absorption depth versus wavelength of light in the semiconductor. Alternate layers, preferably the n-type layers, are detector layers to collect photo-generated carriers, while the intervening layers, preferably p-type, are reference layers and are connected in common to a reference potential referred to as ground. Each detector group includes a blue-sensitive detector layer at an n-type layer at the surface of the semiconductor, a green-sensitive detector layer at an n-type layer deeper in the semiconductor, and a red-sensitive detector layer at the n-type layer deepest in the semiconductor.

Abstract: A method for fabricating a color image sensor for scanning and converting an optical image into electrical signals, includes the steps of: (a) forming a P-type semiconductor layer on a substrate; (b) forming field oxide layers on the P-type semiconductor layer to define regions for red, green and blue photodiodes; (c) providing an ion implantation mask having different mask patterns for the red, the green and the blue photodiodes; (d) implanting impurity ions into the P-type semiconductor layer through the use of said ion implantation mask to form N-type diffusion regions in the P-type semiconductor layer; and (e) applying a thermal process to the resulting structure to form different first, second and third depletion regions corresponding to the red, the green and the blue photodiodes.

Abstract: Method and apparatus for suction-holding a semiconductor pellet on a positioning stage of a bonding apparatus without causing the pellet to be misaligned after positioning thereof including a suction force control device. The suction force control device comprises a suction-switching electromagnetic valve, a suction force-adjusting electromagnetic valve, a vacuum source, a compressed air source and a throttle valve so that a semiconductor pellet is held on a positioning stage by a suction force that is weak enough that a positioning claw can move the semiconductor pellet for positioning; and upon completion of the positioning, the semiconductor pellet is held to the positioning stage by a suction force that is stronger than the weak suction force used for positioning.

Abstract: A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Abstract: A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed. The data pins of odd-numbered packages and even-numbered packages connect to the first bus and the second bus, respectively. The control signal pins connect to the third bus. Each package can optionally include dummy pins, where the dummy pins of the even-numbered packages and the odd-numbered packages respectively connect to the first and second buses so that each of the first, second and third buses connects to the same number of external pins. The pin assignment of the even-numbered packages can be different from the pin assignment of the odd-numbered packages to facilitate connections of the buses.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 &mgr;m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.

Abstract: To a provide a method of forming a layered film of a silicon nitride film and a silicon oxide film on a glass substrate in a short time without requiring a plurality of film deposition chambers. In a thin film transistor, a layered film including a silicon nitride oxide film (12) is formed between a semiconductor layer (13) and a substrate (11) using the same chamber. The silicon nitride oxide film has a continuously changing composition ration of nitrogen or oxygen. An electric characteristic of the TFT is thus improved.

Abstract: A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).

Abstract: In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via a plug. As a result, a contact hole for the substrate-biasing does not need to pass through the insulating layer, the silicon layer, and the interlayer insulating layer of the structure. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can thus be implanted to the surface of the substrate via the contact hole for substrate-biasing. The contact hole for substrate-biasing can be formed without causing an opening fault.

Abstract: A polycrystalline thin film of good quality is obtained by improving a crystallization process of a semiconductor thin film using laser light. After conducting a film forming step of forming a non-single crystal semiconductor thin film on a surface of a substrate, an annealing step is conducted by irradiating with laser light to convert the non-single crystal semiconductor thin film to a polycrystalline material. The annealing step is conducted by changing and adjusting the cross sectional shape of the laser light to a prescribed region. The semiconductor thin film is irradiated once or more with a pulse of laser light having an emission time width from upstand to downfall of 50 ns or more and having a constant cross sectional area, so as to convert the semiconductor thin film contained in an irradiated region corresponding to the cross sectional area to a polycrystalline material at a time. At this time, the energy intensity of laser light from upstand to downfall is controlled to apply a desired change.

Abstract: A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

Abstract: The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Abstract: A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer, and a control gate electrode of the nonvolatile memory cell. The first conductive layer is formed on the semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape. The first interlevel insulating film is formed on the semiconductor substrate so as to cover the field effect transistor, and has a first opening for exposing the surface of the first conductive layer. The second conductive layer is formed on the first conductive layer inside the first opening, and patterned into a predetermined shape. The control gate electrode of the nonvolatile memory cell is formed on the second conductive layer via an internal insulating film patterned into a predetermined shape.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stacked upper having a first gate electrode and a second gate electrode. The second gate electrode may have a broader width than the lower first gate electrode.

Abstract: A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).

Abstract: Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Also disclosed are methods of forming the capacitor structures and capacitors in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.

Abstract: A method of manufacturing a capacitor stack for a flat capacitor includes sequentially stacking a plurality of capacitor layers on top of each other such that each one of the plurality of capacitor layers is, in turn, a top layer of the capacitor stack, and continually applying a compression force between a bottom layer of the capacitor stack and the top layer of the capacitor stack until all of the plurality of capacitor layers have been placed.