Abstract: A capacitive measuring sensor which detects changes in an angle of electrode surfaces arranged at an acute angle to one another. The sensor outputs capacitive changes as a sensor signal. The sensor is preferably elongated and has at its end regions two fastening elements for connection to a body to be measured, two capacitor electrodes and two fastening elements. Changes in the angle of the capacitor electrodes is effected by displacement between the fastening points on the object to be measured.

Abstract: A circuit is tested for latch-up by scanning an optical beam across the surface, supplying power to the integrated circuit, monitoring the power of the power supply, and detecting latch-up in the integrated circuit by capturing an image of the integrated circuit when the power reaches a predetermined threshold. The captured image is compared with a baseline image to determine where latch-up occurs in the circuit.

Abstract: Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

Abstract: An improved vertical pin probing device is constructed with a housing with spaced upper and lower spacers of Invar®, each having a thin sheet of silicon nitride ceramic material held in a window in the spacer by adhesive. The sheets of silicon nitride have laser-drilled matching patterns of holes supporting probe pins and insulating the probe pins from the housing. The Invar spacers and silicon nitride ceramic sheets have coefficients of thermal expansion closely matching that of the silicon chip being probed, so that the probing device compensates for temperature variations over a large range of probing temperatures.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 8t≦r≦23t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 &mgr;m to 30 &mgr;m and larger than that of the second curved surface.

Abstract: A time it takes for a total leakage current (i.e., a total amount of B-mode stress induced leakage currents) flowing through respective MOS devices in a semiconductor integrated circuit to reach a predetermined reference level is estimated as an expected lifetime of the circuit.

Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Abstract: A wire used for transferring bidirectional signals is divided into a plurality of sub line segments. These sub line segments are classified into groups. Further, bidirectional buffers are provided between respective adjacent sub wires. The direction of transfer of a signal by each of the bidirectional buffers is controlled based on at least one of control signals used to control drivers for respectively outputting data signals to the sub line segments.

Abstract: A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.

Abstract: A circuit is provided with a programmable switching matrix incorporating at least one antifuse to selectively route signal paths. The selective routing of signal paths may be used for example, to internally reroute contact pin assignments on semiconductor chips to operate in a plurality of different socket layouts, or to selectively enable or disable features or controls of a circuit. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked therewith.

Abstract: While generating a correction pulse (E) based on a clock signal (Xck1) input into one input terminal (6), a frequency and a phase of a differentiated pulse train (Data_Dif) input into the other input terminal (5) are compared with a frequency and a phase of the clock signal input into the one input terminal, then a leading phase instructing pulse (U4) and an incomplete lagging phase instructing pulse (D4a) are generated based on this compared result, then false pulses contained in the incomplete lagging phase instructing pulse (d4a) are removed by using the correction pulse (E) when the differentiated pulse train (Data_Dif) input into the other input terminal is in the tooth missing state, and then the precise leading phase instructing pulse (U4) and the precise lagging phase instructing pulse (D4) are output from two output terminals (7, 8).

Abstract: An integrated circuit including a phase lock loop or delay lock loop (PLL/DLL) circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a charge pump (CP) circuit; at least one external feedforward output terminal; a loop filter (LF); a loop controlled signal source (LCSS); and a feedback circuit connected between a LCSS output and the PFD feedback input, the feedback circuit including, an external feedback input terminal; first frequency selection circuitry to produce a first programmable feedback signal; second frequency selection circuitry to produce a second feedback signal; and multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

Abstract: A method for controlling a local clock includes receiving a reference clock and generating a phase-shifted version of the reference clock. The two clocks are synchronized using a closed-loop method that produces a control signal. The control signal is smoothed during the closed-loop method and the smoothed signal is then used, instead of the control signal, in generating the phase-shifted clock.

Abstract: A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Abstract: A first and second circuits are connected in parallel between a first supply line supplying a first potential and a second supply line supplying a second potential. Each of the first and second circuits has first and second P-type transistors and an N-type transistor connected in series in order from the first-supply-line side. The gate of the first P-type transistor in the first circuit is connected to the drain of the N-type transistor in the second circuit. The gate of the first P-type transistor in the second circuit is connected to the drain of the N-type transistor in the first circuit. Input potentials opposite to each other are applied to the gates of the N-type transistors in the first and second circuits respectively and output potentials level-shifted from the input potentials are output from the drains of the N-type transistors in the first and second circuits respectively.

Abstract: A switching device (20) is formed to generate a ramp voltage by using a capacitor (48) formed on the semiconductor die (90) with the switching device (20). The switching device (20) drives a high-power device to conduct load currents for a load. The ramp voltage is used to gradually increase the drive that is applied to the high-power device in order to gradually increase the current conducted by the high-power device.

Abstract: A mixer includes a first terminal and a second terminal forming a first input port for receiving a first signal having a first frequency; a second input port for receiving a second signal having a second frequency; a mixer output port for a resulting signal; a first group of valves having their control inputs coupled to the first terminal for receiving the first signal; a second group of valves having their control inputs coupled to the second terminal for receiving the first signal; and a third group of two valves having their control inputs coupled for receiving the second signal. The valves co-operate such that in operation the mixer produces the resulting signal responsive to the first and second signals. The mixer also includes at least one passive low pass filter having an inductor, the low pass filter being connected to the control input of a valve in the first and second groups.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: Method and apparatus for using a MOSFET having a thin gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the MOSFET by applying a nonzero voltage to the source and the drain, and applying a voltage to a gate of the MOSFET. The voltage applied to the gate is greater than a voltage rating of the MOSFET but less than the sum of the voltage rating and the voltage applied to the source and the drain. The gate of the MOSFET may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The thin gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The MOSFET may be constructed using CMOS technology or BiCMOS technology. Apparatuses implementing this method include a capacitor, a read channel for a hard disk drive, and an electrical circuit for amplification of a signal.

Abstract: A circuit includes a current source providing an input current; first and second transistors having common control terminals and forming a current mirror generating a mirror current at the output of the second transistor. A control element having a first and second input and a first and second output is also provided; the first input being connected to the current source, the second input being connected to the output of the second transistor, the first output being connected to the common control terminals, and the second output being connected to the input of the first transistor of the current mirror. The control element is adapted to control the input to the first device and the voltage applied to the common control terminals in response to the inputs to the control device thereby maintaining the defined relationship between the input and output currents of the mirror. A method for implementing a current mirror in low headroom environments is also described.

Abstract: An amplifier circuit for delivering an output signal which varies in amplitude and in phase or frequency, has a power amplifier, an amplitude feedback circuit and a phase or frequency feedback circuit, both constituting closed loops together with said power amplifier, and at least one of said feedback circuits has its gain controllable in dependency of properties of the input or output signals, or both. A radio transmitter includes such an amplifier circuit, and a cellular telephone includes such a radio transmitter. The invention includes a method for controlling an output state in such a radio transmitter.

Abstract: An amplifier subsystem has a modulator to generate a pair of constant amplitude phase-modulated components which are in response to an input signal, a pair of channels that include a pair of power amplifiers to amplify the components, and a combiner to combine the amplified components. A number of variable gain elements are coupled into some of a number of signal paths of the amplifier subsystem. A controller is to receive feedback from the amplifier subsystem and in response maintains signal levels of some of the signal paths within predefined ranges and controls a net gain of the linear amplifier, by adjusting the variable gain elements.

Abstract: A system and method have been provided for determining a frequency tolerance between a generated clock and an input data rate. The invention analyzes beatnotes, externally generated through a comparison of clock and input data rates, and an overflow count of the clock. The occurrence of overflow counts, without intervening beatnotes, indicates that the clock and data rate are close in frequency. The occurrence of beatnotes without intervening overflow counts indicates that the clock and data rates are not close in frequency. Hysteresis is built into the system, preventing the system from indicating an out-of-lock condition when the beatnotes immediate follow the an overflow count, or when the system monitors occasional beatnotes.

Abstract: A precision, low jitter oscillator circuit is provided that is particularly well-suited for generating a clock signal in miniature digital systems, such as digital hearing aids. The oscillator includes a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal. The differential inverters include a capacitive trimming network for adjusting the frequency of the oscillating clock signal and employ resistive loads for minimizing jitter in the clock signal. The components of the oscillator are fabricated in a common silicon process to minimize the size of the oscillator.

Abstract: A gated oscillator is provided for digital circuits. The gated oscillator is achieved by the unconventional use of controlling the operating point of a Van der Pol oscillator. Oscillations are achieved by Van der Pol self-oscillation behavior.

Abstract: A nonreciprocal circuit device, which includes a permanent magnet; a ferrite to which a DC magnetic field is applied by the permanent magnet; a plurality of center electrodes extending from a first major surface of the ferrite to a second major surface of the ferrite via side surfaces of the ferrite; a ground plate disposed on the second major surface side of the ferrite and electrically connected to the plurality of center electrodes; a plurality of matching capacitors electrically connected between the ground plate and port sections of the plurality of center electrodes respectively; and at least one of the matching capacitors being disposed such that the capacitor electrode face thereof and the ferrite form an angle in a range of 60 degrees to 120 degrees.

Abstract: A compact dual element cascade circulator in which performance is enhanced while the size of the overall device is reduced. The circulator includes a plurality of junctions connected in cascade to provide a plurality of non-reciprocal transmission path between signal ports on a network, and a metal housing with a cover in which the junctions are disposed. The plurality of junctions includes a single oblong permanent magnet, a dual ferrite component including two (2) oblong ferrite elements, a dielectric constant medium disposed between the ferrite elements, and a plurality of conductor portions sandwiched between the ferrite elements. A single impedance matching structure is coupled between successive junctions.

Abstract: A high-frequency switch includes a transmission terminal, an antenna terminal, a reception terminal, and a voltage-control terminal; a first diode, the cathode thereof being electrically connected to the transmission terminal, and the anode being electrically connected to the antenna terminal; a first transmission line, electrically connected between the antenna terminal and the reception terminal; a second diode, the cathode thereof being electrically connected to the reception terminal, and the anode being electrically connected to the voltage-control terminal; a second transmission line, one end thereof being electrically connected to the transmission terminal, and the other end being connected to ground; and a capacitor, electrically connected between the voltage-control terminal and ground. The above high-frequency switch can be miniaturized and has superior performance.

Abstract: A transmission line, a resonator, a filter, a duplexer, and a communication apparatus efficiently minimize power losses due to edge effects, thereby having superior loss-reduction characteristics. A continuous line and a plurality of thin lines each having a predetermined length and branching from both sides of the continuous line are formed on a dielectric substrate. With this structure, edges of the individual thin lines substantially do not exist, so that losses due to edge effects can be efficiently minimized.

Abstract: Multi-stage electric filters with improved intermodulation-distortion characteristics and a method for designing such electric filters is provided. In general, the invention may include a multi-resonator electric filter in which one or more of the resonators have been intentionally designed to have a different IP and/or Q than the other resonators in the electric filter. In one case, the electric filters include a 4-resonator Chebyshev narrow pass-band filter with at least the first resonator having a Q and/or IP different from at least one other resonator in the filter. The filter thereby has improved IMD power over conventional designed filters while maintaining high Q. In a preferred embodiment the filter may include a superconducting material. The relative Q and IP of the respective resonators in the improved filter may depend on the relative strength of in-band and out-of-band signals.

Abstract: Here disclosed is a parallel-resonance type band-pass filter, which is employed for mobile communications equipment such as a mobile phone. According to the filter, each resonator has a single capacitor and serially connected plural inductors both of which are formed on the surface or on an inner layer of a substrate. Electromagnetic coupling between the resonators is established through electromagnetic coupling between at least a pair of inductors—the inductors of the pair belong to respective resonators. The input and the output terminals are coupled with the respective resonators via the capacitor having a properly determined capacitance. With such a simple structure, the filter also can work as an impedance transformer, with the result that the mobile communications equipment will be much smaller.

Abstract: A securing member for use in a switch assembly of a circuit breaker includes a support post and a fastener. The securing member assists in mounting an alarm switch onto a bracket of the switch assembly and further resists movement of the actuation levers of a pair of auxiliary switches from moving beyond a first given position and from potentially becoming caught in an operating mechanism that pivots a crossbar. The dual functionality of the securing member is cost effective and occupies only a minimal amount of additional space within the crowded confines of the circuit breaker.

Abstract: A circuit interrupter including a housing, separable main contacts disposed in the housing, and an operating mechanism disposed in the housing and interconnected with the contacts. A trip mechanism is disposed in the housing and has an automatic trip assembly that generates a tripping operation. The automatic trip assembly includes an armature and a magnetic yoke having pivot supports. The armature includes a head portion having a first hook-like member and an oppositely facing second hook-like member. The first hook-like member has a first recess, and the second hook-like member has a second recess. The automatic trip assembly includes a pivot pin positioned on the pivot supports and extending through the first recess and the second recess to provide a rotatable disposition of the armature. The assembly also includes a biasing member applying a force to the armature in a direction to normally rotationally displace a bottom portion of the armature away from the magnetic yoke.

Abstract: A switch with an open state and a closed state suitably includes a cantilever having first and second state corresponding to the open and closed states of the switch, respectively. The switch may also include a magnet configured to provide an electromagnetic field that maintains said cantilever in one of the first and second states. Various embodiments may also include an electrode or electrical conductor configured to provide an electric potential or electromagnetic pulse, as appropriate, to switch the cantilever between the first and second states. Various embodiments may be formulated with micromachining technologies, and may be formed on a substrate.

Abstract: A plurality of Liquid Metal Micro Switches (LIMMS) are mounted on opposite sides of a multi-layer substrate. Vias on the substrate and located within the footprints of the LIMMS serve to make connection with the LIMMS. Traces on the internal layers of the multi-layer substrate are routed around and over each other to arrive at a perimeter surrounding the LIMMS, where they emerge again as vias and are available for interconnection with further circuitry via conventional techniques, such as solder balls, wire bonding, a socket, etc. The multi-layer substrate may also incorporate a ground plane to assist in shielding and the fabrication of any interconnecting transmission lines.

Abstract: Electromagnetic relay having an increased insulating distance between a primary side circuit consisting of an excitation coil and an armature and a secondary side circuit consisting of a movable contact and a fixed contact, so that the withstand voltage of the relay is increased in comparison to prior art electromagnetic relays. The electromagnetic relay includes a base housing having a first insulating wall extending between the excitation coil and the armature, and a second insulating wall separating the movable and fixed contacts and the armature. An operating part of the relay presses the movable contact via a hole formed in substantially the central portion of the second insulating wall of the base housing.

Abstract: A superconducting magnetic resonance imaging magnet assembly is provided. The assembly includes an axial imaging bore to receive patients and a coil housing surrounding the axial bore. A main magnet coil assembly is disposed within the housing. The main magnet coil assembly includes a plurality of main magnet coils to produce a magnetic field. At least three pairs of superconductive coils are provided. In one aspect, each of the coils in at least one of the pairs comprises a superconductor wire carrying an electric current in a direction opposite to the direction of current carried by the coils of another of the superconductive pairs. The superconductor wire comprises a superconductor core and a stabilizer having a channel. The wire is wound so that the channel has a radially outward facing opening.

Abstract: A coil assembly comprises a coil wound upon a bobbin. A pair of terminals is supported by the bobbin. The coil has a pair of lead wires, each of which is connected to one of the terminals. Each terminal is adapted to be coupled to an electronic control unit. The coil is enclosed at least in part by a flux return casing. At least one resilient member is arranged and configured to urge the bobbin and the casing axially downward.

Abstract: A magnet configuration comprising a pair of Halbach arrays magnetically and structurally connected together are positioned with respect to each other so that a first component of their fields substantially cancels at a first plane between them, and a second component of their fields substantially adds at this first plane. A track of windings is located between the pair of Halbach arrays and a propulsion mechanism is provided for moving the pair of Halbach arrays along the track. When the pair of Halbach arrays move along the track and the track is not located at the first plane, a current is induced in the windings and a restoring force is exerted on the pair of Halbach arrays.

Abstract: A surface mounting type coil includes: a coil hiving windings which are wound around a magnetic core having a hole; a cylindrical magnetic body which is provided around the coil; and a plurality of metal plate terminals which leads of the windings are connected to; the metal plate terminals extending along an outer face of the cylindrical magnetic body from a bottom face to a top face thereof, and being secured to the cylindrical magnetic body in such a manner that tips of the metal plate terminals are within the thickness of the cylindrical magnetic body.

Abstract: The present invention relates to a coil (1) having a plurality of turns (2). The characteristic feature of the invention is that the turns (2) include a magnetic material or the turns (2) have an outer layer for carrying an electric current and have a magnetic material in their interior.

Abstract: To prevent a substrate for mounting electronic components from being damaged when cores are rubbed together during assembly, a pair of core members sandwich a part of a coil pattern formed on the substrate from the top and bottom sides of the substrate, and the core members are held together by a core-combining member. A cover member is fixed to the substrate to cover the upper side of the core-combining member. Inclined ribs on the cover member raise the core-combining member by abutting against external inclined fates of leg portions of the core-combining member. A clearance thereby is formed between internal faces of a top bar portion of each core member and a surface of the substrate.

Abstract: The present invention relates to an inductance element and its preparation method. The inductance element comprises a coil structure, an insulation layer, a conductive metal layer and a metal core layer. The preparation method comprises, preparation of a coil structure, applying an insulation material on said coil structure to fix said coil structure, applying a conductive metal layer and plating a magnetic material on said conductive metal layer to form a multiple-layered core structure. In the preparation of the multiple-layered core structure, an intermittent plating approach is adopted, such that the cross-sectional area of the magnetic circuit may be increased. The coil structure applicable to this invention includes one prepared on a printed circuit board or a winded enameled wire coil structure. When a group of two coils is prepared, the inductance element may function as a transformer.