Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.

Abstract: In the method for forming a capacitor of a nonvolatile semiconductor memory device, a TaON glue layer is formed over a semiconductor substrate, and a lower electrode is formed on the TaON glue layer. A ferroelectric film is then formed on the lower electrode, and an upper electrode is formed on the ferroelectric film.

Abstract: Disclosed are a DRAM cell having independent and asymmetric source/drain regions and a method of forming the same. The DRAM cell has an asymmetric structure in which source junctions are thick and drain junctions are thin. Therefore, the source/drain junctions have an asymmetric configuration via separate ion injection steps independent from each other, thereby preventing leakage current due to punch-through. Also, it is not necessary to form an ion injection layer for restraining punch-through, and a relatively low value of electric field is applied to the junctions to prolong refresh time. Further, the relatively thick spacer can be formed adjacent to the source regions thereby decreasing GIDL and further reducing electric field.

Abstract: The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.

Abstract: An improved method for forming a flash memory is disclosed. A self-aligned source implanted pocket located underneath and around the source line junction is formed after the field oxide between adjacent word lines is removed, and before or after the self-aligned source doping is carried out, so that the configuration of the implanted boron follows the source junction profile.

Abstract: A DRAM cell structure capable of high integration includes a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate, and a transistor being formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor. A method for fabricating a DRAM cell structure capable of high integration includes the steps of (a) forming a trench vertically and cylindrically in a silicon substrate, (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench, (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Abstract: A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.

Abstract: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The tunnel oxide layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Abstract: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.

Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

Abstract: A method and apparatus for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS). A capacitor is operatively coupled between the base and emitter terminals of the parasitic bipolar transistor. The capacitor effectively reduces the base to emitter voltage of the parasitic transistor thereby reducing leakage current generated at the collector terminal.

Abstract: A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: An organic electroluminescent display device includes a first substrate, a second substrate spaced apart and facing the first substrate, a switching thin film transistor disposed on an inner surface of the first substrate, a driving thin film transistor electrically connected to the switching thin film transistor, a connecting electrode electrically connected to the driving thin film transistor, a first electrode disposed on an inner surface of the second substrate, a partition wall disposed on the first electrode and having a transmissive hole corresponding to a pixel region between the first and second substrates, an organic layer disposed within the transmissive hole on the first electrode, and a second electrode disposed on the organic layer, wherein the second electrode is electrically connected to the driving thin film transistor through the connecting electrode.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: A protection circuit portion comprises a CMOS to which the drain of the nMOS transistor and the pMOS transistor are connected. The drain is connected to the input or output terminal. In the nMOS transistor, the gate insulating film and the gate electrode are formed on the substrate, and the source and the drain diffusion layer are formed on the surface of the substrate at a location sandwiching the gate electrode. A P-type channel layer diffusion layer connected to the source and the drain diffusion layer is selectively formed on a lower portion of the region constituting a channel. In the pMOS, the gate insulating film, the gate electrode and the source and drain diffusion layer are formed on the well layer formed on the surface of the substrate in the same manner as the nMOS, and a channel diffusion layer is formed on the entire region of the well layer on a lower portion of the region which constitutes the channel.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: An active matrix current source controlled gray level tunable FED. The inventive FED uses active devices to convert a voltage-controlled signal into an output current and a capacitor to record and hold the voltage-controlled signal, thereby producing a low control voltage and active current source driving FED. As such, adjustment and maintenance of the gray level brightness of the FED is achieved because the brightness fixed by the active devices and the capacitor can obtain a high transient brightness when the FED operates in a lower voltage and brightness, thereby producing a high average brightness and avoiding an arc from high-voltage operation or poor vacuum.

Abstract: A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.

Abstract: A mask ROM and a fabrication method thereof are described. The method includes forming a buried drain region in the substrate and forming a gate oxide layer on the substrate. A patterned dual-layer structure dielectric layer is formed on the gate oxide layer. A conductive layer, which is perpendicular to the direction of the buried drain region, is then formed on the gate oxide layer and on the dual-layer structure dielectric layer to form a plurality of code memory cells. The code memory cells that comprise the dual-layer structure dielectric layer correspond to the logic state of “0”, while the memory cells that do not comprise the dual-layer structure dielectric layer correspond to the logic state of “1”.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory.

Abstract: The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.

Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p−n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystalline growth forms the substrate layer (22), and this high quality crystal is used as the high resistivity layer in the device (20). The base layer (24) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface (32) of the substrate layer (22) at a fast rate greater than approximately 2 microns/minute. The top layer (26) is a diffusion layer diffused into an upper surface (34) of the substrate layer (22). To control stress in the wafer (28), the epitaxial base is doped with germanium.

Abstract: An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.

Abstract: A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. Then, the surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer remaining on the semiconductor substrate. Next, an etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. Last, a high-density plasma (HDP) oxide layer is deposited on the etch stopper. The semiconductor device and method for manufacturing the same are capable of preventing bubble defects.

Abstract: Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: A leadframe having component receiving projections, such as electrical connectors, adapted to receive a component thereon, such as a ferrite filter, and having means for securing the position of the component on the leadframe during premold or overmold processes.

Abstract: A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: In order to provide a semiconductor device which makes it possible to mount a semiconductor element on the substrate of the semiconductor device main body at the correct position with a higher degree of accuracy, a semiconductor element 2 is mounted at a circuit forming surface of a semiconductor substrate 1 at the periphery of which pad electrodes 5 are provided and a specific area in the semiconductor device containing the semiconductor element 2 is sealed with resin. At the circuit forming surface of the semiconductor substrate 1, reference lines 3 are formed in correspondence to the positions of at least three corners of the semiconductor element 2 to be mounted.