Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced. The method comprises the steps of: providing a bottom frame matrix including a plurality of bottom frame units, each of which unit comprises a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit comprises a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively, and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.

Abstract: A wire-bonded chip on board package has a substrate including a first resin. A solder mask made of a second resin having a thermal expansion coefficient identical to that of the first resin of the substrate is disposed on the top surface of the substrate such that it has a smooth outer surface and some openings to expose the respective areas of the conductive patterns on the top surface. An IC chip with an inactive side thereof tightly attaches to the outer surface of the solder mask. Wire bonds electrically connect the contact pads formed on an active side of the IC chip to the conductive patterns of the top surface. A molding material encapsulates the chip, the wire bonds and the substrate top surface.

Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.

Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system.

Abstract: The present invention provides a method of forming an integrated semiconductor device, and the device so formed. An active surface of at least two semiconductor devices, such as semiconductor chips, are temporarily mounted onto an alignment substrate. A support substrate is affixed to a back surface of the devices using a conformable bonding material, wherein the bonding material accommodates devices having different dimensions. The alignment substrate is then removed leaving the devices wherein the active surface of the devices are co-planar.

Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: A method for assembling FCBGA packages having fewer heating cycles and process steps than prior art is made possible through the use of a novel carrier pallet. The pallet includes recesses which mirror external solder ball contacts of the BGA package under assembly. A solder ball is positioned in each recess, a chip carrier substrate aligned and positioned atop the solder, a chip having flip chip contacts aligned to the opposite surface of the chip carrier, and the assemblage subjected to heating and cooling as required to connect both sets of contacts in a single thermal cycle. As required by the device under assembly, an underfill material and a protective cover may be included in the assembly process while making use of the carrier pallet, and without moving the devices. The carrier pallet may be used for transporting and attaching solder contacts of many types of BGA or CSP devices. Yield, reliability, and cost advantages are made possible by the invention.

Abstract: Disclosed herein is a chip on board lead package for optical mice and lens cover for the same. A semiconductor chip on board package for optical mice has a board, a semiconductor chip, at least one circuit pattern, at least one bonding wire, and a lens cover. The board has top and bottom surfaces, and a pair of via holes. The semiconductor chip is attached to a center portion on the top surface of the board and provided with a plurality of electrode terminals. The circuit pattern is formed on the top surface of the board. The bonding wire electrically connects the electrode terminals of the semiconductor chip with the circuit pattern. The lens cover encloses the top surface of the board and has a lens disposed on the same axis as that of the semiconductor chip, a plurality of electrode pins formed at positions of the lens cover corresponding to the positions of the via holes in the board to be integrated with the lens cover, and an opening formed in a center portion within the lens cover.

Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.

Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.

Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: A dual-side thermal interface and cooling design of an integrated power module is disclosed which effectively reduces the equivalent thermal impedance on the power module by 20%. This in turn reduces the temperature rise of the junction temperature of the power devices inside the power module by 20% with an equivalent load current. As a consequence the weight and volume associated with the conventional cooling mechanism not employing a dual thermal interface is reduced, thus increasing the ambient operating temperature limit of a power converter in the module.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A semiconductor device that includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semi-conductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

Abstract: There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized.

Abstract: To prevent Al wiring formed on a via-hole in which a CVD-TiN film is embedded from corroding.

Abstract: An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging-semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

Abstract: A multi-layered wiring structure has a tungsten plug embedded in an inter-level insulating layer and an upper aluminum alloy line held in contact with the upper surface of the tungsten plug and a reservoir projecting beyond the tungsten plug, and electric current flows from the upper aluminum alloy line into the tungsten plug, wherein the gradient of current density toward reservoir is larger than the gradient of current density toward the upstream side so that the reservoir effectively supplements aluminum atoms to vacancy generated around the boundary between the upper aluminum alloy line and the tungsten plug, thereby enhancing the resistance against the electromigration.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure having a substrate, a layer of a first dielectric material on the substrate; and spaced apart metal contacts on the layer of the first dielectric material. There is a space between adjacent metal contacts and each space is filled with the first dielectric material. A recess is formed in the filled spaces of the first dielectric material which extends from a level at a top of the metal contacts a part of the distance toward the substrate. A second dielectric layer is on at least some of the metal contacts and in the recesses on the filled spaces of the first dielectric material such that there is optionally a gap in the recesses of the second dielectric layer at side walls of the metal contacts. An additional layer of the first dielectric material is on the second dielectric layer.

Abstract: During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit. These further interconnects, depending on the availability of components for driving or evaluation, are embodied as sensor interconnects or else as connectionless interconnects only to confuse potential hackers.

Abstract: Disclosed is a multilayer integrated circuit structure joined to a chip carrier, and a process of making, in which the area normally occupied by a solid dielectric material in the IC is at least partially hollow. The hollow area can be filled with a gas, such as air, or placed under vacuum, minimizing the dielectric constant. Several embodiments and processing variants are disclosed. In one embodiment of the invention, the wiring layers, which are embedded in a temporary dielectric, alternate with via layers, also embedded in a temporary dielectric, in which the vias, besides establishing electrical communication between the wiring layers, also provide mechanical support for after the temporary dielectric is removed. Additional support is optionally provided by support structures though the interior levels and at the periphery of the chip. The temporary dielectric is removed subsequent to joining by dissolution or by ashing in an oxygen-containing plasma.

Abstract: A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer 10) with good step coverage formed on a surface of a conductor film such as lower electrodes 9 and 9a of a capacitor on a semiconductor substrate is transformed into a reformed layer 11, which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

Abstract: Low-strength plasma treatment for interconnects is disclosed. A low k dielectric-metal interconnect is formed that has a top surface, via a damascene process, such as a single- or a dual-damascene process. The top surface of the low k dielectric-metal interconnect is low-power plasma treated to substantially cure any damage to the top surface resulting from the damascene process. Such damage may include the entrapment of metal ions, such as copper ions where the metal of the interconnect is copper, and chemical-mechanical planarization (CMP) materials resulting from the CMP employed during the damascene process, within the top surface of the low k dielectric-metal interconnect. The low-power plasma used may be helium plasma.

Abstract: A method to improve nucleation and/or adhesion of a CVD or ALD-deposited film/layer onto a low-dielectric constant (low-k) dielectric layer, such as a polymeric dielectric or a carbon-doped oxide. In an embodiment, the method includes providing a substrate into a deposition chamber. A dielectric layer having a reactive component is formed over the substrate. The formed dielectric layer having the reactive component is then processed to produce polar groups or polar sites at least on a surface of the formed dielectric layer.

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Abstract: In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and has conductive traces formed thereon. A soldermask is received on the one side, and has a plurality of openings formed therethrough to locations on the conductive traces. The soldermask includes a peripheral elongated trench therein positioned on the one side to align with at least a portion of an elongated mold void perimeter of a transfer mold to be used for transfer mold packaging of the one side. In one implementation, the invention includes a transfer mold semiconductor packaging process. In one implementation, the invention includes a semiconductor package. In one implementation, the invention includes a ball grid array.

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract: A method of manufacturing a lens presenting a graded tint, the lens comprising first and second layers each of which is made of a thermoplastic material, with only one of the layers being colored in the tint concerned, the method comprising the steps of:

Abstract: Apparatus is disclosed for repairing a flaw in a surface, particularly in the field of vehicle glass repair. The apparatus has a housing adapted to engage the surface to be repaired, a repair seal for sealing between the housing and around the flaw to be repaired to define a repair space over the flaw. A reservoir communicates with the repair space and, in use, contains liquid repair material. A vacuum pump communicates with the repair space and the reservoir to apply a partial vacuum to the repair space and to the reservoir without repair liquid from the reservoir being drawn into the repair space in order to degas separately the flaw and repair liquid in the reservoir. After appropriate degassing, repair liquid from the reservoir is caused to flow into the repair space to fill the repair space with repair liquid.

Abstract: Nano-sized particles such as nano-clays can be mixed with polymers through either melt compounding or in-situ polymerization. By modifying the particle surface with various surfactants and controlling processing conditions, we are able to achieve either intercalated (partial dispersion) or exfoliated (full dispersion) nano-clay distribution in polymers with the clay content up to 35% by weight. When a blowing agent is injected into the nanocomposite in an extruder (a continuous mixer) or a batch mixer, polymeric foam can be produced. Supercritical carbon dioxide, an environmentally friendly, low-cost, non-flammable, chemically benign gas is used as the blowing agent. This process forms a microcellular foam with very high cell density (>109 cells/cc) and small cell size (<5 microns) can be achieved by controlling the CO2 content, melt and die temperature, and pressure drop rate.

Abstract: A method for the automatic production of hollow bodies from mixed material, particularly concrete. A mold assembled from a mold core comprising a shaking device, an exterior mold and a bottom sprue is positioned in a molding area, non-solidified bulk material, particularly unset concrete, is uniformly filled into the mold space between the mold core and the exterior mold, the mixed material is compressed by shaking, an upper centering end is formed by pressing an upper sprue into the unset concrete column and thereafter the so formed, still soft molded body is removed from the mold by extraction and is transported to a drying area. At least some of the mold components are automatically assembled in an assembly area previous to a mold exchange and moved into the molding area as a pre-mounted assembly. Previous to a renewed mold exchange they are reassembled in the molding area to form an independent assembly to be transported off.

Abstract: An extrusion molding apparatus for a product having a wood pattern and an extrusion molding method are disclosed, in which a second synthetic resin containing a wood powder of 80˜120 meshes at a predetermined ratio is fed to a die through a second extruder and then is coated on a surface of the product, thereby providing an esthetic surface and an improved durability.

Abstract: Described are methods of making electrodes for electrochemical systems, especially cathodes for lithium polymer batteries, and products prepared from the methods; the methods involve the use of a co-rotating, fully intermeshing twin screw extruder, the extrusion of essentially solvent-free systems, or both.

Abstract: A manufacturing method for environment-friendly food container is disclosed. The process employs paddy husk or vegetative plant stalks to be crushed or ground into powdery form. These materials are then mixed and stirred with water, oil, surfactant and adhesive. The product is then proceeded to a second stirred mixing process and is then proceeded to a squeezing device to form into plate-like material directly leaded to a pressing device. The plate-like material is then proceeded to a first drying process, a glue-containing process and a second drying process. The material after the second drying process can be used for the fabrication of containers for food.

Abstract: Disclosed are a device, in which a plurality of components are vertically stacked on a substrate without any cavity being formed thereon, and a method for manufacturing the device, thereby easily manufacturing the device, improving the productivity of the device, and reducing the production cost of the device. The device of the present invention is manufactured by mounting a plurality of first components on a base substrate and forming supporters on the upper surface of the base substrate so that two or more of the supporters are arranged around each of the first components, molding the upper surface of the base substrate including the first components and the supporters, dicing the molded base substrate into device units, and mounting a second component on each of the upper surfaces of the diced parts of the base substrate.

Abstract: A molding die assembly includes an upper die and a lower die, wherein at least one of the upper and lower dies is provided with a cavity corresponding to the shape of a rubber member to be molded, wherein at least one of the upper and lower dies is provided with an annular projection around a cavity. The distance between the upper and lower dies at the annular projection is made smaller than the distance between the opposed surface portions, other than the cavity, of the upper and lower dies. A rubber member produced by the above mentioned molding die assembly is also provided.

Abstract: The invention is directed to a class of fiber or strand suspension compositions that may be processed further into viscoelastic pastes or porous solids. The preferred compositions of the invention comprise biologically derived or biologically compatible materials, such as collagen, that can be injected or implanted for tissue augmentation or repair. This invention is also directed to methods of making these compositions and to apparatus that can be used to make the compositions.

Abstract: This invention is a method for making purses and other bags. The first part of the process is forming a female mold of the bag. This mold can be formed in extreme detail. The mold is then preheated and colored plastic is then poured into it. The mold is then lowered into a hot oil or salt bath and the plastic and the hot oil or salt reacts causing the plastic to line the interior wall of the mold. The mold is then taken out of the hot oil or salt bath and placed in a cooling tank where the plastic is cooled and sets. The mold is taken out of the cooling tank and the unfinished bag is removed from the mold. The bag is then finished by polishing and adding any accessories such as snaps, zippers, linings, and handles to the bag. The process can be used to form a hard or soft sided bag.

Abstract: The present invention is related to a rotary cooling station to be used in conjunction with a high output injection molding machine and a robot having a take-out plate. More particularly, the present invention teaches a high speed robot that transfers warm preforms onto a separate rotary cooling station where they are retained and internally cooled by specialized cores. The preforms may also be simultaneously cooled from the outside to speed up the cooling rate and thus avoid the formation of crystallinity zones. Solutions for the retention and ejection of the cooled preforms are described. The rotary cooling station of the present invention may be used to cool molded articles made of a single material or multiple materials.