Abstract: A flash memory bridging device, method and application system. The flash memory bridging device provides a buffer region that serves as a cache for storing the address of a portion of a NAND flash memory. A cache control logic inside the flash memory bridging device is used to determine if the requested data is a cache hit so that a direct response is possible or a cache miss so that waiting is demanded. During a data read operation, an error correction function is implemented so that data errors are corrected. Using NAND flash memory to simulate the operation of the NOR flash memory and store program code and data not only lowers production cost, but also improves overall performance and reliability of the system.

Abstract: A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using a photoresist. One bit line BL connected to the two NAND-type memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 1000 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

Abstract: System for setting reference cell threshold voltage of a memory device. The memory device includes a plurality of core cells and first and second reference cells all coupled to a common word line. The method comprises steps of programming the first reference cell to a first voltage threshold level that is centered within a data bit “1” distribution of the core cells, and programming the second reference cell to a second voltage threshold level that is centered within a data bit “0” distribution of the core cells.

Abstract: A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Abstract: A sense amplifier enable signal generating circuit includes a dummy bit cell which is connected to a dummy word line and a dummy bit line and discharges the dummy bit line in response to a signal level of the dummy word line. The sense amplifier enable signal generating circuit further comprises a process tracking circuit which adjusts a signal level of the dummy word line in response to a signal level of the dummy bit line to adjust a discharge rate of the dummy bit line, and a sense amplifier control circuit that generates the sense amplifier enable signal responsive to the signal level of the dummy bit line. In further embodiments, the sense amplifier control circuit includes a control circuit that generates the sense amplifier enable signal responsive to an internal clock signal and a control signal. A process adjusting circuit is connected to the dummy bit line and generates the control signal responsive to a signal level on the dummy bit line and the internal clock signal.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: An array of memory cells of an integrated circuit are organized so metal bitlines are segmented. The memory cells may be nonvolatile memory cells such as floating gate, Flash, EEPROM, and EPROM cells. The bitlines for the memory cells are strapped to metal, and the metal bitline is segmented. The individual segments may be selectively connected to voltages as desired to allow configuring (e.g., programming) or reading of the memory cells. The programming voltage may be a high voltage, above the VCC of the integrated circuit. By dividing the metal bitlines into segments, this reduces noise between bitlines and improve the performance and reliability, and reduce power consumption because the parasitic capacitances are reduced compared to a long metal bitline (i.e., where all the segments are connected together and operated as one).

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “1” (or logic “1) is successively performed.

Abstract: A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

Abstract: MRAM cells include a magnetic resistor having first and second terminals, and access transistor that is connected to the first terminal, and a bit line that also is connected to the first terminal. A reading word line is connected to the second terminal, and a word line is connected to the access transistor. The first terminal may include a conductive axis and the magnetic resistor at least partially surrounds the conductive axis. The MRAM cell may be written by turning on the access transistor to force writing current into the first terminal, and thereby change the resistance of the magnetic resistor. Reading may be performed by applying voltage between the bit line and the reading word line, and sensing current through the magnetic resistor in response.

Abstract: A circuit and method according to an embodiment of the invention synchronize multiple digital data paths, each containing a set of digital data signals and an associated clock signal. The circuit includes a dual-port memory having a first port configured to store samples of each set of digital data signals by way of the clock signal associated with each set. A second port of the memory is configured to retrieve the stored samples, with the retrieval of the samples being timed so that each of the sets of digital data signals is synchronized with each other and with one of the clock signals.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.

Abstract: The present invention provides a method of recording information on a memory medium and reading the information, comprising the steps of forming a reflective or transmissive surface having an anisotropic microstructure on a substrate of the memory medium to record information in the microstructure, entering light onto the reflective or transmissive surface, and detecting change in the polarization or intensity of a reflected or transmitted light caused by the microstructure, to read the information. The present invention also provides a memory medium, a production method thereof, and an information reading system.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: In the conventional nonvolatile memory, it is not possible to determine the cause of the error is accidental or due to the degradation when the error is detect at the time of data read. Therefore, unnecessary substitute processing is performed, resulting in the exhaustion of the substitute area to shorten the life of the storage device.

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Abstract: Systems, devices, structures, and methods are described that reduce energy consumption during a refresh cycle in a memory device. An isolation signal is held in a non-energized state until the it is determined that another action is to be performed on the section of memory associated with the isolation signal. The isolation accordingly cycles from an energized state to a non-energized state and back for each complete refresh cycle in the section of memory.

Abstract: An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.

Abstract: This associative memory circuit comprises a plurality of logic circuits connected to a common match line. Each of the logic circuits compares a content stored in each of a plurality of memory cells with externally supplied search data so as to output a comparison result thereof to the match line. The associative memory circuit also comprises a reference-potential producing circuit provided correspondingly for the match line so as to produce a reference potential used in relation with the match line, and a differential amplifier circuit performing a differential amplification to a potential of the match line and the reference potential so as to judge whether or not the content matches the search data.

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.

Abstract: An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.

Abstract: An embedded memory unit includes a memory array having a design size given by an integer n, the array including a matrix of memory cells arranged in n+1 lines, and selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read. A built-in self-test (BIST) circuit is coupled to test the memory array and to generate a binary pass/fail output. A repair machine is coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the array has passed the self-test.

Abstract: A semiconductor memory device and a method for pre-charging the same, the semiconductor memroy device comprising a plurality of memory cell array blocks, each having a plurality of memory cells connected between respective bit line pairs and respective word line pairs, a plurality of pairs of data input/output lines connected to the respective bit line pairs for transferring data, a first pre-charge circuit for pre-charging the bit line pairs to a first pre-charge voltage during a first operation, a second pre-charge circuit for pre-charging the data input/output line pairs and the first pre-charge voltage to the first pre-charge voltage during the first operation, a plurality of third pre-charge circuits, each being disabled in the first operation and pre-charges the data input/output line pairs in the corresponding memory cell array blocks to a second pre-charge voltage during a second operation, and a discharging circuit for lowering the first pre-charge voltage when the first pre-charge voltage is greater

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A method and system for minimizing a leaked current within an array of memory cells as well as a method and system for differentiating a resistive value within a sensed memory cell during a read operation are disclosed. The memory array includes a plurality of bit lines and word lines that are cross-coupled via a plurality of memory cells. Each memory cell is limited in providing a conductive path in a first direction only by way of a unidirectional element. Such unidirectional elements typically comprise of diodes. The apparatus utilizes the diodes to form a current path from the bit line to the word line having passed through the diode and resistive memory cell. Further, a differential sense amplifier is utilized to differentiate the sensed current during a read operation from a reference value after an equipotential value is placed across the array to limit leakage current from developing within adjoining word and bit lines during a sense operation of a given memory cell.

Abstract: Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: An isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode and as the other of the logic high and logic low during another portion of the standby power mode to prevent unnecessary switching every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. The switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is likewise prevented. In other embodiments, methods, electronic systems, wafers and DRAM are taught.

Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: A hierarchical bit line selection circuit is connected between a plurality of pairs of bit lines of a plurality of sub-arrays of a random access memory and a data line sense amplifier. The bit line selection circuit has a bit line selector circuit to selectively couple one pair of bit lines of the plurality of bit lines of each sub-array to the pair of local data lines. The bit line selection circuit further has a local data line selector circuit to select one of a plurality of pairs of local data lines to be connected to a pair main data lines that are connected to the inputs of the data line sense amplifier. The memory cell sub-arrays are folded in placement with the main data line switches to reduce data access time.

Abstract: To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.

Abstract: A tip for an extruder screw includes a body having a first end for attachment to a screw, a second end, and an outer surface. A wiper extends outwardly from an outer surface of the body. In one embodiment, the wiper is a substantially helical conveying flight. In another embodiment the tip includes at least two substantially helical conveying flights on the outer surface of the body.

Abstract: A mixing apparatus having a channel for guiding an input gas stream, a drop on demand fluid drop emitting apparatus for emitting drops of a fluid into the input gas stream to produce a gas mixture that contains the fluids drops, and a pressure control system for controlling a pressure of the fluid in the drop on demand fluid drop emitting apparatus.

Abstract: A mixing apparatus that includes a drop on demand fluid dispenser for adding an additive fluid to a receiver liquid to produce a composite liquid that includes the receiver liquid and the additive fluid.

Abstract: A plastic disruption and homogenization device. The device has rotor that is axially disposed within a stator. The stator and the rotor have several teeth to aid the disruption and homogenization process. The device consists of plastic material that allows the rotor to rotate smoothly without the use of bearings.

Abstract: A method of determining the sonic slowness of a formation traversed by a borehole comprising generating tracks from sonic waveform peaks received at a plurality of depths wherein the peaks that are not classified prior to tracking is set forth. A method for generating a slowness versus depth log is generated for waveform arrivals by classifying long tracks, classifying small tracks; classifying tracks that overlap; filling in gaps; and creating a final log is disclosed.

Abstract: The specification discloses a system and related method for determining characteristics of earth formations traversed by a borehole. An acoustic transmitter mounted on a tool, whether that tool is a wireline tool or a logging-while-drilling tool, imparts acoustic energy into the formation, and a plurality of receivers spaced apart from the transmitter and from each other receive acoustic energy responsive to the transmitter firing. Portions, or all, of each received signal are used to estimate source signals using an assumed transfer function. Each of those estimated source signals are then compared in some way to determine an objective function. This process is repeated for multiple assumed transfer functions, and at multiple starting times within the received signals. By searching for minimas of a plot of the objective function, characteristics of the earth formation may be determined.

Abstract: The patent discloses a signal processing technique for determining the fast and slow shear wave polarizations, and their orientation, for acoustic waves in an anisotropic earth formation. The signal processing method decomposes composite received waveforms a number of times using a number of different strike angles. The decomposed signals are used to create estimated source signals. The estimated source signals are compared in some way to obtain an objective function. Locations in a plot where the objective function reaches minimum values are indicative of the acoustic velocity of the fast and slow polarizations within the formation.

Abstract: The composition of the seabed can be estimated by measuring the amplitude of echoes back-scattered from the seabed. However, the amplitude measured varies not only with the type of material present on the seabed but also with the range travelled to and the angle of incidence of the transmitted pulse at the seabed. This invention is a method for adjusting the amplitudes of backscattered echoes to compensate for the attenuation due to range and angle of incidence. A compensation table is created, each cell of which is associated with a unique combination of a partition of range and a partition of angle of incidence values. Each cell contains summary data for all echo amplitudes associated with that cell. The echo amplitude values are then adjusted using the summary data held in the compensation table.

Abstract: An electro-mechanical transducer, which provides amplified piston motion from an orthogonal drive direction wherein the electro-mechanical drive additionally provides the inertial reactive mass for the moving mass of the piston. The piston motion is amplified by lever arms, which are typically attached to a piezoelectric or electrostrictive drive system. The arrangement allows a compact, high output transducer design.

Abstract: A welding hood assembly which includes a voice-activated lens shade adjusting device. The welding hood is equipped with an electronically-controlled lens whose shade darkness can be immediately and incrementally adjusted via voice commands spoken into a microphone mounted inside the hood and integrated with a voice-command system. When the welder produces a voice command for a specific degree of shading, the lens will immediately change to the desired level of shade.