Abstract: The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the semiconductor substrate with a channel region therebetween. The source and drain region of the semiconductor substrate are then subjected to an angled amorphization implant, wherein the angled amorphization implant amorphizes the semiconductor substrate thereat and in portions of the channel region near a lateral edge of the gate, thereby defining an amorphized source extension region and drain extension region, respectively. The method continue with an implantation of the source region and the drain region with a lightly doped p-type source/drain implant, followed by an anneal to repair damage in the semiconductor substrate due to the pre-amorphizing implant and the lightly doped source/drain implantation.

Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: An SOI (Silicon On Insulator) substrate is provided with: a support substrate (201); a single crystal silicon layer (202) disposed above one surface of the support substrate; an insulation portion (205) disposed between the support substrate and the single crystal silicon layer, the insulation portion comprising a single layer of an insulation film or a lamination structure of a plurality of insulation films, and including a silicon nitride film or a silicon nitride oxide film (204).

Abstract: An apparatus and method for manufacturing substrate elements includes providing a mother substrate, and forming a plurality of through-holes on first lines and second lines opposing each other across sections on the mother substrate. The sections define each of the substrate elements to be formed. The through-holes on the first lines are disposed alternately with respect to the through-holes on the second lines. Electrodes are also provided on the principal plane of the mother substrate and on the inner surfaces of the through-holes. Then, the mother substrate is cut along cut lines in the vertical and horizontal directions.

Abstract: A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract: This invention relates to a method for forming a dielectric layer, more particularly, to a method for forming a silicate dielectric layer. The first step of the present invention is to form a silicate layer on the substrate of the wafer by using a physical vapor deposition (PVD) procedure. The silicate layer is a hafnium silicate (HfSi) layer or a zirconium silicate (ZrSi) layer. Then the silicate layer is treated to become a gate dielectric layer or an inter-layer dielectric layer which has higher a dielectric constant by using a rapid thermal annealing (RTA) procedure in a environment which is filled of nitrogen or ammonia.

Abstract: A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure.

Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.

Abstract: This invention provides raw material compounds for use in CVD which contain an organic iridium compound as a main ingredient, the organic iridium compound consisting of tris(5-methyl-2,4-hexanedionato)iridium. According to the CVD which uses the above raw material compounds, a pure iridium thin film and an iridium oxide thin film of excellent morphology can be produced effectively.

Abstract: A method for fabricating a semiconductor device and forming an insulating film used therein, includes forming an isolation insulating film on a semiconductor wafer and forming gates, separated by gaps having a predetermined distance, on an active region. Next, a first interlayer dielectric film is deposited to a predetermined thickness on the semiconductor wafer having the gates, so that the gaps between the gates are not completely filled. Then, a sputtering etch is performed entirely on a surface of the first interlayer dielectric film. Thereafter, the first interlayer dielectric film is partially removed through isotropic etching. Next, a second interlayer dielectric film is deposited on the first interlayer dielectric film so that the gaps between the gates are completely filled.

Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

Abstract: A method for forming a copper containing semiconductor feature to prevent thermally induced defects in including: (a) providing an anisotropically etched opening formed in a dielectric insulating layer; (b) conformally depositing a barrier layer over the anisotropically etched opening; (c) conformally depositing a copper portion to fill a portion of the anisotropically etched opening with copper; and, (d) repeating steps b and c at least once to completely fill the anisotropically etched opening to form a copper filled semiconductor feature.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: A copper damascene structure including a titanium-silicon-nitride barrier layer formed by organic-metallic atomic layer deposition is disclosed. Copper is selectively deposited by a CVD process and/or by an electroless deposition technique.

Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer and covering the metal over isolation regions.

Abstract: The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.

Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.

Abstract: An organometallic precursor for forming a metal pattern and a method of forming the metal pattern using the same, in which an electrically conductive metal pattern is formed using an organometallic precursor, through an exposing step without using a separate photosensitive resin. The exposure time required to dissociate the organic ligands from the metals of the organometallic precursor is very short making the overall patterning process very efficient.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: Resistive memory elements and arrays for data storage devices are disclosed. An exemplar resistive memory element generally comprises a first conductive structure and a second conductive structure, each of the conductive structures having a width of less than 1&lgr;, anti-fuse material on each conductive structure, and conductive material on the anti-fuse material such that anti-fuse material is interposed between each conductive structure and the conductive material.

Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: A charge separation heterojunction structure which uses a fullerene polymer film as a part of its constituent materials and which may be used to produce a solar cellor a light emitting diode superior in durability, physical properties of electrons and economic merits. The heterojunction structure is such a structure in which an electron-donating electrically conductive high-polymer film and an electron-accepting fullerene polymer film are layered between a pair of electrodes at least one of which is light transmitting. In forming the layers, the fullerene polymer film is identified using in particular the Raman and Nexafs methods in combination so that upper layers are formed after identifying the polymer film.

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

Abstract: A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

Abstract: This invention provides an inspection method and device which can efficiently measure the altitude distribution of a surface of a semiconductor device which is chemically and mechanically polished based on measured data at several points on the surface of the chip. In operation, exposure mask data for the semiconductor device is divided into arbitrary regions, in an arbitrary region j of the exposure mask data, &rgr;j=Pj/Sj which is a ratio between an area Sj of the region j and an area Pj of a portion in the region j where a pattern is present is calculated. An altitude Hj of the semiconductor after chemical mechanical polishing is obtained by a simulation which is performed using, as parameters, the ratio &rgr;j, a size h of a step on a surface of the semiconductor device before polishing, a polishing speed K, Young's modulus G of a polishing pad, a half-value width Rc of a stress function and a thickness d of the polishing pad.

Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophillic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconductor substrate in a bath containing an oxidizing agent, or by the addition of an oxidizing agent to the chemical slurry used during planarization of the resist material.

Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Abstract: Disclosed herein is a method of etching deep trenches in a substrate which utilizes the overlying mask structure to achieve a trench having a positive tapered sidewall angle of less than about 88°. The method employs the successive etching of a lateral undercut in the substrate beneath a masking material, while at the same time etching vertically downward beneath the mask. The coordinated widening of the lateral undercut at the top of the trench, while vertically extending the depth of the trench, is designed to provide the desired trench sidewall taper angle.

Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. The method includes depositing a first portion of the film by forming a high density plasma from a first gaseous mixture flown into the process chamber. The deposition processes is then stopped and part of the deposited first portion of the film is etched by flowing a halogen etchant into the processing chamber. Next, the surface of the etched film is passivated by flowing a passivation gas into the processing chamber, and then a second portion of the film is deposited over the first portion by forming a high density plasma from a second gaseous mixture flown into the process chamber. In one embodiment the passivation gas consists of an oxygen source with our without an inert gas.

Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas.

Abstract: The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.

Abstract: A method for processing a wafer in a plasma processing chamber using single frequency RF power is provided. The method includes generating a single modulated RF power and providing a wafer over an electrostatic chuck in a plasma processing chamber. The electrostatic chuck includes a first electrode disposed under the wafer for receiving the modulated RF power, and a second electrode disposed over the wafer. The method further includes receiving the modulated RF power, by the plasma processing chamber, and generating plasma and ion bombardment energy in the plasma processing chamber for processing the wafer in response to the modulated RF power.

Abstract: Looser and tighter pitch geometries in semiconductor layouts may be fractured into separate groups and defined separately on at least two separate photomasks. Thereafter, the looser pitch geometries may be exposed using a first mask and the tighter pitch geometries may be exposed using a second mask. The conditions of exposure may be optimized for the different geometries. As a result, the customized exposures for each type of geometry may be optimized without some of the compromises conventionally required.

Abstract: We have developed a method of selectively etching silicon nitride relative to oxides in a high density plasma chamber of the kind presently known in the art. We have obtained selectivities for silicon nitride:silicon oxide in the range of about 15:1 to about 24:1. We have employed the method in the etching of silicon nitride spacers for sub 0.25 &mgr;m devices, where the spacers are adjacent to exposed oxides during the etch process. We have obtained silicon nitride spacers having rounded top corners and an extended “tail” toward the bottom outer edge of the nitride spacer. The method employs a plasma source gas which typically includes SF6, HBr, N2 and optionally, O2. Typically, the pressure in the etch chamber during etching is at least 35 mTorr and the substrate temperature is about 20° C. or less.

Abstract: A method for reactive ion etching of Si02 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.

Abstract: The invention includes a semiconductor construction comprising a semiconductor substrate, and a first layer comprising silicon and nitrogen over the substrate. A second layer comprising at least 50 weight % carbon is over and physically against the first layer, and a third layer consisting essentially of a photoresist system is over and physically against the second layer. The invention also includes methodology for forming the semiconductor construction.

Abstract: To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.

Abstract: High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.