Abstract: A growth method for a bulk II-VI type semiconductor material, including at least a first component and a second component. The method supplies in a crucible a charge including the components, with proportions of the components being such that the first component is used as a solvent. The crucible is then laced in an open tube reactor. The reactor temperature is then raised to obtain a temperature profile in the reactor ensuring the melting of the charge in the crucible and with the evaporation of the first component beginning, with the pressure inside the reactor being adjusted by the circulation of a gas so that the atmospheric pressure, with the partial pressure of the first component being greater than the partial pressure of the second component.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.

Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

Abstract: A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.

Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor element on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.

Abstract: An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.

Abstract: The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.

Abstract: A semiconductor device is manufactured by an integrated circuit forming process, and a series of subsequent steps. In the series of steps, a protection tape 18 is adhered onto a first surface of a semiconductor substrate on which a plurality of semiconductor elements are formed, and the second surface of the semiconductor substrate is ground so that the semiconductor substrate has a desired thickness, the semiconductor substrate is then conveyed while controlling the temperature of the semiconductor substrate. The semiconductor substrate is then separated into a plurality of semiconductor elements. The occurrence of warping on the semiconductor substrate during conveyance of the semiconductor substrate is thus prevented.

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.

Abstract: This invention provides a method for manufacturing a semiconductor chip package which mainly utilizes a substrate having a organic surface protection thereon to package a central-pad chip. In the encapsulating process, since the molding flash is completely formed on the surface of the organic surface protection, the molding flash can be easily removed together with the organic surface protection without damaging the substrate surface. This invention further provides a method for manufacturing the substrate.

Abstract: A kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. The method relates to an analysis of the geometrical relationship between non-predetermined portion(s), generally referred to as defects, and the surrounding predetermined topology of a conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of a wafer, and particularly an examined die thereon. Further, in accordance with this geometrical information, a preferred classification of the effects of defects into a numerical value, the “kill index”, is achieved. Preferably, this kill index is strongly linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.

Abstract: A base film is formed for the TFTs in order to prevent diffusion of impurities from the glass substrate into the active layer, to maintain stability in the characteristics such as Vth and S-value of the TFTs and to maintain enhanced productivity. A film in which the composition ratios of N, O and H are continuously changed by changing the flow rates of H2 and N2O, is used as the base film to prevent a change in the TFT characteristics. The base film can be formed by varying the flow rates of H2 and N2O in the same film-forming chamber to enhance the productivity.

Abstract: According to the present invention, a semiconductor device to use a SOI substrate performing insulation by a LOCOS method in which an oxide resistivety film provided on a silicon layer is used, includes steps of: implanting impurity in a LOCOS edge which is a silicon layer under bird's beak of the field oxide film with the oxide resistant film as a mask after a field oxide film is formed and forming a high density impurity area having impurity density higher than impurity density of an impurity diffusion layer formed on the silicon layer, and removing a pad oxide film after a heat treatment is performed for the field oxide film after the high density impurity area is formed. Therefore, a method of manufacturing the semiconductor device at a lower cost to suppress occurrence of hump and to prevent a MOSFET characteristic from deteriorating can be provided.

Abstract: A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.

Abstract: Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

Abstract: The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.

Abstract: A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Abstract: A capacitor having a tantalum-contained-dielectric layer is formed by a fabrication method including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a plasma vapor deposition (PVD).

Abstract: A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: There is provided a semiconductor device manufacturing method which comprises the steps of forming a first insulating film over a silicon substrate (semiconductor substrate), forming a lower electrode, a dielectric film, and an upper electrode of a capacitor on the first insulating film, forming a first capacitor protection insulating film for covering at least the dielectric film and the upper electrode, forming a second capacitor protection insulating film, which covers the first capacitor protection insulating film, by a chemical vapor deposition method in a state that a bias voltage is not applied to the silicon substrate, and forming a second insulating film on the second capacitor protection insulating film by the chemical vapor deposition method in a state that the bias voltage is applied to the silicon substrate.

Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.

Abstract: In a semiconductor device having a plurality of memory cells, each of the memory cells includes a floating gate, a control gate, a source and drain, and a silicide layer. The floating gate is formed on a semiconductor substrate of a first conductivity type through a gate insulating film to be insulated from a surrounding portion. The control gate is formed on the floating gate through an ONO film. The source and drain are formed on the semiconductor substrate on two sides of the floating gate and doped with an impurity of a second conductivity type. The silicide layer is formed on a surface of at least one of the drain and source. A method of manufacturing the semiconductor device is also disclosed.

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract: A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

Abstract: The method of manufacturing a non-volatile semiconductor memory device comprises a step of providing a first ion implantation on the principal surface of a silicon substrate in a manner to cover a groove to form a first impurity region on the principal surface. Next, a step of providing a second ion implantation to cover the groove to form a second impurity region on the principal surface that overlaps the first impurity region at the groove and electrically connects the second source/drain region and the third source/drain region by the first impurity region. In short, the impurity region at the groove is formed by a twice ion implantation of the first and second ion implantations.

Abstract: A semiconductor device has an alternating conductivity type layer that improves the tradeoff relation between the ON-resistance and the breakdown voltage and a method of manufacturing such a semiconductor device. The alternating conductivity type layer is formed of n-type drift regions and p-type partition regions alternately arranged with each other. At least the n-type drift regions or p-type partition regions are formed by ion implantation under an acceleration voltage changed continuously. The p-type partition regions or n-type drift regions are formed by epitaxial growth or by diffusing impurities from the surface of a substrate or a layer for the layer.

Abstract: A power metal oxide semiconductor-field-effect-transistor (MOSFET) device using trench technology to achieve a reduced-mask-production process. The power MOSFET device includes a gate signal bus having multiple gate trenches formed using fewer masks than previously required for a similar device. The two-dimensional behavior of the trenches provides an advantageous field-coupling effect that suppresses hot-carrier generation without the need for the commonly used thick layer of silicon dioxide beneath the gate polysilicon. The use of easily controlled silicon trench etching in production of the power MOSFET results in stable, low cost, and high yielding manufacturing.

Abstract: A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.

Abstract: Methods for making integrated circuit devices, such as high density memory devices and memory devices exhibiting dual bits per cell, include forming multiple oxide fences on a semiconductor substrate between multiple polybars. The oxide fences create a hole pre-code pattern that facilitates ion implantation into trenches disposed between the polybars. The holes, or voids, formed by the oxide fences provide greater control of the critical dimension of ion implantation, for example, the critical dimension of the trench sidewalls. Semiconductor devices used in the manufacture of memory devices include the oxide fences during the manufacturing process.

Abstract: A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

Abstract: A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portion of the layer of conductive material is removed according to the mask.

Abstract: A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment.

Abstract: A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches (116) of a workpiece (112). A temporary spacer adjacent gate electrode contacts (132) and pad nitride layer are removed. A spacer material is deposited over exposed portions of the workpiece (112) and over the top and sides of the gate electrode contacts (132). The spacer material is removed from the horizontal surfaces of the DRAM device (100), including the exposed portions of the workpiece (112) and the top of the gate electrode contacts (132). Spacers (144) having sidewalls sloping downwardly away from the gate electrode contacts (132) are left remaining on the gate electrode contact (132) sides, preventing voids from forming during a subsequent array top oxide deposition. Spacers may also be formed adjacent top regions of isolation trenches simultaneously with the formation of spacers (144).

Abstract: According to one disclosed embodiment, a heavily doped subcollector is formed. Subsequently, a collector is fabricated over the heavily-doped subcollectoi, wherein the collector comprises a medium-doped collector layer adjacent to the subcollector and a low-doped collector layer over the medium-doped collector layer. Both the medium-doped collector layer and the low-doped collector layer can comprise gallium-arsenide doped with silicon at between approximately 5×1016 cm−3 and approximately 1×1018 cm−3, and at between approximately 1×1016 cm−3 and approximately 3×1016 cm−3, respectively. Thereafter, a base is grown over the collector, and an emitter is deposited over the base. The collector of the HBT prevents the depletion region from reaching the subcollector without unduly impeding the expansion of the depletion region. As a result, filamentation in the subcollector is prevented, but the HBT's performance remains optimal.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth and a fourth depth so as to counteract a change in band gap in the base between the first depth and the second depth. For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth and fourth depth so as to counteract the change in band gap at approximately the second depth.

Abstract: A high surface area capacitor comprising a double metal layer of an electrode metal and a barrier material deposited on hemispherical grain (HSG) silicon and a high dielectric constant (HDC) material deposited over the double metal layer. An upper cell plate electrode is deposited over the HDC material. The double metal layer preferably comprises one noble metal for the electrode metal and an oxidizable metal for the barrier material. The noble metal alone would normally allow oxygen to diffuse into and oxidize any adhesion layer and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. The barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion. The HSG polysilicon provides a surface roughness that boosts cell capacitance. The HDC material is also used to boost cell capacitance.

Abstract: A method is proposed for mounting a passive component, such as a resistor or a capacitor, over an IC package substrate, such as a BGA (Ball Grid Array) substrate. Conventionally, the mounting of a passive component over a substrate would result in the undesired existence of a gap between the passive component and the substrate, which could lead to such problems as bridged short-circuit, popcorn effect, and dismounting of the passive component during subsequent processes. As a solution to these problems, the proposed method utilizes an electrically-insulative material, such as epoxy resin, to fill up the gap between the passive component and the substrate. Various techniques can be employed to fill the electrically-insulative material into the gap, including dispensing and stencil printing.

Abstract: A method of changing the resistance of a perovskite metal oxide thin film device with a resistance-change-producing pulse includes changing the resistance of the device by varying the duration of a resistance-change-producing pulse.

Abstract: Method and apparatus for marking microelectronic devices, such as bare microelectronic dies and packaged devices, to enhance the identification and automatic handling of wafers, dies and packaged devices. In one embodiment, a microelectronic device comprises a microelectronic die having an integrated circuit, a hidden marking layer superimposed relative to the die, and a cover layer over the hidden marking layer. The hidden marking layer can be applied to a surface of the die and/or a surface of a package encasing at least a portion of the die such that in either situation the hidden marking layer is superimposed relative to the die. In one embodiment, the hidden marking layer is a material that (a) can be removed by a scribing energy (e.g., incinerated or otherwise consumed), and/or (b) is at least partially opaque to an exposure energy. The hidden marking layer can also have a depression defining an identification mark through which at least a portion of the exposure energy can penetrate.

Abstract: A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is uncovered. The substrate is electrochemically etched proceeding from the substrate surface. A porous substrate is formed in a trench-shaped region proceeding from the substrate surface. The trench is formed by removing the porous substrate from the trench-shaped region.

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

Abstract: A new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed in a high temperature process after the trench is filled with an insulative material. The insulative material is provided in a low temperature process.

Abstract: A microelectromechanical system may be enclosed in a hermetic cavity defined by joined, first and second semiconductor structures. The joined structures may be sealed by a solder sealing ring, which extends completely around the cavity. One of the semiconductor structures may have the system formed thereon and an open area may be formed underneath said system. That open area may be formed from the underside of the structure and may be closed by covering with a suitable film in one embodiment.

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.