Abstract: A method of evaluating a PLL built-in circuit includes outputting an applied pattern signal from a test equipment synchronized with a system clock signal received by the test equipment, dividing the applied pattern signal into M/N frequencies by a frequency divider, wherein M and N are positive integers. The method further includes inputting the divided pattern signal into the PLL built-in circuit, inputting an output pattern signal outputted from the PLL built-in circuit into the test equipment and caring the output pattern signal with the applied pattern signal so as to evaluate the PLL built-in circuit. In the above method, M and N are set in a manner that a frequency of the output pattern signal from the PLL built-in circuit is substantially equal to a frequency of the system clock signal.

Abstract: A self-compensation circuit for terminal resistors includes a current mirror, a reference resistor, a comparator and a plurality of terminal resistors. The current mirror provides a first current through the reference resistor to form a first voltage and a second current through an external resistor to form a second voltage. The comparator compares the first voltage and the second voltage and generates an output voltage that is able to be feedback to the control terminal of the reference resistor. The control terminal of each terminal resistor is connected to the output end of the comparator, thus the resistance of each terminal resistor is able to be proportional to the resistance of the external resistor.

Abstract: An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.

Abstract: An output buffer (100) contains a low voltage driver (110), a medium voltage driver (108), and a high voltage driver (106). When an output pad (112) is configured to operate between ground and the medium voltage, the low voltage driver (110) is first used during low-to-high transitions to drive the output pad (112) from ground to an intermediate voltage in a fast manner. After the intermediate voltage is obtained on the output pad (112), a detection circuit (111) will switch output pad control from the low voltage driver (110) to the medium voltage driver (108). The medium voltage driver (108) will drive the output pad (112) from the intermediate voltage to the final logic one output voltage. This two-stage low-to-high driving methodology ensures that there will be less delay time from input (DO) to the output pad (112).

Abstract: A method of forming an output transistor (11) protects the output transistor (11) from overvoltage conditions on an output (13). The body of the output transistor (11) is coupled to the gate of the transistor (11) prior to the high voltage being applied to the output (13).

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an output terminal of the first inverter; a second inverter 11 in which an input terminal is connected to a third node T3; a sixth node T6 connected to an output terminal of the second inverter; a third inverter 12 in which an input terminal is connected to a fourth node T4; a first transfer gate 20 in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T4, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate 21 in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T4; and a fifth node T5 connected to an output t

Abstract: A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Abstract: A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A depletion type n-channel MOS transistor (hereinafter referred to as “D-type NMOS”) as a MOS transistor of a SOI structure is disposed between a plus side power supply terminal of a CMOS circuit and a plus side terminal of a power supply unit so as to connect a source thereof to the pulse side power supply terminal of the CMOS circuit, to connect a drain thereof to the plus side terminal of the power supply unit, and to input to a gate thereof a voltage such that even if the voltage of the plus side terminal of the power supply unit exceeds the upper limit of the operation voltage of the CMOS circuit, the source of the D-type NMOS is equal to or lower than the upper limit of the operation voltage of the CMOS circuit, and the same voltage as the voltage of the plus side terminal of the power supply means when the voltage of the plus side terminal of the power supply means is the vicinity of the lower limit of the operation voltage of the CMOS circuit.

Abstract: A differential signal reception device and method for supporting variable threshold levels. The device flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltage. The device further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply.

Abstract: Each of a plurality of clock generation units has a clock driver which generates a clock signal in accordance with a reference clock, and a supplying unit which supplies the reference clock to the clock driver. The supplying unit supplies the clock driver, in a case where another clock generation unit is already attached to a clock signal generation device at a time the clock generation unit to which the supplying unit belongs is attached to the clock signal generation device, with a clock signal generated by the clock driver of the another clock generation unit as the reference clock during a predetermined time. The clock driver makes a clock signal to be generated follow the supplied reference clock.

Abstract: Trimming methods and apparatus are disclosed for selectively removing resistance between first and second nodes in an electrical device, including trim circuits comprising a resistor and a diode formed in the resistor body having a conductive portion which may be selectively melted to short the resistor. A multi-bit trim cell is disclosed having trim cells individually comprising a resistor with a diode formed in the resistor body for selectively shorting the resistor, and a fuse for selectively disconnecting the diode from a trim pad.

Abstract: An output stage and method for a charge pump circuit which substantially reduces the degradation of the output voltage. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A capacitor is connected between a second clock signal and the drain of the second NMOS transistor. Another capacitor is connected between a first clock signal and an intermediate node. The key part of the invention is a diode pair connected anode of one to the cathode of the other and inserted between the intermediate node and the drain of the first NMOS transistor.

Abstract: A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for voltage regulation. Regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive device is provided to vary the inductance in the output current path. The orthogonal inductive device is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.

Abstract: A capacitive element includes two or more voltage-variable capacitors (varactors). The varactors are configured so that they are coupled in series with respect to an applied AC signal and are coupled in parallel with respect to an applied DC bias voltage. The effective capacitance of the overall capacitive element can be tuned by varying the DC bias voltage.

Abstract: An amplifier circuit with offset compensation is particularly suited for a Hall element. In addition to the useful signal demodulation that is normally present and connected downstream of an amplifier, an error signal demodulator provides an error signal demodulation. The measured signals that are tapped off at the Hall sensor are coupled out at the input or output of the amplifier, and a demodulated error signal is fed back to the input of the amplifier. This makes it possible to reduce the drive range of the amplifier. The amplifier circuit is suitable in particular for Hall sensors that are operated in chopped mode.

Abstract: To provide a small-sized high frequency power amplifier for preventing oscillation by a small number of switching circuits and outputting high power and low power with high efficiencies, a high frequency power amplifier module and a portable telephone, the high frequency power amplifier is constituted by an amplifying circuit A and an amplifying circuit B connected in parallel, a size of a transistor at an output stage of the amplifying circuit B is made to be equal to or smaller than ¼ of a size of a transistor of an output stage of the amplifying circuit A and a switching circuit is connected between a signal line forward from the output stage of the amplifying circuit A and a ground terminal.

Abstract: An amplifier distortion reduction system detects a plurality of amplitudes corresponding in time within a frequency band of operation. In response to at least one of the plurality of amplitudes, adjustments can be made to components within the frequency band of operation, enabling the amplifier distortion reduction system to adapt to changing operating conditions. In a feed forward embodiment having a carrier cancellation loop and IMD cancellation or distortion cancellation loop, the output of the carrier cancellation loop can be monitored and equalizer adjustments provided to reduce the amplitude of the carrier signal(s) equally over the frequency band of operation. The output of the IMD cancellation loop can be monitored and equalizer adjustments provided to reduce the IMD components equally over the frequency band of operation. Thus, processing circuitry can monitor amplitudes corresponding in time over the frequency band of operation and provide improved performance over the frequency band.

Abstract: A balanced current converter with multiple PWM converter channels has an error amplifier, a main converter channel and at least one parallel converter channel. The converter provides a DC power output and feeds back an average output voltage signal. The error amplifier compares a reference voltage signal and the average output voltage signal to generate an error signal. The main converter channel outputs a main channel current signal and a main channel power output according to the error signal. The parallel converter channel compares the main channel current signal and the respective parallel channel current signal to generate a first deviation signal, then compares the first deviation signal and the error signal to generate a second deviation signal. The parallel converter channel provides and measures a respective parallel channel power output to feed back the respective parallel channel current signal.

Abstract: A digitally controllable nonlinear pre-equalizer system receiving an input signal and generating an output signal, the system including a splitter for dividing the input signal into a first signal path and a second signal path, an attenuator and a time delay element in the first signal path, the attenuator and the time delay element operable to generate a linear signal, a mixer and a vector modulator in the second signal path, the mixer being responsive to a signal from a digital to analog converter coupled to a processor chip providing a digital signal to the digital to analog converter, the mixer and vector modulator operable to generate a nonlinear signal, and a summer for summing the linear signal and the nonlinear signal to generate the output signal.

Abstract: A combined multiplexer and switched gain circuit (250) that selectively multiplexes differential analog signals from a primary channel (20) and a diversity channel (22) in a diversity receiver system (10) to a single output. The circuit (250) is based on a current mode logic design where a plurality of separate conduction paths (278-284) are provided between a voltage line (266) and a current source (268). An output line (264) of the circuit (250) is coupled to each conduction path (278-284) so that the differential analog signals from the primary channel (20) and the diversity channel (22) can be selectively outputted to the circuit (250). Each conduction path (278-284) includes a gain device, such as degenerative resistor, that provides signal gain or no signal gain for that conduction path (278-284). Control signals are selectively applied to switching devices (310-324) and each conduction path (278-284) so that the conduction path (278-284) can be independently selected to provide the multiplexing.

Abstract: The amplifier circuit includes differential amplifier circuits (3 to 4); a peak detector circuit (7) for detecting a peak value of an output voltage of a differential amplifier circuit 4 of the last stage; an offset compensation voltage generator circuit (8) for generating an offset compensation voltage for offset compensation on the basis of a detection result of the peak detector circuit (7); and an offset output limiter circuit (9) for limiting the offset compensation voltage generated by the offset compensation voltage generator circuit (8) into a predetermined range and feeding back the limited offset compensation voltage to a differential amplifier circuit (3) of the first stage.

Abstract: A distributed amplifier consistent with certain embodiments of the present invention has a plurality of amplifier sections 1 through N (302, 306) with each amplifier section having an input and an output. A plurality of N input transmission line sections are connected in series, with inputs of the 1 through N amplifier sections interconnected at their inputs along the series of input transmission line sections. A plurality of N output transmission line sections are also connected in series, with outputs of the 1 through N amplifier sections interconnected at their outputs along the series of input transmission line sections. A load (160) can be driven by an output at the Nth amplifier section (108). A high-pass filter (310) connects a dummy load (150) to the output of the first amplifier section (302). The input and output transmission line sections can, for example, be lumped element T sections and the high-pass filter can be made of a lumped element half section.

Abstract: A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

Abstract: A method and apparatus are disclosed for tuning a voltage controlled oscillator (VCO) having two point modulation used in a phase lock loop modulation system. A loop correction voltage applied to a first modulation input of the VCO when a first modulation signal, e.g., +1, is applied to a second modulation input of the VCO is compared to a loop correction voltage applied to the first modulation input when a second modulation signal, e.g., −1, is applied to the second modulation input of the VCO. The comparison produces a correction signal used to adjust the signal level of at least one of the signals, e.g., the second modulation input signal, applied to the two modulation inputs of the VCO.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: Systems and methods are described for a band switchable voltage controlled oscillator. A method comprises: operating said voltage controlled oscillator in a first frequency band by switching a first capacitive circuit having a capacitance that varies with a tuning voltage; and operating said voltage controlled oscillator in a second frequency band by switching a second capacitive circuit having a capacitance that does not vary with the tuning voltage.

Abstract: An oscillator is provided that can be flexibly retrofitted to become usable for a wide range of applications, that is compatible with different users'requests, and that enables a user to design a high-frequency unit using the oscillator without concerns. The oscillator includes a SAW resonator and an oscillation unit provided in the form of an integrated circuit. The SAW resonator and oscillation unit are encapsulated in the same package and then sealed. The whole oscillator is thus provided in the form of a module. The oscillation circuit includes a first adjustment terminal with which a current flowing through a current source is adjusted externally. A resistor offering a desired resistance is connected between the first adjustment terminal and a ground terminal, whereby a negative resistance can be adjusted. Moreover, a second adjustment terminal with which a current flowing through a current source in an amplification circuit is included.

Abstract: An amplitude modulated source signal (102) is received, where this signal has a source frequency bandwidth and a source envelope. A dummy envelope is computed that would yield a constant if the dummy envelope and source envelope were to be combined. An amplitude modulated dummy signal (105) is generated, where this dummy signal exhibits the computed, dummy signal envelope and has a prescribed frequency bandwidth different than the source frequency bandwidth. The source and dummy signals are added to form a combined signal (113), which is directed to an input (114a) of a nonlinear circuit (114), that is, one that exhibits amplitude dependent nonlinearity. Signals of the dummy frequency bandwidth and any intermodulation products are filtered from the output, thereby providing a linearized output (118) corresponding to the original, source signal.

Abstract: A non-reciprocal circuit element has matching capacitors, each disposed between an I/O port and ground. Each matching capacitor has a dielectric substrate and first buffer layers, second buffer layers, and main lead layers formed on both surfaces of the dielectric substrate by dry thin-film deposition, in that order. For example, a Ni—Cr alloy, a Ni—Cu alloy, and Ag are used for the first buffer layers, the second buffer layers, and the main lead layers, respectively. The matching capacitors can solve the problems arising from the electrodes of known capacitors, and thus the non-reciprocal circuit element and communication devices using the capacitors can have excellent electrical characteristics.

Abstract: The present invention relates to a concurrent multi-band amplifiers and to a monolithic, concurrent multi-band low noise amplifier (LNA). The inventive LNA includes a three-terminal active device, such as a transistor with a characteristic transconductance, gm, disposed on a semiconductor substrate. The active device has a control input terminal, an output terminal, and a current source terminal. The amplifier also includes an input impedance matching network system, Zin, and an output load network. Zin simultaneously and independently matches the frequency-dependent input impedance of the three-terminal active device to a predetermined characteristic impedance at two or more discrete frequency bands. The output load network simultaneously provides a voltage gain, Av, to an input signal at the amplifier input at each of the two or more discrete frequency bands.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: An ultra wideband, frequency dependent attenuator apparatus for providing a loss which can be matched with a physically longer, given delay line, but yet which provides a much shorter time delay than the physically longer, given delay line with constant group delay. The apparatus is formed by an ordinary microstrip transmission line placed in series with an engineered lossy microstrip transmission line, with both transmission lines being placed on a substrate to effectively form a hybrid microstrip transmission line. The lossy transmission line includes resistive material placed along the opposing longitudinal edges thereof. In one embodiment, spaced apart metal tracks are formed along each strip of resistive material to provide the lossy microstrip transmission line with a desired loss characteristic.

Abstract: A switched loop RF radiator circuit, comprising a radiator element, a RF input/output (I/O) port, and a balun coupled between the radiator element and the (I/O) port. The balun includes a 180° switched loop circuit having transmission line legs coupled to a balun transition to provide a selectable phase shift, and a microelectromechanically machined (MEM) switch Many radiator circuits can be deployed in an electronically scanned antenna array.

Abstract: A miniaturized phase shifter and a multi-bit phase shifter are provided, in which filters are constructed using capacitors at FET pinch-off and pass phase can be shifted by turning the FET on and off, the phase shifter including: a first FET having a drain electrode connected to an input terminal and a source electrode connected to an output terminal; a second FET, in which one of a drain electrode and a source electrode thereof is connected to the source electrode of the first FET and the other is connected to ground via a first inductor; and a third FET, in which one of a drain electrode and a source electrode thereof is connected to the drain electrode of the first FET and the other is connected to ground via a second inductor.

Abstract: An electrical signal filter including elongate upper and lower filter housing members abutted along a longitudinal seam between the housing members. The housing members hold at least one circuit board. A ground post is formed integrally with the lower filter housing member and is secured to the circuit board without solder. First and second mechanical engagement members are used to rotationally secure end caps to the housing members without solder. As a result, assembly of the filter components can be accomplished without the need for expensive soldering operations, thus reducing the overall manufacturing cost of the filter.

Abstract: An electronic filter assembly of the type that includes a female terminal cap having a fitting portion and containing a terminal passage through the fitting portion, and a collet assembly secured in and substantially closing the terminal passage of the female terminal cap. The collet assembly comprises an insulator, a collet terminal, and a seal. The insulator is made from a single piece of insulator material, containing a bore therethrough. The collet terminal extends through the bore of the insulator. The seal is located inside the terminal passage of the female terminal cap, between the collet terminal and the female terminal cap.

Abstract: An electronic device includes a housing for accommodating a carrier substrate. An electronic module and a conductor structure for making electrical connection with the electronic module are fitted on the carrier substrate. A filter device for improving the electromagnetic sensitivity is arranged in the housing. The filter device is formed by an electrical and/or capacitive connection of a first conductor surface of the conductor structure to an external first potential and by an electrical and/or capacitive connection of a second conductor surface of the conductor structure to a second electrical potential, the first conductor surface and the second conductor surface being arranged approximately opposite one another.

Abstract: A surface acoustic wave filter has a piezoelectric substrate; at least an input IDT electrod arranged on a piezoelectric substrate; and at least an output IDT electrod arranged on the piezoelectric substrate. A pitch of electrode fingers of the input IDT electrode and a pitch of electrode fingers of the output IDT electrode are different from each other.

Abstract: A evanescent resonator device includes a short-circuited evanescent waveguide and loading capacitor. The evanescent waveguide of the resonator includes a single length of evanescent transmission line terminated in short circuit, a first support substrate having a predetermined dielectric constant, the first support substrate having a top surface and a bottom surface; a dielectrically loaded feed network including: (a) a second substrate arranged on the top surface of the first support substrate, the second substrate having a predetermined dielectric constant that is higher than the first support substrate; and (b) a metal strip arranged on an upper surface of the second substrate, so that the second substrate is arranged between the first support substrate and the second substrate. A ground plane is arranged on the bottom surface of the first support substrate, the support substrate includes a hollow metalized center area being open on an upper end closest to the second substrate.

Abstract: A multi-layer substrate comprises a first dielectric layer, a coplanar waveguide line formed on a first surface of the first dielectric layer, the coplanar waveguide line including a signal conductor and a pair of ground conductor layers positioned at opposite sides of the signal conductor, separately from the signal conductor, and a second dielectric layer formed to cover the coplanar waveguide line and the first dielectric layer and having an opening positioned at least on the signal conductor of the coplanar waveguide line. A thickness of the first dielectric layer is smaller than the value of c/{4f·(∈1−1)½}, where c is velocity of light, f is a frequency of a signal propagating in the signal line, and ∈1 is a dielectric constant of the first dielectric layer.

Abstract: A switch relay with a switching status display is described, in which a display element is in operative connection with a switch contact of the switch relay and displays the switch positions in a clearly recognizable manner. The display element enlarges the display stroke so that contact movement is more readily visible. The principle is based on the elongation of a pointer of the flexing line of, for example, a constructed film hinge. As a result of the display element being constructed as a synthetic part low in mass, the contact dynamics are reduced by only a small extent.

Abstract: The device according to the invention comprises an armature mechanically connected to an actuating rod of the contacts of the apparatus and movable in a support block between a rest position and an active position, at least one permanent magnet and at least one winding. The magnet(s) has(have) the function of holding the armature in the rest position whereas the winding(s) has(have) the function of generating, when an opening order occurs due for example to a voltage surge or other (or respectively a closing order), a magnetic field designed to counteract the force of the magnets so as to move the armature to the active position resulting in separation of the contacts (or respectively closing of the contacts). This device is characterized in that the above-mentioned armature is mounted movable in rotation between two stops arranged in the support, said stops respectively bounding the two above-mentioned positions.

Abstract: An electromagnetic actuator includes a stationary member, a movable member magnetically coupled with the stationary member with a gap therebetween, and a support member for displaceably supporting the movable member relative to the stationary member. Both the stationary member and the movable member have a core section carrying a coil wound around its periphery. As the coil of the stationary member and that of the movable member are energized with electric current, the movable member is either attracted toward or repulsed from the stationary member. The electromagnetic actuator can be used for an optical scanner by providing a mirror and a lens on the movable member.