Abstract: An electronic equipment has an enclosure, a backplane board, a connector, a child board, a connection plate on the bottom edge of the child board mating with the connector, a guide, a rack gear, and a pinion gear. The guide moves within a child board housing part inside the enclosure between an upper and a lower position along a substantially vertical direction. At the upper position, the guide slidably mates with the child board and guides the child board to a temporary attachment position substantially vertically, and movement from the upper to the lower position causes the child board at the temporary attachment position to move substantially vertically to a fully attached position. The rack gear fixed relative to the guide, and the rotating shaft has a pinion gear meshing with the rack gear, and is supported so as to rotate freely relative to the enclosure.

Abstract: An integrated shield wrap suitable for use in an electronic device including electronic circuitry. The integrated shield wrap includes an insulator section composed of an electrically insulative material, as well as a shield section joined to the insulator section and composed of an electrically conductive material. The integrated shield wrap can be configured as necessary to suit a particular application and, in general, serves to electrically insulate the electronic circuitry from other circuitry and components within the electronic device while simultaneously implementing a shielding functionality that permits management of electromagnetic emissions from some or all of the electronic circuitry.

Abstract: In a shielding scheme for circuit boards, conductive shields have contoured mating surfaces that become flat, or co-planar, at the circuit board-shield interface when the shields are fastened to opposite sides of the circuit board. The contoured mating surfaces compensate for deformation of the shields resulting from the fastening so that uniform mechanical pressure is applied at all designated points along the circuit board-shield interface even though fastening points are intermittently spaced throughout the shields. When compressible conductive gaskets are optionally interposed between the shields and the circuit board, stops are included to accommodate for the thickness of the gasket. High signal isolation is achieved without correspondingly high contact area on the circuit board and without closely-spaced fastening points. Low assembly time and manufacturing cost results for shielded circuit board assemblies incorporating the shielding scheme.

Abstract: A DC—DC voltage converter has a controller, two switches, a transformer and two rectifying diodes. The transformer has a first winding, a second winding and a center tap. Input voltage is connected between the center tap and ground. An anode of each diode is connected to the outer ends of the two windings and the cathodes of the two diodes are connected together to provide a positive output with respect to ground. Each switch is connected between an outer end of one winding and ground. The controller generates control signals to turn the switches on and off for limited periods of time in phase opposition to alternately connect the outer ends of the first and second winding to ground to cause current to flow alternatively in one of the windings and induce a voltage in the other winding that is additive to the input voltage, thereby providing an output voltage greater than the input voltage.

Abstract: A power supply comprising a flyback converter and a controller is disclosed. The flyback converter drives a load when electrically coupled to an alternating current power source. The controller controls a soft switching during each switching time period of the flyback converter. Upon an initial switching time period, the controller determines each acceptable switching frequency for the subsequent switching time periods and selects one of the acceptable switching frequencies for soft switching the flyback converter over one or more switching time periods during a constant load.

Abstract: A PWM controller having a saw-limiter for power limit without input voltage sensing. The saw-limiter has an adder, a reference voltage, a scaler and a saw-tooth signal that is generated by the PWM oscillator. The saw-limiter produces a saw-limited voltage. The PWM controller will turn off its output when the current-sense input signal of the PWM controller is higher than the saw-limited voltage. The saw-limited voltage is equal to the reference voltage while a PWM switching period starts. After that, the amplitude of the saw-limited voltage will gradually increase until it reaches its maximum voltage. Subsequently, a saw-tooth like waveform is generated for the saw-limited voltage. The slope of the current-sense input signal is proportional to the line voltage. Therefore, a higher line voltage creates a sharp slope for the current-sense input signal, which will be restricted by a lower saw-limited voltage and produces a shorter PWM signal.

Abstract: There is intended to provide an overvoltage-protective device capable of protecting a power system from overvoltage not destructively without using a fuse. An alarm signal from an MOS transistor Tr3, a structural element of a DC/DC converter 21, is inputted to a switching circuit 55, a structural element of the AC/DC converter 11. In case an alarm signal keeps high-level potential without indicating overvoltage-state, the switching circuit 55 connects a output current detecting circuit 53 having the smaller gain G1 to an output voltage detecting circuit 50 as well as a feedback circuit 51A, thereby to set large output-power-supply capability. In case an alarm signal inverses to low-level potential indicating overvoltage-state, the switching circuit 55 connects a output current detecting circuit 54 having the larger gain G2 to the output voltage detecting circuit 50 as well as the feedback circuit 51A, thereby to set small output-power-supply capability.

Abstract: A power converter device using synchronous rectifiers and method for controlling operation thereof are provided. A first synchronous rectifier is coupled to the secondary transformer winding to pass a voltage induced at the secondary winding in response to an input voltage supplied to the primary transformer winding during an on-state of a main power switch. A first drive circuit is coupled to the gate terminal of the first synchronous rectifier to selectively activate and deactivate the first rectifier in correspondence with the respective on and off states of the main power switch based on a gate voltage supplied by the first drive circuit, with at least one circuit parameter being selected in the first drive circuit for maintaining the gate voltage within a predefined range regardless of variation in the level of the input voltage.

Abstract: A switching voltage converter in half bridge topology includes a control circuit for achieving a constant locking time for two power switches to switch between a TOP position and BOT position. The TOP switch is realized by one or more parallel-switched n-channel transistors and the BOT switch 3 is realized by one or more parallel-switched p-channel transistors. Both of the power switches are controlled by a gate driver. The reference potential of the gate driver is at the potential of the output signal Uout of the half bridge. The driver is controlled by a switching-signal producing unit at the same reference potential as the driver 1, whereby unit and driver can be directly connected to each other.

Abstract: Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.

Abstract: A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and a ground conection, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is defined by a memory cell transistor having its terminals shorted together.

Abstract: A digital magnetic memory cell device for read and/or write operations having a first and a second magnetic layer, the magnetization of which is oriented parallel or antiparallel for the storage of digital information. An intermediate layer is disposed between the first and second magnetic layers. A pair of intersecting conductors are disposed to switch the magnetization of at least one of the two magnetic layers in a memory cell defined by the intersection thereof when a read or a write current is applied thereto. The conductors intersect at an angle &bgr; so that current pulses having a pulse duration <10 ns make it possible to switch the magnetization of a cell fully and securely from a parallel to an antiparallel orientation and vice versa.

Abstract: A nonvolatile storage device and method of operation capable of preventing opens in a word line and/or bit line that may result from electromigration is disclosed. A nonvolatile storage device according to an embodiment may include a number of magnetic resistance elements provided at intersections of word lines and bit lines, a word line control circuit for selecting one word line and supplying a write current thereto in a write operation, and a bit line control circuit for selecting one bit line and supplying a write current thereto. A word line control circuit can provide a bidirectional write current to a word line.

Abstract: A ferromagnetic thin-film based digital memory including a memory cell having a bit structure with a nonmagnetic intermediate layer having a memory film of an anisotropic ferromagnetic material on each of the opposite side major surfaces of an intermediate layer with there being a film thickness difference there of at least five percent, or a film effective anisotropy field difference because of different ferromagnetic materials used therefor, or both. An electrically insulative intermediate layer is provided on the memory film across from one intermediate layer major surface, this insulative intermediate layer having a major surface on a side opposite the memory film on which a magnetization reference layer is provided having a relatively fixed magnetization direction.

Abstract: An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.

Abstract: P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic hole-electron pairs to be generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Various circuits incorporating such fuse or antifuse elements are also disclosed.

Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated.

Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.

Abstract: A compensation circuit for transistor threshold voltages in integrated circuits is described. The compensation circuit includes a transistor, current source, and gate reference voltage supply. The transistor is biased to provide a well bias voltage, or backgate voltage VBG, which is coupled to transistors provided on a common integrated circuit. This compensation circuit eliminates the need for gate biasing capacitors, and provides flexibility in setting threshold voltages in low voltage circuits. The gate reference voltage and current source are established to provide a desired backgate voltage VBG. Compensation circuits are described for both n-channel and p-channel transistors. A memory device is described which includes compensation circuits for controlling threshold voltages of transistors provided therein.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: A method for recognizing a defective memory cell in a memory having a plurality of memory cells includes directly comparing predetermined properties of the memory cells to one another. Predetermined identical information is read into each memory cell of the plurality of memory cells, and then the information stored in the plurality of memory cells is read out. For each one of the plurality of memory cells a strength of a read-out signal is determined, and the memory cells are sorted depending on the strength of the respective read-out signal.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A sense amplifier section of a semiconductor memory device includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.

Abstract: An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A semiconductor integrated circuit (100) that may determine whether or not a power supply voltage has dropped to a level that data integrity in a RAM portion (15) may be lost has been disclosed. Semiconductor integrated circuit (100) may include a power on clear (POC) circuit (1), a low voltage detecting circuit (2), a RAM data destruction preventing block (3), a RAM portion (15), and a combination circuit (4). POC circuit (1) may detect when a power supply potential is below a predetermined voltage and provide a reset signal to RAM data destruction preventing block (3). RAM data destruction preventing block (3) may prevent access to memory cells (20) in RAM portion (15) in response to the reset signal. Low voltage detecting circuit (2) may determine if the power supply potential may have dropped below a data holding voltage. In this way, data may only be rewritten to RAM portion (15) after a reset operation if data integrity may be lost.

Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.

Abstract: A serial access memory low in current consumption, capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays each having memory cells electrically connected to corresponding bit lines, signal lines provided in common between the memory arrays and electrically connected to the corresponding bit lines through first transfer circuits, write registers electrically connected to the corresponding signal lines through a second transfer circuit, a write bus electrically connected to the write registers through a third transfer circuit, an input circuit electrically connected to the write bus, read registers electrically connected to the corresponding signal lines through a fourth transfer circuit, a read bus electrically connected to the read registers through a fifth transfer circuit, and an input circuit electrically connected to the read bus.

Abstract: A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.

Abstract: A DRAM includes a sense amplifier which is activated when first and second nodes are set respectively to L and H levels to amplify a potential difference between paired bit lines. The DRAM further includes a write column select gate which is activated when the first node is set to L level to write a data signal on a pair of write data lines into a corresponding sense amplifier when a corresponding write column select line is set to H level. In this way, the data signal can be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which can enhance the random access rate.

Abstract: Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

Abstract: A two-way ultrasonic positioning and navigation system and method involve a plurality of objects each capable of transmitting and receiving ultrasonic signals. A first object transmits an initiating ultrasonic signal and identifies a second object for responding to the initiating ultrasonic signal. The second object transmits a responding ultrasonic signal after a predetermined time delay from receiving the initiating ultrasonic signal. The first objectives the responding ultrasonic signal, and determines a distance between the first object and the second object based on a time period starting at the transmission of the initiating ultrasonic signal and ending at the reception of the responding ultrasonic signal, and on knowledge about the predetermined time delay and other known in advance time delays.

Abstract: A seismic data acquisition method and system are shown. The method acquires seismic data using an acoustic source capable of producing a seismic signal and an acoustic receiver in an area having periodic acoustic interference. The method includes sensing a time window in which the periodic acoustic interference at the acoustic receiver is substantially attenuated, and adjusting the acoustic source's discharge time so a desired portion f a seismic signal produced by the acoustic source arrives at the acoustic receiver within a subsequent time window.

Abstract: A method for analyzing and classifying the morphology of seismic objects extracted from a 3D seismic data volume. Any technique may be used to extract the seismic objects from the 3D seismic data volume. According to the inventive method, one or more morphologic parameters are selected for use in classifying the morphology of the selected seismic objects. Geometric analyses are then performed on each seismic object to determine geometric statistics corresponding to the selected morphologic parameters. The results of these geometric analyses are used to classify the morphology of the seismic objects according to the selected morphologic parameters.

Abstract: An acoustic device that places existing components in a damping pattern after transmitting an acoustic signal. In one embodiment, the device comprises a transistor bridge and an acoustic transducer. The transistor bridge is coupled between two predetermined voltages having a voltage difference, and the acoustic transducer is coupled between the arms of the transistor bridge. The transistor bridge enters a damping configuration after applying an excitation pattern to the acoustic transducer. In the damping configuration, the input terminals of the transistor bridge are preferably grounded. In applying the excitation pattern, the transistor bridge preferably applies the voltage difference to the acoustic transducer in alternate polarities. In a preferred embodiment, the acoustic transducer includes a transformer having a primary winding coupled between the arms of the transistor bridge, and further includes a piezoelectric crystal coupled to a secondary winding of the transformer.

Abstract: The present invention relates to a system for collecting ocean turbulence data without interference from the hydrodynamic effects of the vehicle. The ocean turbulence data collection system comprises an underwater vehicle, such as an unmanned underwater vehicle, at least one sensor for collecting the ocean turbulence data, and a stinger arrangement mounted to the nose portion of the vehicle for positioning the at least one sensor sufficiently forward of the nose portion of the vehicle to avoid interference from the hydrodynamic effects of the vehicle. The collection system is also provided with at least one accelerometer for compensating for motion not induced by turbulence.

Abstract: Disclosed is an automotive CD player/receiver with an integrated digital recorder that improves over conventional digital audio playback devices commonly found in automobiles and the like. The present invention improves;over conventional car audio technology by providing an otherwise conventional CD player for automotive use with a built-in magnetic media hard drive of a capacity sufficient to store the music of several CDs. By storing a variety of chosen individual songs or entire CDs on hard drive they are ready for instant playback, eliminating the need to carry several CDs and their cases, while still allowing the users to have their favorite songs at their fingertips.

Abstract: While a magneto-optical recording medium is irradiated with a laser beam, the medium is rotated relative to the beam at a controlled speed in such a manner that a high temperature region of a heat spot produced on the basis of the light intensity distribution of the beam is formed outside the associated light spot. A magnetic field source includes a magnetic field generator which is narrow in the direction along the track of the medium. The field source is positioned with the field generator at the heat center outside the light spot to apply a narrow recording magnetic field to the high temperature region. This forms a recording magnetic domain in the high temperature region. The magnetic domain is rectangular and narrow in the direction along the track. Rectangular recording magnetic domains adjoining in the direction along the track hardly interfere with each other even if they are closely spaced. This results in high density recording.

Abstract: A light-pickup device has a constitution in which a microcomputer executes control for applying offset voltage to a focus error signal by changing over connection of an FE offset circuit when a servo-processor kicks focus drive voltage for acceleration in order to change over information recording layers of an optical disk having two information recording layers on a plane thereof. Then, a signal output level at a zone in which no focus error signal is occurred, does not coincide with focus zero cross. Owing to this constitution, the servo-processor detects focus zero cross point of the focus error signal even in a simple circuit structure.

Abstract: A tracking controller capable of conducting a correct tracking control even if a recording track is formed with a narrow track pitch on a recording disk. The tracking controller calculates an error value between a read signal read from a recording track intended for reading and a predetermined value, a first coefficient from a correlation between a read signal read from a recording track adjacent to the recording track intended for reading on the inner peripheral side of the disk and the error value, and a second coefficient from a correlation between a read signal read a recording track adjacent to the recording track intended for reading on the outer peripheral side of the disk and the error value. A difference between the first and second coefficients is calculated as a tracking offset which is subtracted from a tracking error to correct a tracking offset.

Abstract: A focus controller for focusing a light beam and positioning the focused light beam onto a signal recording layer of a signal recording media is disclosed. The controller comprises a light beam focusing means having a numerical aperture of 0.6 or more; a focus controlling means for positioning the light beam focused by the light beam focusing means onto the signal recording layer of the recording media; and an offset adjusting means for adjusting an offset between the focused light beam positioned by the focus controlling means and the signal recording layer of the recording media.

Abstract: An apparatus for managing defects and recording and/or reproducing real time data for a recording medium. The recording and/or reproducing apparatus stores information representing use or non-use of linear replacement defect management in which a defective area on the recording medium is replaced with the spare area, in order to record real time data on the recording medium. While maintaining compatibility between the defect managing method and a defect managing method based on a current DVD-RAM standard, i.e., while allowing a report of the fact that there are blocks which have not been linearly replaced, linear replacement is not performed when real time data is recorded. Thus, real time data can be recorded and reproduced.

Abstract: An object of the present invention is achieved by a security medium creating method for providing a recording medium with security, the method including a medium defect information acquiring step of acquiring medium defect information concerning a medium defect of a first recording medium including recording data requiring security, a medium defect information recording step of recording the foregoing medium defect information acquired by the foregoing medium defect information acquiring step on a second recording medium, and a false defect information recording step of recording false medium defect information in a predetermined defect information recording area in which the foregoing medium defect information of the foregoing first recording medium is recorded so as to provide the security, wherein an access to the foregoing first recording medium is made impossible by the foregoing false defect information recording step.

Abstract: The present invention relates to a method for identifying a data area D,E or D,G, reserved in accordance with a first specification, as useful data area G in accordance with a second specification.

Abstract: On an optical disk medium according to the present invention, address information is recorded along a wobbling track groove 2. The track groove 2 is made up of a plurality of unit sections 22, 23. Each of these unit sections 22, 23 has side faces that are displaced periodically in a disk radial direction. This displacement oscillates at a single period in a tracking direction. However, the displacement pattern differs depending on “each bit of address information (subdivided information)” allocated to each of the unit sections 22, 23.