Abstract: Isolated extracellular matrix-binding proteins, designated ClfB, SdrC, SdrD and SdrE, and their corresponding amino acid and nucleic acid sequences and motifs are described. The proteins, peptides, fragments thereof or antigenic portions thereof are useful for the prevention, inhibition, treatment and diagnosis of S. aureus infection and as scientific research tools. Further, antibodies or antibody fragments to the proteins, peptides, fragments thereof or antigenic portions thereof are also useful for the prevention, inhibition, treatment and diagnosis of S. aureus infection. In particular, the proteins or antibodies thereof may be administered to wounds or used to coat biomaterials to act as blocking agents to prevent or inhibit the binding of S. aureus to wounds or biomaterials. ClfB is a cell-wall associated protein having a predicted molecular weight of approximately 88 kDa and an apparent molecular weight of approximately 124 kDa, which binds both soluble and immobilized fibrinogen.

Abstract: A human nucleic acid, PD2, its encoded protein and antibodies immunologically specific thereto are disclosed herein. The expression of the disclosed PD2 gene plays a key role in the regulation of differentiation and in the maintenance of the neoplastic state. The PD2 gene and its encoded protein represent valuable therapeutic targets in the differential diagnosis and therapy of pancreatic adenocarcinomas.

Abstract: Compositions and methods for the therapy and diagnosis of cancer, particularly breast cancer, are disclosed. Illustrative compositions comprise one or more breast tumor polypeptides, immunogenic portions thereof, polynucleotides that encode such polypeptides, antigen presenting cell that expresses such polypeptides, and T cells that are specific for cells expressing such polypeptides. The disclosed compositions are useful, for example, in the diagnosis, prevention and/or treatment of diseases, particularly breast cancer.

Abstract: Stable clones of neural stem cells (NSCs) have been isolated from the human fetal telencephalon. In vitro, these self-renewing clones (affirmed by retroviral insertion site) can spontaneously give rise to all 3 fundamental neural cell types (neurons, oligodendrocytes, astrocytes). Following transplantation into germinal zones of the developing newborn mouse brain, they, like their rodent counterparts, can participate in aspects of normal development, including migration along well-established migratory pathways to disseminated CNS regions, differentiation into multiple developmentally- and regionally-appropriate cell types in response to microenvironmental cues, and non-disruptive, non-tumorigenic interspersion with host progenitors and their progeny. Readily genetically engineered prior to transplantation, human NSCs are capable of expressing foreign transgenes in vivo in these disseminated locations.

Abstract: A process of parthenogenic activation of mammalian oocytes which includes increasing intercellular levels of divalent cations in the oocyte; and reducing phosphorylation of cellular proteins in the oocyte. One method of accomplishing this is by introducing Ca2+free cation, such as ionomycin, to the oocyte and then preventing phosphorylation of the cellular proteins within the oocyte by adding a serine-threonine kinase inhibitor, such as 6-dimethylaminopurine (DMAP).

Abstract: An assembly for promoting the growth of plant tissues that includes a plurality of plates each defining an array of wells wherein each of the wells contains a tissue sample. Support for the plates is provided by a rack having a plurality of vertically stacked shelves that may include one or more register depressions that urge the plates into predetermined positions. Light for the tissue samples is provided by a plurality of light-emitting diode arrays each mounted on a circuit board. Each circuit board is supported by a respective card edge connector of the rack so that the light-emitting diodes are in proximity to the plates supported on one of the shelves therebelow. Preferably, the light-emitting diode array corresponds to the well array supported in the registered position on the shelf therebelow so that each light-emitting diode is centered above a respective one of the wells.

Abstract: An Agent for the removal of turbidity and biological samples including 0.5-10 mM Phenol, 0.5-15% polyoxyethylated triglyceride and at least one non-ionic tenside in a range of 0.5-15% capable of dissolving the polyoxyethylated triglyceride.

Abstract: The present invention is a method and an apparatus to provide a dynamic matrix system for synthesizing a plurality of chemical compounds simultaneously, i.e. in parallel, and to synthesize a series of plurality of simultaneously synthesized chemical compounds sequentially, i.e. in series. The apparatus includes a base support structure, a physical chemistry teabag support structure, a plurality of physical chemistry teabags and a fixed-reactant/liquid reactant mixture shifting (changing) mechanism. The base support structure has a plurality of reaction vessels arranged in at least a two dimensional predetermined array. The physical chemistry teabag support structure is adapted to hold and support a plurality of physical chemistry teabags arranged in at least a two dimensional predetermined teabag array, at least partially coinciding with the base support structure reaction vessel array. The teabags have at least one predetermined fixed reactant thereon.

Abstract: The present invention relates to methods for high information content (HIC) analysis or screening of complex biological systems using Fourier transform mass spectrometry (FTMS). The present methods are useful for analyzing complex biological mixtures containing both high molecular weight molecules (e.g., polynucleotides, proteins, polysaccharides) and low molecular weight molecules (e.g., oligonucleotides, peptides, lipids, oligosaccharides, steroid hormones, catabolic and metabolic intermediates) permit the elucidation of molecular differences between complex biological samples, and permit the identification of biologically active molecules (e.g. therapeutically active drugs, etc.).

Abstract: Reaction of a dialdehyde, particularly phthaldialdehyde (I), with R—Z where Z is a nucleophilic group (preferably SH) and R is polymerisable (e.g. allyl) gives a reactive thioacetal (V) which can react with an amine ligand L—NH2 to produce an isoindole (IV) which may be fluorescent. At some stage, generally before interaction with L—NH2, the R groups are polymerised, possibly leading to self-assembly of the polymer on a metal or SH-bearing surface. Such a coated surface is useful as a transducer in assays or as a binding medium e.g. for chromatography.

Abstract: Color-forming compositions comprising (i) a solvent absorbing material such as a polymer; (ii) a color-former or chelating agent compounded with the solvent absorbing material; and (iii) a source of metal ions, whereby the metal ions complex with the color former as the solvent absorbing material absorbs the solvent, resulting in a detectable color change of the solvent absorbing material. Both reversible and irreversible versions of these color-forming compositions are provided.

Abstract: A system for the rapid characterization of multi-analyte fluids, in one embodiment, includes a light source, a sensor array, and a detector. The sensor array is formed from a supporting member into which a plurality of cavities may be formed. A series of chemically sensitive particles are, in one embodiment positioned within the cavities. The particles may be configured to produce a signal when a receptor coupled to the particle interacts with the analyte. Using pattern recognition techniques, the analytes within a multi-analyte fluid may be characterized.

Abstract: Disclosed is a method of detecting the presence in a sample of a polypeptide exogenously administered to a mammalian subject from whom the sample is obtained, and distinguishing between such an exogenously administered polypeptide and a naturally-occurring endogenous polypeptide present in the sample; the method comprising obtaining a sample from the subject; and subjecting the sample to analysis of fluorescence at a suitable wavelength; wherein the exogenously administered polypeptide is tagged with a greater or lesser amount of fluorescence activity, relative to the untagged endogenous polypeptide, at the wavelength(s) analyzed.

Abstract: A method and device is disclosed for rapidly identifying a large number of proteins by placing a protein mixture in a sample chamber of an electrophoresis gel, and performing electrophoresis to separate the mixture by molecular weight, in a direction of separation, into a two-dimensional separation pattern in the gel. The separation pattern is transferred to a membrane, such as a sheet of nitrocellulose, and a plate with a set of separate, side-by-side slots is then applied to the membrane. A different antibody mixture is introduced into each of the slots by perfusing each antibody mixture under pressure through the slots. The antibody mixture that is perfused through each slot recognizes several different proteins of sufficiently different molecular weights that different protein bands can be resolved by the antibody mixture in each slot.

Abstract: The invention provides methods of diagnosis using human antibodies. The methods are particularly useful for analyzing human samples containing HAMA or heterophilic antibodies. A human antibody can bind to an analyte in such samples without binding to HAMA or heterophilic antibodies present in the sample. The methods can be effected using a sandwhich format among others.

Abstract: The present invention provides imprint compositions useful for capturing, isolating, detecting and/or quantifying macromolecules in a sample, methods of making and using the same. Generally, the imprint compositions comprise a matrix material defining an imprint of a template molecule, and the template molecule typically corresponds to a portion of a macromolecule of interest.

Abstract: Provided are a fluorescent microsphere comprised of a plurality of fluorescent nanocrystals embedded in a polymeric microsphere; a kit prepared from the fluorescent microspheres; and a method of producing the fluorescent microspheres comprising swelling the polymeric microsphere so that into its pores can enter fluorescent nanocrystals, and then unswelling the polymeric micropsheres so that the fluorescent nanocrystals become physically entrapped in the pores of the unswelled polymeric microsphere. Also provided is a method of using the fluorescent microspheres comprising affinity ligand for determining the presence or absence of a predetermined number of analytes in a sample by contacting the sample with the fluorescent microspheres, and detecting the fluorescence signal pattern of excited fluorescent microspheres bound to one or more analytes of the predetermined number of analytes, if present in the sample.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Abstract: A method for fabricating contacts on semiconductor components includes the steps of testing the components, and then using test data to fabricate the contacts on only components that meet a predetermined criteria. Initially a substrate, such as a wafer or a panel, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. In a first embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on dice contained on a semiconductor wafer. In a second embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on packages contained on a panel. In a third embodiment, a stencil mask is patterned with openings using a laser scanner programmed with the test data, and solder is stenciled into the openings, and reflow bonded to the component contacts to form contact bumps.

Abstract: A method is disclosed for the induction of a suitable band gap and electron emissive properties into a substance, in which the substrate is provided with a surface structure corresponding to the interference of electron waves. Lithographic or similar techniques are used, either directly onto a metal mounted on the substrate, or onto a mold which then is used to impress the metal. In a preferred embodiment, a trench or series of nano-sized trenches are formed in the metal.

Abstract: A method of preparing a conductive polymeric film, includes providing a liquid crystal phase comprising a plurality of hydrophobic cores, the phase on a substrate, introducing a hydrophobic component to the phase, the component a conductive polymer precursor, and applying an electric potential across the liquid crystal phase, the potential sufficient to polymerize the said precursor.

Abstract: In an imager having an array of light-sensitive elements and employing striped common electrodes, exposed edges of preimidized polyimide layers above the light-sensitive imaging elements are sealed with the material of the common electrode (e.g., indium tin oxide). Similarly, exposed preimidized polyimide edges in electrical contacts for the array and bridge members electrically coupling adjacent light-sensitive imaging elements are also sealed with the material of the common electrode.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

Abstract: A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; a resin encapsulant; and a mark member. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. The mark member is embedded in the upper surface of the resin encapsulant. The mark member, which is transferred from a transfer sheet in a single process step, is highly visible and can be formed efficiently.

Abstract: A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: In a bottom gate type semiconductor device made of a semiconductor layer with crystal structure, source/drain regions are constructed by a lamination layer structure including a first conductive layer (n+ layer), a second conductive layer (n− layer) having resistance higher than the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i layer). At this time, the n− layer acts as LDD region, and the i layer acts as an offset region is a film thickness direction.

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function.

Abstract: The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the position where a tunnel window is to be formed, on top of said gate insulator film; a step for forming an impurity region in the vicinity of the surface of said semiconductor substrate by introducing an impurity using the mask layer; and a step for forming a tunnel insulator film on the surface of the semiconductor substrate, using a mask layer. In the present invention, the position in which the source is formed and the position in which the tunnel window is formed are determined by means of the position of the same through-hole. Therefore, the manufacturing error in the distance between the tunnel window and the source can be nullified.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: In the capacitor in a semiconductor device, a nitride film is formed over a lower electrode on a semiconductor substrate, and a TaON film is formed over the nitride film. The Al2O3 film is formed over the TaON film, and an upper electrode is formed over the Al2O3 film.

Abstract: A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate.

Abstract: A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed.

Abstract: A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the high-voltage device area, a P-body is formed in the epitaxial layer between two adjacent first gate structures. Then, a plurality of second gate structures is formed on the low-voltage device area.

Abstract: A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.

Abstract: A semiconductor device and method of manufacture. A liner composed of a high-K material having a relative permittivity of greater than 10 is formed adjacent at least the sidewalls of a gate. Sidewall spacers are formed adjacent the gate and spaced apart from the gate by the liner. The liner can be removed using an etch process that has substantially no reaction with a gate dielectric of the gate.

Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example, the epitaxial emitter may be N-type single-crystal silicon. The heterojunction bipolar transistor further comprises an etch stop layer situated on the top surface of the base, where the etch stop layer is in contact with the epitaxial emitter. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the etch stop layer, where the epitaxial emitter is situated between the first and second spacer. The first spacer and the second spacer, for example, may be LPCVD silicon nitride. The heterojunction bipolar transistor further comprises a dielectric layer deposited on the first and second spacers.

Abstract: A method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated region around the semiconductor device, followed by wet chemical etching to form a mesa on the order of 0.2 to 0.3 &mgr;m. The method provides a simple but novel approach to fabricate edge terminations in semiconductor devices in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge. Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique disclosed herein utilizes ion-implantation to create a compensated region around the device and wet chemical etching to make a shallow mesa.

Abstract: A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

Abstract: A method for manufacturing a semiconductor device includes the steps of: sequentially forming a pad oxide layer, a nitride layer and a first photoresist layer on the semiconductor substrate; patterning the first photoresist layer into a predetermined shape to form a first photoresist layer pattern; etching the pad oxide layer, the nitride layer and the semiconductor substrate by using the first photoresist layer pattern as an etching mask, thereby forming first and second deep trench isolations in the semiconductor substrate; forming a barrier layer on an inside wall of the second deep trench isolation by performing a nitriding process after removing the first photoresist layer pattern and forming a second photoresist layer pattern at a region formed with the first deep trench isolation on the resultant material; and forming a shallow trench isolation by removing the second photoresist layer pattern and then growing silicon in the first deep trench isolation region covered with the second photoresist layer pa

Abstract: A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

Abstract: A silicon-on-insulator (SOI) device with a strained silicon film has a substrate, and a buried oxide layer on the substrate. Silicon islands are formed on the buried oxide layer, the silicon islands being separated from each other by gaps. The buried oxide layers has recesses directly under the gaps. A material fills the recesses and the gaps, this material being different from the material forming the buried oxide layer. The material induces a net amount of strain in the silicon islands, thereby modifying the electrical properties of carriers in the silicon film and improving device performance.

Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.

Abstract: A method of forming a crystalline semiconductor thin film on a base material which can be prepared at a low temperature by simple step and device, the method including a processing step of applying UV-rays to an amorphous semiconductor thin film provided on a base material while keeping a temperature at not less than 25° C. and not more than 300° C. in a vacuum or a reducing gas atmosphere, as well as a substrate having the semiconductor thin film provided on the base material, a substrate for forming a color filter and a color filter using the substrate.

Abstract: A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within a first depth zone through the second portions of the substrate. The first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth. The substrate is annealed for a first time to form a noncontiguous buried insulating layer substantially within the first depth zone in the second portions of the substrate. The substrate is masked with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate. The fourth portions of the substrate at least partially overlap the second portions of the substrate. A second dopant is implanted substantially within a second depth zone through the fourth portions of the substrate.

Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a gate oxide film on a surface of a semiconductor substrate, subjecting the gate oxide film to a nitriding treatment, forming a gate electrode film over the surface of the semiconductor substrate, annealing the gate oxide film in an inert gas atmosphere after the nitriding treatment and after formation of the gate electrode film, and thereafter patterning the gate electrode film to form a gate electrode.