Abstract: A method for setting an electric motor, which includes, during a non-powering sequence of at least one of the motor phases, measuring on a predetermined time window, the induced voltage (Ti) in the non-powered phase and in comparing its mean value to a threshold value (Ts) to stop powering of the motor on the current sequence if the measured mean value is less than the threshold value.

Abstract: A circuit for the speed recovery of a direct current motor includes an output stage, output stage having a first pair of transistors, a second pair of transistors, and means a first circuit configured to detect a current circulating in the motor. The output stage further includes a second circuit configured to, activate the second pair transistors for a determined first time period so as to short-circuit the motor, and, at the end of the first time period, unbalance the output stage so as to force a maximum current to circulate for a determined second time period as a function of a value detected by the first circuit during the first time period, so as to stop the motor.

Abstract: This invention relates to a system for limitation of the output current from a speed controller for three-phase asynchronous electric motors, comprising a PWM type converter in which the electronic switches are controlled by a microcontroller circuit (Mc), characterized by the fact that the microcontroller circuit comprises means (LIC) of calculating the modulus of the current vector using motor phase current measurements, and comparing it with a limitation set value in order to obtain a limitation error (y) and to calculate a correction voltage (&Dgr;V) that is added to the control voltage (V) applied to the motor.

Abstract: A power supply unit, a distributed power supply system and an electric vehicle loaded therewith, capable of charge/discharge operation are disclosed. A first cell group is connected in parallel to a second cell group in which the electrolytic solution can be electrolyzed or the generated gas can be recombined. A plurality of the parallel circuit pairs are connected in series, and the series circuit is connected with a charger/discharger to constitute the power supply unit. The charger/discharger charges the power supply unit up to a voltage at which the electrolytic solution of the second cell group is electrolyzed or the generated gas is recombined.

Abstract: A power mediation method and circuit for powering a communications controller based device using battery cells that exhibit non stable power delivery characteristics. The use of a servo-loop creates an energy potential in an energy storage element and maintains that required energy potential using the functionality of the communications controller that concurrently draws required power from the energy storage element.

Abstract: When a voltage of a system is stabilized by connecting the system with two types of voltage regulators, i.e., a slow-response tap-changing transformer and a quick-response reactive power regulator, it is not always clear how characteristics of the reactive power regulator should be regulated. Moreover, the regulation takes much time. In a range where voltage fluctuation of the system is small and a tap-changing transformer can cope with the change, gain of a reactive power regulator is set to be low, and its output is restrained. In a range where voltage fluctuation of the system is large and the voltage deviates from a width of a dead zone of the tap-changing transformer, gain of the reactive power regulator is set to be high, and regulating current is fully utilized.

Abstract: In a high-efficiency method and pulse generator for generating short voltage pulses by means of a voltage booster having a first switch, an inductor and a storage capacitor, the first switch generates in the inductor current pulses which are fed to the storage capacitor when the output voltage falls below a predetermined limit value. The pulse generator thus generates a pulse output voltage which is greater than a fed input voltage and is in any desired relationship therewith. The pulse output voltage is fed to a load element by an output switch. The power losses remain low due to pulse-wise charging of a storage capacitor with current pulses.

Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two functions. First, the source current itself flows through the transistors of the transistor biasing circuit to the two transistors forming the first leg of the current mirror. Second, the transistor biasing circuit biases the gates of the transistors in the current mirror so that the output transistors are at the onset of saturation.

Abstract: An electrical sampler device has a plurality of samplers for sampling an electrical signal. Each of the samplers is responsive to a corresponding sampling point. The electrical sampler device also has a propagation line coupled to each of the plurality of samplers, for propagating a sampling signal. One or more delay elements are coupled to the propagation line. The delay means elements delay the propagation of the sampling signal between two neighboring samplers.

Abstract: A method for detecting steady-state convergence of a signal compares a filtered version of the signal or its derivative to a threshold over a given time interval, and a measure of the signal variability is used to tune the filter behavior. In one implementation, the signal is filtered with a high-pass filter, and the cut-off frequency of the filter is adjusted inversely with respect to the measured variability of the signal. In another implementation, the signal derivative is filtered with a low-pass filter, and the cut-off frequency of the filter is adjusted in proportion to the measured variability of the signal. In each case, the variability of the signal is measured by computing a differential of the signal and then smoothing the differential.

Abstract: A coil includes a first portion, a second portion, a third portion, and a fourth portion. The first portion is wound in a first direction around a first core and the second portion is wound in the first direction around a second core. The third portion is wound in a second direction that is different from the first direction around a third core such that the third portion is decoupled from the first and second portions. Additionally, the fourth portion is wound in the second direction around a fourth core and decoupled from the first and second portions. An inner area is formed by arranging the portions and a voltage is induced in the coil if an electrical conductor is placed in the inner area.

Abstract: A method of determining a magnetic track width of a magnetic head. The method begins by obtaining a full track profile of the magnetic head which includes a plurality of signal amplitudes read across a track of a magnetic disk at a plurality of magnetic head positions. An initial magnetic track width value is then determined from the full track profile data. Preferably, this initial value is the magnetic write width which is determined based on the difference between left and right head positions which read half of the maximum signal amplitude. To determine the final magnetic write width, the initial value is adjusted with side reading correction values. The side reading correction values are determined based on left and right side reading “tails” of a bell-shaped signal curve which is formed by the full track profile data when graphed. It is not necessary to obtain the microtrack profile to determine these side reading values.

Abstract: An apparatus and method for decreasing image acquisition and reconstruction times in magnetic resonance imaging are provided. Magnetic resonance data is acquired in parallel by an array of separate RF receiver coils disposed at generally circumferentially-spaced locations relative to one another around the imaging volume defined by the body coil of a magnetic resonance imaging apparatus. Further, the image reconstruction also is performed in parallel, thereby shortening up image display times. The apparatus and method operate on the basis of determining an estimate of the sensitivity profile of each RF coil in the array, and thereafter, utilizing those profiles in the creation of a desired image by encoding later acquired magnetic resonance data from a body of interest disposed in the imaging volume of the magnetic resonance imaging apparatus.

Abstract: A local signal supply device for an NMR spectrometer comprises a local signal generator, the output of which is divided into the same number of portions as there are local signal-selecting switches. The local signal-selecting switches independently select necessary local signals and supply them to corresponding resonance frequency signal generators.

Abstract: A gradient coil assembly for use with an MR imaging system comprising: a main gradient coil disposed about an imaging axis to produce a gradient field; a corrector coil disposed about an imaging axis and positioned with a return portion substantially overlapping a return portion of main gradient coil. The main gradient coil and said corrector coil cooperate to provide a first field of view, the main gradient coil operates to provide a second field of view. A method of reducing power deposition in a gradient coil assembly comprising: determining a first current density corresponding to a first field-of-view for an effective gradient coil; computing a second current density corresponding to a second field of view, by reducing current from the first current density without changing a sign of said the associated therewith; determining a geometry for a main gradient coil; and ascertaining a geometry for a corrector coil.

Abstract: Methods and apparatus are disclosed for minimizing or eliminating an undesired axial electric current induced along a subsurface borehole in the process of subsurface measurements with transmitter and/or receiver antennas which are substantially time varying magnetic dipoles with their dipole moments aligned at an angle to the axis of the borehole. Some antennas are disposed within the borehole on instruments having a non-conductive support member. One instrument includes a conductive all-metal body with an antenna adapted for induction frequencies. Antenna shields adapted for controlled current flow are also provided with an all-metal instrument. Methods include providing an alternate path for the current along the instrument body. Another method includes emitting a controlled current to counter the undesired current. Another method corrects for the effect of the current using a superposition technique.

Abstract: A portable spark tester for a gas cooking appliance includes a housing having a non-conductive base assembly, and a plurality of electrical conductive cables each having a first end adapted to be attached to an ignition wire for a respective gas burner of the appliance, and a second end which is secured within the housing at a position spaced from a central electrode. This spaced relationship defines a spark gap across which an electrical charge can jump. In use, the spark tester provides a technician with the ability to correctly identify certain non-functioning components of a spark ignition system of the gas appliance.

Abstract: The amount of charge passing through a measurement resistor connected to a rechargeable battery is measured by integrating in an analog manner an overall current. This overall current is equal to the sum of the resistor current and of a reference current that selectively takes one of two opposite values. The results of the integration are compared with a reference voltage, and one of two opposite values of the reference current is selected depending on each result of the comparison. The number of times where the positive opposite value of the reference current is selected furnishes an indication on the amount of charge during the integration time.

Abstract: A system and method for testing an on-line current transformer is provided. The current transformer includes a primary winding and a secondary winding. An operating current continues to flow through the primary winding during testing of the current transformer. A controllable load is applied to the current transformer secondary winding. The controllable load is varied over a range of load settings including a maximum current setting and a maximum voltage setting. At a plurality of load settings within the range of load settings, a current flowing through the current transformer secondary winding is measured. Also, a voltage across the current transformer secondary winding is measured. An actual excitation curve is generated from the measured currents and voltages corresponding to the plurality of load settings.

Abstract: A probe for non-destructive determination of complex permittivity of a material and for near field optical microscopy is based on a balanced multi-conductor transmission line structure created on a dielectric substrate member which confines the probing field within a sharply defined sampling volume in the material under study.

Abstract: A low-cost leak sensor that prevents leakage current from flowing between electrodes when moisture is deposited. A leak sensor is formed on an insulating substrate. The leak sensor has a through hole having a pair of opposed walls with a predetermined space. The opposed walls are provided with conducting films. On the opening of the through hole in the insulating substrate, a pair of lands are connected electrically with the pair of conducting films. A pair of wiring patterns are connected electrically with the pair of lands on the insulating substrate.

Abstract: A sensor device for registering voltage drops on corrosion exposed structures and coupled to a surface area thereof to which a voltage is supplied by electrodes causing an excitation current in that area and having a plurality of cables connected to a plurality of sensors arranged in a matrix defining measurement points with defined distances.

Abstract: A method for timed measurement of a voltage across a device in a charging circuit of a piezoelectric element. The voltage across the device is sensed and read at a predefined time in synchronization with an injection event of the at least one piezoelectric actuator. The device may be the piezoelectric element or a buffer capacitor.

Abstract: A method is described for measuring the capacitance and the equivalent oxide thickness of an ultra thin dielectric layer on a silicon substrate in which the dielectric layer is uniform or patterned. The surface of a dielectric layer is electrically charged by a flux on ions from a corona discharge source until a steady state is reached when the corona flux is balanced by the leakage current across a dielectric. The flux is abruptly terminated and the surface potential of a dielectric is measured versus time. The steady state value of the surface potential is obtained by extrapolation of the potential decay curve to the initial moment of ceasing the corona flux. The thickness of a dielectric layer is determined by using the steady state potential or by using the value of the surface potential after a predetermined time.

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop. The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation.

Abstract: In an information processing apparatus, a transmission distortion of a signal transmitted between a module and a controller is reduced. A plurality of modules and a controller controlling the modules are mounted on a circuit board. A bus line connects the controller to the modules, the bus line including a main line and a plurality of branch lines each of which is branched from the main line and is connected to a respective one of the modules. Impedance matching elements are provided to the main line of the bus line so as to match a characteristic impedance between the controller and each of the modules. Each of the impedance matching elements is located behind a branch point of one of the branch lines connected to the respective one of the modules with respect to the controller.

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF.

Abstract: High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number (14) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number (10) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.

Abstract: A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

Abstract: A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.

Abstract: A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).

Abstract: A long channel transistor and a shorter channel transistor operate in conjunction to drive an output node. The long channel device is first activated by a drive signal and the drive signal is input to a delay element that then activates the shorter channel device. By enabling the long channel device first, hot carrier injection effects are reduced. Employing two transistors that are sized to operate in different voltage ranges reduces surge current. The two-transistor configuration of the present invention occupies less area than a single long channel device with similar drive capabilities.

Abstract: A low side switching driver circuit (50) includes an emitter follower circuit, an input buffer (51), and a power source (52) and capacitors (53, 54) for driving these circuits. The power source (52) is not provided for each one of low side switching elements (5, 6, 7), but the low side switching elements (5, 6, 7) use the power source (52) as a common power source thereamong. A resistor (58) is provided between the node between the negative pole of the capacitor (53) and a first low potential power source line, and a second low potential power source line (G) of the low side switching driver circuit. The capacitor (54) is connected to the input buffer (51). Resistors (59, 60) as current limiting elements are provided between the input buffer (51) and the power source (52).

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.

Abstract: A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.

Abstract: Disclosed is a method for calibrating a delay-locked loop containing a chain of delay line elements that propagate a reference clock from delay line element to delay line element. Also disclosed is a delay-locked loop that operates in accordance with the method. The method includes, during a calibration procedure, sequentially varying the configuration of the chain of delay line elements so that there is one unused delay line element and a plurality of used delay line elements and, for each configuration, electrically compensating at least one delay line element based on a phase comparison results obtained from previous calibration configurations of the delay line elements so as to set the total delay through the chain of delay line elements at a desired value. The phase comparison is made between the reference clock and the propagated reference clock.

Abstract: A delay locked loop circuit for improving the jitter index using a phase blender. The present delay locked loop circuit comprises a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, and a second delay circuit which receives an input clock signal in order to generate a second delayed input clock signal. The first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit. The second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delay circuit. A phase blending circuit receives the first and second delayed input clock signals, blends the phases of the first and second delayed input clock signals, and generates a phase blended clock signal.

Abstract: A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal.

Abstract: A phase splitter circuit includes a first signal transfer path for receiving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverted phase of the first output signal, and a duty cycle correction circuit for controlling pull-up and pull-down speeds of the first and second signal transfer paths to the opposite direction in response to the first and second output signals. According to this structure, duty cycles of the first and second output signals approach 50% and a skew or delay time therebetween approaches “0.

Abstract: A high-speed D flip-flop includes first and second precharge circuits, and first to fifth switching circuits. The first precharge circuit precharges first and second internal nodes to a first supply voltage in response to a clock signal, and the first switching circuit provides a first discharge path between the first internal node and a third internal node in response to an input signal. The second switching circuit provides a second discharge path between the second and third internal nodes in response to a potential of the first internal node, and the second precharge circuit precharges an output terminal to a first supply voltage in response to a potential of the second internal node. The first switching circuit provides a third discharge path between the output terminal an the third internal node in response to the potential of the second internal node, and the fourth switching circuit connects the first to third discharge paths with a second supply voltage in response to the clock signal.

Abstract: The present invention is directed to a phase shifting arrangement for generating a set of mutually orthogonal signals. In one aspect, the invention provides a system that includes a phase shifting unit for receiving an input signal. The phase shifting unit includes a first phase shift circuit for generating a first output signal phase-shifted by a first amount with respect to the input signal, a second phase shift circuit for generating a second output signal phase-shifted by a second amount with respect to the input signal, and a third phase shift circuit for generating a third output signal phase-shifted by a third amount with respect to the input signal.

Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

Abstract: A bidirectional bipolar transistor switch for use in customer end telecommunications equipment connected to a telephone line whose line feed polarity can be either positive or negative, for switching low level AC signals. A pair of bipolar transistors are connected in anti-parallel and are operated by a common current sensing resistor in the base/emitter circuit of both transistors. The transistors operate with no DC bias on the collector, and both forward and reverse conductor modes are used.

Abstract: A precision current source is disclosed that includes a voltage setting circuit that precisely sets the voltage across a range setting resistor to set the current flowing in a load resistance connected in series with the range setting resistor. The voltage setting circuit precisely sets the voltage across the range setting resistor as a function of an input reference voltage. The voltage setting circuit includes an instrumentation amplifier that determines the voltage across the range setting resistor and the difference between this voltage and the reference voltage is used drive a drive voltage amplifier. The drive voltage amplifier output adjusts to minimize the difference between the reference voltage and the voltage across the range setting resistor. Other embodiments include the use of a DC blocking capacitor to allow only AC coupling and various nulling. circuits to remove any charge buildup on a DC blocking capacitor.

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.

Abstract: A system and method for filtering a jittered clock is disclosed. The filter of the present invention may check if a reference clock is received at a point in time within a pre-defined window of time. If the clock is received at a point in time within the window, the reference clock may be utilized as a reference for a system application such as a reference for a phase-locked loop. If the reference clock is not received at a point in time within the window, an interpolated clock representing an ideal received clock may be utilized. This may minimize the disturbance of system applications by blocking extreme deviations of the reference clock.

Abstract: An at least second-order active filter circuit includes an operational amplifier (Op) whose frequency response, in conjunction with an RC network (R1, R2, C1, C2), serves to set a predetermined low-pass characteristic. The frequency response of the operational amplifier (Op) forms an integral part of this low-pass characteristic.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).