Abstract: Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.

Abstract: A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that the interstitial gallium does not diffuse to the base layer and thus does not cause the beryllium to be displaced and diffused. Instead of doping with phosphorus, a layer including phosphorus can also be utilized.

Abstract: A X-Y addressable MOS imager sensor method and apparatus wherein a semiconductor based MOS sensor having an array of pixels forming the X-Y addressable MOS imager, the X-Y addressable MOS imager having a plurality of the pixels such that each pixel within the plurality of pixels has a photodetector with a reset mechanism that adjusts the photodetector potential to a predetermined potential level employs the measuring a plurality of reset levels with two different elapsed times between reset and measurement of the reset level, a comparison circuit operatively coupled to the means for measuring to determine a difference in reset levels, a predetermined set of transfer functions used to identify effective signal levels of the photodetectors, and determines from the difference which transfer function is applicable to that photodetector range of accumulated light. In response to the difference detected, transfer functions are applied to the charge read out from the photodetector.

Abstract: Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of manufacturing the particular semiconductor memory device. Specifically, provided are a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film, and a method of manufacturing the particular semiconductor memory device.

Abstract: A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.

Abstract: A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with an identical pitch, and, also, alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed to have the vertical construction and the bit line located at the upper side of the substrate, where a channel region is formed, is shielded with a conductive film, a part of which forms the gate electrode.

Abstract: The present invention relates to the field of semiconductor integrated circuits and, in particular, to capacitor arrays formed over the bit line of an integrated circuit substrate. The present invention provides a method for forming stacked capacitors, in which a plurality of patterned capacitor outlines, or walls, are formed over the bit line of a semiconductor device. In one aspect of the invention, spacers are formed on the patterned capacitor outlines and become part of the cell poly after being covered with cell nitride. In another aspect, the spacers are formed of a material capable of being etched back, such as titanium nitride. In another aspect, a metal layer is patterned and annealed to a polysilicon layer to form a mask for a capacitor array, and subsequently etched to form the array.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.

Abstract: Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate; forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

Abstract: A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is formed with the control gates and extends in a common horizontal direction.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A nonvolatile semiconductor memory device has a cell transistor and a non-cell transistor which are covered with an interlayer insulator film (228). The non-cell transistor has a first insulator film (212) formed on a semiconductor substrate (210); a first gate electrode (214b) formed on the first insulator film; a second insulator film (216b) formed on the first gate electrode in a first area of the gate electrode, the first area being a part of the first gate electrode; a second gate electrode (218b) formed on the second insulator film; and a contact portion (234) embedded in a contact hole (232) of the interlayer insulator film (228) to contact the first gate electrode in a second area of the first gate electrode, wherein the second insulator film is not formed on the second area and the contact portion is out of contact with the second insulator film.

Abstract: The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A CMOS device with an integral reverse connection protection circuit having a low impedance region, whose impedance becomes lowest when a Vcc pad to which is to be supplied power supply voltage and a GND pad to which is to be supplied ground potential are connected in reverse polarity. The low impedance region, Vcc pad and GND pad are electrically connected through a metal line and a metal line, and current is diverted into the low impedance region during the reverse connection so as to protect an internal circuit. Surge protection elements with identical characteristics are disposed in proximity to three sides or four sides of a pad, and each side of the pad and the surge protection element corresponding thereto are electrically connected to each other, so that surge current applied to the pad is dispersed to the plurality of surge protection elements to protect the internal circuit.

Abstract: A semiconductor device has a first IGBT (1) for controlling a principal current and a second IGBT (2) for preventing an over-current of the first IGBT (1). A diode portion (11) is disposed between the emitter (5) of the first IGBT (1) and the emitter (6) of the second IGBT (2) so as to be in parallel with a sensing resistor (8). The diode portion (11) is composed of a first diode (9) and a second diode (10), which are connected in reverse series to each other. In order to prevent the over-current of the first IGBT (1) and the destruction of the second IGBT (2), each of the diodes (9, 10) has a breakdown voltage in the reverse voltage direction, which is lower than the endurance voltage between the emitters (5, 6) and is higher than the upper limit of the voltage sensed by the sensing resistor (8).

Abstract: A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs.

Abstract: A lateral high voltage transistor device is disclosed. The transistor includes a gate, a drain, and a source. The drain is located apart from the gate to form an intermediate drift region. The drift region has variable dopant concentration between the drain and the gate. In addition, a spiral resistor is placed over the drift region and is connected to the drain and either the gate or the source of the transistor.

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract: An anisotropic conductive film which can be appropriately applied for the display apparatus by which the user can directly write characters•figures on the display, or erase characters and figures displayed on the display. The anisotropic conductive film according to the present invention is provided with the transparent insulating film 19 having a plurality of through holes 20 penetrating from one surface to the other surface, transparent conductive particle 21 buried in the through holes 20, and transparent stuffing material 22 stuffed in the void of the through holes 20 in which the conductive particle 21 is buried.

Abstract: Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods are described. In one embodiment, a monolithic inductance-enhancing integrated circuit comprises a transistor supported by a bulk monocrystalline silicon substrate. An inductor assembly is supported by the substrate and operably connected with the transistor in an inductance-enhancing circuit configuration having a quality factor (Q) greater than 10. In another embodiment, a complementary metal oxide semiconductor (CMOS), inductance-enhancing integrated circuit includes a field effect transistor supported over a silicon-containing substrate and having a gate, a source, and a drain. A first inductor is received within an insulative material layer over the substrate, and is connected to the gate. A second inductor is received within the insulative material layer and is connected to the source.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element. A capacitor is used in an illustrative example.

Abstract: According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.

Abstract: An object of the invention is to minimize variation in characteristics of a vertical bipolar transistor. An insulating side wall spacer composed of a silicon nitride film 10 and a silicon oxide film 9 is formed on the side surface of an opening 101 formed in a base electrode polysilicon film 7. The thickness (=WD) of the insulating side wall spacer is made thicker than the maximum thickness (=WF) within a range of variation in thickness of a polycrystalline film 12 grown from the side surface of the base electrode polysilicon film 7 exposed inside the opening 101 (namely, WD>WF). The size of an opening for forming an emitter electrode polysilicon film 16 on an intrinsic base 11 is not influenced by the thickness of a polycrystalline film 12 epitaxially growing from the side surface of the polysilicon film 7 for the base electrode, but is defined by the side wall spacer formed on a portion of the side surface of the base electrode polysilicon film.

Abstract: A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).

Abstract: A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; and a resin encapsulant. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate and a second bottom face of the semiconductor chip is in contact with the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. A level difference exists between a first bottom face and the second bottom face of the semiconductor chip. The first and second bottom faces are respectively located at a peripheral portion and a central portion of the semiconductor chip. A part of the resin encapsulant is interposed between the first bottom face and the upper surface of the wiring substrate.

Abstract: An image sensor to be mounted to a printed circuit board. The module includes a substrate, an integrated circuit, a frame layer, a photosensitive chip, a plurality of wires, and a transparent layer. The substrate is composed of metal sheets arranged in a matrix, and a middle board positioned in a central region surrounded by the metal sheets. Each metal sheet has a first board and a second board connected to the printed circuit board. A slot is formed under the substrate. The integrated circuit is arranged within the slot and electrically connected to the substrate. The chip is placed on the middle board. The wires electrically connect the first boards, to the chip. The transparent layer is placed on the frame layer to cover the chip.

Abstract: A socket coupled to a circuit board to receive a package of microelectronic device has one or more electrical contacts coupled to its outer surfaces. Each contact provides a low inductance shunt connection from the side of the package to the circuit board. The contact includes multiple adjacent, electrically conductive members, each including a rigid portion and a flexible portion projecting from the rigid portion. The flexible portion is positioned to be in physical contact with a corresponding electrical conductor on an outer surface of the package when the package is coupled to the socket. At least one adjacent pair of the electrically conductive members conduct current in opposite directions to provide mutual inductance. The contact further includes a dielectric layer sandwiched between each two adjacent rigid portions of the conductive members.

Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.

Abstract: An electronic component having recesses on side faces of its package for housing an electric element therein. A metal layer that does not reach the bottom end of the package is formed on the surface of the recess. The metal layer has excellent wettability to a brazing material and helps extra material flow into the recess easily. In addition, the interface between the top end face of the recess and the side face is curved to make the brazing material flow into the recess easily. When the opening of the package is sealed with a lid using the brazing material, the extra brazing material flows into the recess. This prevents the brazing material from protruding outside of the package and thus improves dimensional accuracy of the electronic component. Therefore, mounting accuracy of the electronic component can be improved and short circuit can be prevented.

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract: In packaging integrated circuits for high speed (multi-gigabit) applications, chip carriers having signal paths between the substrate board and the chips at the top with a number of evenly divided vertical steps produces frequency properties that are sufficiently good that it is possible to run signals through the package, rather than by means of connectors attached to the top surface of the carrier.

Abstract: A multi-chip semiconductor package is proposed, in which a lead frame is formed with a chip carrier that consists of at least one supporting frame and a plurality of downwardly extending portions integrally formed with the supporting frame. As the chip carrier occupies small space, this does not impede flowing of a molding compound used for forming an encapsulant. The adjacent extending portions are provided with sufficient space therebetween for allowing the molding compound to flow through the space, so that problems of incomplete filling with the molding compound and the formation of voids can be eliminated. Moreover, the downwardly extending portions can function as a pre-stressed structure so as to closely abut a bottom of a mold cavity after mold engagement, thereby making the chip carrier well assured in position without being dislocated.

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: A high frequency semiconductor integrated circuit device having a semiconductor chip, a package for housing the semiconductor chip and a ground conductor, comprises a first package terminal for transferring a high frequency signal; a second package terminal which is either a package terminal for transferring a high frequency signal or a package terminal for supplying current to a node at which a high frequency signal is transferred or to a drain of a transistor; a third package terminal disposed between the first and second package terminals, for applying a bias voltage to a circuit element of the integrated circuit through a first resistor; and a first capacitor disposed in the package, and having one electrode connected between the third package terminal and the first resistor and the other electrode connected to the ground conductor. The integrated circuit device provides sufficient high frequency isolation between package terminals.

Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.

Abstract: A probe unit has a plurality of metal leads regularly juxtaposed on the surface of a substrate. Each metal lead has a resilient contact piece in a front portion of the lead, the resilient contact piece being spaced apart from the substrate surface or extending over an edge of the substrate. The cross sectional shape of the resilient contact piece is an arc shape and/or has a projection near at the distal end of the resilient contact piece.

Abstract: A semiconductor device includes a first interlayer film of SiN and a second interlayer film of SiO2 that are formed in the order over a semiconductor substrate having, at a surface, a conductive layer. In the same or different etching process, a contact or via hole is formed through the first interlayer film above the conductive layer, while an interconnect trench is formed through the second interlayer film.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of the lower plug, so that a contact area between the lower plug and the conductive layer increases without increasing a contact resistance therebetween. Thus, the conductive layer can endure physical impacts applied in the formation of the conductive layer itself and in subsequent integration processes, without detaching from the lower plug or the wafer.

Abstract: Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.

Abstract: In order to prevent a rise in resistance due to oxidation of copper wiring and diffusion of copper, a semiconductor device is provided which contains a wire protective film 1 covering the top of the copper wiring 2 formed in the insulation film and a barrier film surrounding the side and bottom of the copper wiring. The wire protective film and/or barrier film is formed with a cobalt alloy film containing (1) cobalt, (2) at least one of chromium, molybdenum, tungsten, rhenium, thallium and phosphorus, and (3) boron.

Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.

Abstract: The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

Abstract: A semiconductor integrated circuit 10 includes a semiconductor substrate 1, an insulating layer 2 formed on the semiconductor substrate 1, and a bonding pad 3 formed on the insulating layer 2. The semiconductor substrate 1 has a region 4 facing the bonding pad 3 and a region 5 substantially surrounding at least a part of the region 4. The region 5 of the semiconductor substrate 1 is set substantially at an equipotential.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: In plastics-encapsulated semiconductor devices, for example surface-mount power devices, aluminium corrosion due to ingress or generation of moisture within the encapsulation (150) is avoided by bonding at least one sacrificial additional wire (24, 25, 26, 27) of substantially pure aluminium to a bond pad (11, 13, 14) and/or terminal area (101, 110) of the device. The actual connection wires (21, 22, 23) of the device are of an alloyed aluminium material, such as nickel-doped aluminium, that is more resistant to corrosion by moisture than is the sacrificial additional wire (24, 25, 27). The sacrificial additional wire (24, 25, 27) serves as a corrodible getter of the moisture within the encapsulation (150). The bond pads (11, 12, 13, 14) may be of an aluminium alloy, for example an aluminium-silicon alloy, or even of relatively pure aluminium.

Abstract: An electrical circuit is disclosed having a drive stage and a control stage suitable, for example, for operating an electric motor in an electrical power assisted steering system.