Abstract: A method for transfecting T cells with a nucleic acid molecule comprising a gene such that the gene is expressed in the T cells is described. The T cells are stimulated and proliferating prior to introduction of the nucleic acid molecule.

Abstract: The invention is directed to reliable and efficient detection of mRNAs as well as other RNAs in living cells and its use to identify and, if desired, separate cells based on their desired characteristics. Such methods greatly simplify and reduce the time necessary to carry out previously-known procedures, and offers new approaches as well, such as selecting cells that generate a particular protein or antisense oligonucleotide, generating cell lines that express multiple proteins, generating cell lines with knock-out of one or more protein, and others.

Abstract: The problem of replication-competent adenovirus in virus production is solved in that we have developed packaging cells that have no overlapping sequences with a new basic vector and thus, are suited for safe large scale production of recombinant adenoviruses. One of the additional problems associated with the use of recombinant adenovirus vectors is the host-defense reaction against treatment with adenovirus. Another aspect of the invention involves screening recombinant adenovirus vector lots, especially those intended for clinical use, for the presence of adenovirus E1 sequences, as this will reveal replication-competent adenovirus, as well as revertant E1 adenoviruses. It is also an aspect of the present invention to molecularly characterize the revertants that are generated in the newer helper/vector combinations.

Abstract: A method, compositions and kit are set forth for detecting blood stains. A reactant solution includes fluorescin solubilized (reduced) in acetic acid in ethanol. The solution may be buffered to a pH of approximately 9. After spraying the reactant solution on the suspected area an oxidizer is applied to promote the fluorescin to fluorescein reaction with the blood. The reacted fluorescein is then detected through luminescence for capture by photography.

Abstract: A method for utilizing a filtration device for removing interferants from a test sample containing a mixture of a composition of interest and interferants in an automated apparatus is disclosed. The filtration device includes a microporous hollow fiber membrane having a plurality of pores sized to retain the composition of interest while allowing smaller diameter interferants to pass through the membrane.

Abstract: This invention relates to a method for using a novel combination of assays to detect minimal activation of the coagulation response for determining whether a patient whose initial clinical evaluation indicates chronic fatigue syndrome, fibromyalgia, and related conditions can be treated using anticoagulant therapies. If activation of the coagulation response is detected, the present invention further includes treatment of CFS, FM or related condition using anticoagulant therapies.

Abstract: A method and apparatus are provided for measuring the gas efflux from a substrate. In particular, one or more measuring chambers receive a gas enriched air from the substrate. A respiration system sends reference air having a known gas concentration to the measuring chamber. The reference air mixes with the gas enriched air to form a mixed air, which is returned to the respiration system. The respiration system then measures the gas efflux of the substrate over the given amount of time.

Abstract: A novel method for the qualitative and quantitative analysis of dicarboxylic acids in biological samples is provided. The method includes the steps of esterfying the acid component of the sample and subsequently analyzing the esterified sample using tandem mass spectroscopy using atmospheric pressure ionization techniques in the positive ion mode. The method is particularly useful in the determination of methylmalonic acid in biological samples, and thus, the diagnosis of vitamin B12 deficiency.

Abstract: A device for producing microscopic arrays of molecules is provided, the device comprising a plurality of inverted cavities containing solutions, a substrate adapted to be received by the cavities for extracting the solutions, a substrate for depositing the extracted solutions onto a location on a matrix; and a quality control monitoring system for verifying that the solutions are deposited onto the location on the matrix. A process for producing an array of molecules also is provided, the process comprising providing a plurality of inverted solution cavities, wherein each cavity contains a solution; extracting each solution from its respective inverted cavity; loading each solution at a predetermined position in an array; and verifying that each solution is loaded onto its respective position in the array.

Abstract: The present invention relates to bioassay materials useful for the detection of toxic substances and, more particularly, to packaging materials for food and other products, along with methods for their manufacture and use. The invention provides a unique composite material capable of detecting and identifying multiple biological materials within a single package. The biological material identification system is designed for incorporation into existing types of flexible packaging material such as polyvinylchloride or polyolefin films, and its introduction into the existing packaging infrastructure will require little or no change to present systems or procedures.

Abstract: A surface plasmon resonance apparatus for detecting a soluble analyte (e.g. a protein) or a particulate analyte (e.g. a cell), the apparatus comprising: (a) a sensor block adapted to receive a sensor, said sensor, for example a sensor slide, having a metallized sensor surface capable of binding the analyte; (b) a light source capable of generating an evanescent wave at the sensor surface of a sensor slide on the sensor block; (c) a first detector capable of detecting light from the light source which is internally reflected from the sensor surface; and (d) a second detector (e.g. a video camera) capable of detecting light scattered or emitted from an analyte bound thereto. Optionally the apparatus further comprises a second light source for increasing the intensity of the light scattered or emitted from an analyte bound to the sensor surface, preferably, this is sited to such as to minimize the amount of light transmitted therefrom which is detected by the first detector.

Abstract: Compositions are disclosed comprising (a) a metal chelate wherein the metal is selected from the group consisting of europium, terbium, dysprosium, samarium osmium and ruthenium in at least a hexacoordinated state and (b) a compound having a double bond substituted with two aryl groups, an oxygen atom and an atom selected from the group consisting of oxygen, sulfur and nitrogen wherein one of the aryl groups is electron donating with respect to the other. Such composition is preferably incorporated in a latex particulate material. Methods and kits are also disclosed for determining an analyte in a medium suspected of containing the analyte. The methods and kits employ as one component a composition as described above.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: A method is provided for manufacturing a magnetic head for recording information on a magnetic recording medium in the form of a direction of magnetization, which enables manufacture of a magnetic head with gaps between turns of a conductive material constituting a coil being filled with an insulating material without any void and heat generation in the coil being suppressed. A photoresist with a higher flowability than an insulating material containing a metal element is applied to the coil. A part of the photoresist applied to the coil which covers the conductive material constituting the coil is removed by exposure and development, and on the conductive material, an insulating metal compound layer made of an insulating material containing a metal element and having a higher thermal conductivity than the photoresist is formed and polished for flattening.

Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.

Abstract: A optoelectronic module comprises one or more VCSELs electrically connected to an IC and optically connected to a fiber optic faceplate. The fiber optic faceplate, comprising a closely packed bundle of optical fibers, permits efficient capture of light from the VCSELs. Precise alignment of the faceplate with respect to the VCSELs is not needed since light not collected by one fiber is captured by another nearby optical fiber. One method of fabricating the module comprises forming substrate layers on both sides of the VCSELs such that features can be formed on the first substrate layer while the second temporary substrate layer provides structural support. The method further comprises forming apertures on the first substrate layer by etching. An etch stop buffer layer positioned between the first substrate layer and the VCSELs protects the VCSELs from being etched in the process. The second temporary substrate layer is removed after the fiber optic faceplate is mounted on the first substrate side.

Abstract: A method of fabricating a monolithic integrated semiconductor photonic device is provided. In this method, it is possible to remarkably reduce an optical loss in a passive waveguide by forming a non-doped clad layer around a passive layer. Thus, the passive waveguide can be effectively coupled with an active waveguide. Further, a current confinement layer is formed around an active layer, using the non-doped clad layer. Therefore, an expensive tool such as an ion implanter is not required, thereby decreasing manufacturing costs.

Abstract: A method of manufacturing a solar cell comprises interposing an intermediate layer containing p-type or n-type impurity between a silicon thin film and a support substrate, and heating all or part of the structure thus formed to a temperature at which the impurity contained in the intermediate layer diffuses into the silicon thin film, forming a high-concentration impurity layer in the silicon thin film.

Abstract: In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrative optical semiconductor integrated circuit device, a vertical pnp transistor and a photodiode have been formed, and first and second epitaxial layers and are stacked without doping. This enables a depletion layer forming region to be remarkably increased in the photodiode, and high-speed response becomes possible. Additionally, in the vertical pnp transistor, an n+ type diffusion region surrounds the transistor forming region. This can remarkably improve voltage endurance of the vertical pnp transistor 21.

Abstract: A method of forming a color filter on a substrate having pixel driving elements. A substrate having a plurality of light-transmitting areas and active areas is provided. A pixel driving element is formed on the substrate in each active area, wherein an insulation layer is formed between each pixel driving element. A planarization layer is formed on the pixel driving elements and the insulation layer. Part of the planarization layer is removed to form contact holes and openings, wherein the contact holes expose part of the pixel driving elements, and the openings expose the insulation layer in the light-transmitting areas. Color pigment is filled into the openings to form a color filter on the substrate having the pixel driving elements. Transparent pixel electrodes are formed in the contact holes to electrically connect the pixel driving elements, wherein the transparent electrodes extend onto part of the color filter.

Abstract: The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed.

Abstract: A solar cell substrate with thin film polysilicon. The solar cell substrate includes a substrate; a transparent conductive layer, formed on the substrate; a thermal isolation layer having inlaid conductive layers, formed on the transparent conductive layer; and a polysilicon layer, formed on the thermal isolation layer.

Abstract: A method of encapsulating components based on organic semiconductors, includes adhesively bonding a housing to a substrate. Bonding is carried out using a UV-curable reactive adhesive including an epoxy resin, a hydroxy-functional reaction product of an epoxide compound with a phenolic compound, a silane-type adhesion promoter, and a photoinitiator, and also if desired, filler. This method is used in particular for encapsulating organic light-emitting diodes (OLEDs).

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: A method is proposed for fabricating a substrate-based semiconductor package without mold flash. The proposed method is characterized by the provision of one or more dummy traces between each overly-spaced pair of signal traces that might cause mold flash in subsequent molding process, so that the solder mask covering over these traces can be made substantially planarized in its top surface without the undesired forming of a recessed portion that would otherwise cause leakage of molding material to the outside of the molding region during molding process. Owing to the provision of these dummy traces, no leakage hole would exist between the molding tool and the solder mask, thus preventing mold flash. The proposed method therefore allows the finished semiconductor package to be more assured in quality.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: In a semiconductor device, each of the leads is provided with guided-surfaces that are inclined surfaces and each of the bumps is provided with a recess that has guide-surfaces formed by inclined surfaces. The leads are smoothly guided toward the centers of the upper surfaces of the bumps with the aides of the inclined surfaces formed on the leads and bumps, so that the attitude of the leads is corrected and the leads are snugly brought into the recess and prevented form falling off of the bump.

Abstract: The resin-encapsulated semiconductor device of the present invention includes: a die pad provided by thinning a lower portion of a lead frame; a semiconductor chip mounted on the die pad; a plurality of leads provided by thinning an upper portion of the lead frame; a connection member for connecting the semiconductor chip and the lead with each other; a plurality of suspension leads connected to the die pad; and an encapsulation resin for encapsulating an upper portion of the lead frame. In this way, it is possible to further reduce the thickness of a resin-encapsulated semiconductor device, while upsetting the die pad. Furthermore, the stress occurring from the encapsulation resin is absorbed by the self flexural deformation of the die pad and the lead, which are thinned, thereby improving the connection reliability.

Abstract: A method of making a Fe-Ni strip whose chemical composition comprises, by weight: 36% ≦Ni+Co≦43%; 0%≦Co≦3%; 0.05%≦C≦0.4%; 0.2%≦Cr≦1.5%; 0.4%≦Mo≦3%; Cu≦3%; Si≦0.3%, Mn≦0.3%; the rest being iron and impurities, the alloy having an elastic limit Rp0.2 more than 750 Mpa and a distributed elongation Ar more than 5%. The alloy is optionally recast under slag. The strip is obtained by hot-rolling above 950° C., then cold-rolling and carrying out a hardening treatment between 450° C. and 850° C., the hardening heat treatment being preceded by a reduction of at least 40%. The invention is useful for making integrated circuit support grids and electronic gun grids.

Abstract: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a coefficient of thermal expansion that is less than the mold compound. The IC package is capable of being attached to a circuit board via a mass reflow process.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: The present invention relates to a method for crystallizing the active layer of a thin film transistor utilizing crystal filtering technique. According to the conventional metal induced lateral crystallization (MILC) method, amorphous silicon layer can be crystallized into poly-crystal silicon layer. According the crystal filtering technique of the present invention, amorphous silicon layer can be single-crystallized by filtering a single crystal component from the poly-crystal region being crystallized by MILC. The TFT fabricated including an active layer crystallized according to the present method has significantly improved electrical characteristics such as electron mobility and leakage current as compared to the TFT including a poly-crystal silicon active layer made by conventional methods. The invention also provides various TFT fabrication methods applying the crystal filtering technique.

Abstract: The present invention discloses a method of manufacturing an active matrix display device, comprising: a) forming a semiconductor layer on an insulating substrate; b) forming a gate insulating layer over the whole surface of the substrate while convering the semiconductor layer; c) forming a gate electrode on the gate insulating layer over the semiconductor layer; d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer; e) ion-implaing a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer; f) depositing sequentially a transparent conductive layer and a metal layer on the inter insulating layer; g) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes directly contacting the high-density source and drain regions and having a dual-layered structure; h) forming a passivation layer over the

Abstract: A high-quality diode is formed in an SOI process, using standard steps and implant doses that are used in the process for other devices such as a FET and a buried resistor; in particular using a buried resistor mask and implant to form one side of the diode, using the FET gate oxide to terminate the P-N junction, and using the FET gate to protect the junction from shorting during the silicide step.

Abstract: There is provided the step of forming a polysilicon film by scanning a laser irradiation region while irradiating a continuous wave laser onto an amorphous silicon film formed into an island or ribbon-like shape on a substrate. If a width of a rectangle in which the amorphous silicon film is inscribed is 30 &mgr;m or less, any one condition of (1) a top end shape of a pattern is a convex shape, (2) a top end shape is a concave shape and consists of straight lines and has three corner portions at a top end side, and both angles of the corner portions on both sides of the top end shape are set to 45 degree or more, (3) a top end shape is a concave shape and consists of curved lines, and (4) a width of a top end portion is 25 &mgr;m or less, is satisfied.

Abstract: The invention provides a semiconductor device and a method for forming patterns in which the manufacturing cost is reduced while the step coverage is improved. The ITO film 50 and the MoCr film 100 are dry-etched after having formed the ITO film 50 and the MoCr film 100.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: In a semiconductor device, formed are a lower capacitor electrode on an element isolation film on a silicon substrate, a capacitor insulating film and an upper capacitor electrode. A silicon oxide film is formed on the entire surface of the silicon substrate. On the silicon oxide substrate, formed is a resist pattern that covers a region extending from the inside of a periphery of the upper capacitor electrode to the outside of the periphery thereof. Sidewalls that cover side faces of a gate electrode and the lower capacitor electrode, and a sidewall that covers a side face and an upper periphery of the upper capacitor electrode, are formed by performing anisotropic etching.

Abstract: A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: In order to fill in an isolation trench formed on a semiconductor substrate, the isolation trench is filled up to a predetermined middle position with a coating film first, and then an insulating film formed by a CVD method is deposited thereon. Additionally, the insulating film is polished by a CMP method, for example, so as to be ground. Thus, the isolation trench is filled with stacked films of the coating film and the insulating film. Further, an electrode pattern and a dummy pattern are formed on the semiconductor substrate, and the trench formed between these patterns is filled up to a predetermined middle position in its depth direction with the coating film. Then, a remaining depth portion of the trench is filled with the insulating film formed by a CVD method.

Abstract: For fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, any region of a stack of a layer of tunnel dielectric material, a layer of floating gate material, a layer of floating dielectric material, and a layer of control gate material, not under a patterning structure, is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material over the tunnel dielectric structure, to form a floating dielectric structure comprised of the floating dielectric material disposed over the floating gate structure, and to form a control gate structure comprised of the control gate material disposed over the floating dielectric structure.

Abstract: A memory cell and method for making a memory cell. The memory cell has a floating gate and a control gate, and a source region and a drain region. The structure of the device is such that the area of capacitive coupling between the floating gate and the source region is oriented along a sidewall of a trench formed in a substrate. The drain region is disposed under the bottom of the trench.

Abstract: A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench.

Abstract: A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.