Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: Notches are formed in a surface of a wafer on which semiconductor elements have been formed. Then, a surface protection tape is stuck to the element-formed surface of the wafer. Subsequently, the wafer is cleaved along a crystal orientation using the notches as starting points. Finally, a back surface of the wafer is ground.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.

Abstract: A semiconductor device where an interface circuit operating on a high power supply voltage and exchanging signals and data with an external device and an internal circuit operating on a low power supply voltage are integrated in a single chip. The interface circuit includes a transistor whose gate insulating film is made of SiO2. The internal circuit includes a transistor whose gate insulating film is made of an oxynitride film of nitrogen-added SiO2. Boron or BF2 has been introduced into the gate electrodes of the p-channel transistors among those whose gate insulating films have been made of an oxynitride film.

Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of stack materials and oxidation methods. The etch stop layer may be patterned within the poly or may be a continuous conductive etch stop layer in the poly. The present invention also relates more broadly to a process for forming wordline architecture of a memory cell. In accordance with another embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly.

Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip with upper and lower surfaces, wherein the upper surface includes a conductive pad, providing a conductive trace, then disposing an insulative adhesive between the conductive trace and the chip, thereby mechanically attaching the conductive trace to the chip such that the conductive trace overlaps the pad, the adhesive contacts and is sandwiched between the conductive trace and the pad, and the conductive trace and the pad are electrically isolated from one another, then removing the adhesive between the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the adhesive is removed by laser ablation then plasma etching.

Abstract: A conductive composition of titanium boronitride (TiBxNy) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the titanium boronitride is used to construct contact pads such as inline pads, backend pads, sensors or probes. Advantages of embodiments of the titanium boronitride include reduced scratching, increased hardness, finer granularity, thermal stability, good adhesion, and low bulk resistivity. Exemplary methods of creating the titanium boronitride include a sputtering process and a plasma anneal process.

Abstract: A fabrication method of wafer level packages capable of improving reliability by maximizing a contact area of metal wiring and a conductive ball and of simplifying fabrication processes by reducing the number of sputtering. The disclosed method comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer including a first opening exposing the chip pad and a second opening forming a ball land on the substrate; forming metal wiring connected to the chip pad in a single unit through the first opening and covering the second opening to have a ball land on the first insulating layer; forming a second insulating layer including a third opening which covers the metal wiring, however, exposes the ball land; and adhering a conductive ball to be in contact with the third opening on the ball land.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: A method for depositing a silicon oxycarbide hard mask on a low k dielectric layer is provided. Substrates containing a silicon oxycarbide hard mask on a low k dielectric layer are also disclosed. The silicon oxycarbide hard mask may be formed by a processing gas comprising a siloxane.

Abstract: A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

Abstract: Tungsten silicide WSix is grown through reduction of WF6 with SiCl2H2, and the flow rate between WF6 and SiCl2H2 is controlled in such a manner that the composition ratio x ranges from 2.0 to 2.2 in an initial stage for forming cores on a doped polysilicon layer, and is treated with heat at 700 degrees to 850 degrees in centigrade so as to grow tungsten silicide grains with <001> orientation faster than tungsten silicide grains with <101> orientation; the tungsten silicide WSix is tightly adhered to the doped polysilicon, and the abnormal oxidation is restricted during the heat treatment.

Abstract: A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO2 film (insulating film), a via hole provided in the SiO2 film on the electrode pad along the opening rim of the through hole, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole.

Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

Abstract: A semiconductor device having a multi-layered spacer and a method of manufacturing the semiconductor device include gate electrodes each comprising a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor substrate, a gate polyoxide layer formed on sidewalls of the gate conductive layer and the gate oxide layer and being in contact with a predetermined portion of the semiconductor substrate, a silicon nitride layer being in contact with sidewalls of the capping dielectric layer and the gate polyoxide layer, an oxide layer being in contact with the silicon nitride layer, and an external spacer being in contact with the oxide layer.

Abstract: A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over the polysilicon layer. After forming both the polysilicon layer and the nitride layer, both the polysilicon layer and the nitride layer are etched from a certain uppermost portion of the sidewalls of the trench thereby exposing the silicon substrate at the uppermost portions of the sidewalls. After exposing the silicon substrate at the uppermost portions of the sidewalls, a collar oxide layer is formed over the exposed silicon substrate at the uppermost portions of the sidewalls thereby protecting any edges of the polysilicon layer exposed by the etching step.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: A single chip pad oxide layer growth process is disclosed. First, a silicon chip is sent into a reaction chamber, which is filled with hydrogen and oxygen. A rapid thermal process is employed to increase the temperature inside the chamber to about 850° C. to 1100° C. to grow a SiO2 layer. The error on the final temperature after the rapid thermal process can be controlled to fluctuate within one to two degrees.

Abstract: The present provides a method for forming a porous metal silicate dielectric layer having a dielectric constant of less than 2.0. The porous metal silicate dielectric formed by embodiments of the present invention is suitable for integration into the microelectric device manufacturing process. By carefully controlling the amount and type of surfactant used, the pore size and structure of the dielectric layer can be predetermined.

Abstract: Adhesion of high fluorine content films to semiconductor substrates may be improved by forming an intervening adherence layer. The adherence layer may be formed from a plasma gas. In some cases, the adherence layer may be used to adhere photoresist for advanced photolithography processes to silicon substrates.

Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.

Abstract: An assist pattern design method for lithography C/H process that includes the following steps: determining the exposure wavelength of a lithography machine light source; determining a minimum resolution line width by the sigma, process integration parameter and numerical aperture of the lithography machine; recovering the minimum line width on a mask according to the miniature scale of the determined minimum resolution line width; and using a line pattern smaller than the recovered minimum line width to connect multiply C/H patterns on the mask.

Abstract: Implosion-proof mesh tape is constructed by covering the surface of a mesh-like fabric matrix with a hot-melt adhesive and then coating it with a pressure-sensitive adhesive. It is thereby possible to obtain a cathode-ray tube with an implosion-proof structure wherein the surfaces of the fiber matrix directly contact with both a metal clamping band and the glass panel.

Abstract: A fire resistant textile material comprising a woven faced fabric composed of fibers selected from meta-aramid, polyamideimide and mixture thereof, the fabric including a woven mesh of strengthening fibers selected from para-aramid, polyparaphenylene terephthalamide copolymer and mixture thereof.

Abstract: Camouflage covering fabricated by the method of attaching dyed jute strands to netting, wherein the netting is placed over an individual or object to be camouflaged. The covering may be formed as an integral garment, such as a hooded poncho, or may be attached to clothing such as a battle dress uniform (BDU) to form a ghillie suit. The covering may be draped over an object such as a weapon, vehicle, equipment, or supplies. The present invention allows for quick, cost-effective creation of realistic three-dimensional camouflage coverings and apparel that are easily portable, naturally frayed in appearance, and securely assembled without the use of loops or snaps.

Abstract: The invention concerns a method for making a micaceous product capable of being impregnated preferably in the form of a mica ribbon by combining at least a support and a mica sheet. The invention is characterized in that it consists in: coating the support and the sheet with a solvent-fee resin or a mixture of solvent-free resins using several coating rollers brought to a temperature for producing the coat; combining the support with the mica sheet; subjecting them to a pressure and heat treatment.

Abstract: The present disclosure generally relates to dyed melamine fabrics and methods for dyeing melamine fabrics. In one arrangement, the fabrics comprise a plurality of melamine fibers, wherein the flame resistant fabric has been dyed through a beam dyeing process in which the fabric has not been mechanically agitated. In one arrangement, the methods comprise the steps of wrapping melamine fabric around a perforated beam of a beam dyeing machine such that several layers of fabric surround the beam, injecting dyebath into the beam so that it penetrates the fabric layers, and circulating the dyebath through the fabric layers until the fabric is dyed to a desired shade.

Abstract: Provided is a water-decomposable fibrous sheet including fibers containing at least 3% by mass of fibrillated rayon. The fibrillated rayon has a degree of beating of at most 700 cc and has primary fibers of a predetermined fiber length and microfibers extending from the primary fibers. In the fibrous sheet, the microfibers are entangled with at least either of other microfibers and other fibers therein, and the surface friction resistance of the fibrous sheet in dry, measured according to the abrasion resistance test method of JIS P-8136, is at least three rubbing cycles.

Abstract: A glass ceramic, for use as a resistor or a gas-tight glass ceramic solder for use in a spark plug, includes a fused seal of a starting glass fused from a starting mixture containing SiO2, Al2O3, TiO2 and CaO, the fused seal including crystalline phases in at least some areas. A method for producing such a glass ceramic provides for the starting glass to be processed in a first method step to form a starting material, which is heated for a first period of time in a second method step from a starting temperature, which is below the softening temperature of the starting glass, to a fusion temperature, which is above the softening temperature of the starting glass, and is kept at that temperature for a second period of time and finally is cooled again. A spark plug may include a terminal stud and a center electrode, which are electrically connected across a resistor that is formed in at least some areas by the glass ceramic.

Abstract: Extremely high solids content silica dispersions are useful for forming green bodies of near net shape as compared to the shape of the bodies after sintering. The green bodies are particularly useful for sintering to form low impurity-containing crucibles for single crystal silicon production.

Abstract: A dielectric ceramic composition including a dielectric base phase containing BaTiO3 as a main component, and plate-shaped or acicula deposition phase existing together in the dielectric base phase. Preferably, the dielectric ceramic composition includes a main component of BaTiO3, a first subcomponent including at least one compound selected from MgO, CaG, BaG, SrO and Cr2O3, a second subcomponent of (Ba, Ca)xSiO2+x (where, x=0.8 to 1.2), a third subcomponent including at least one compound selected from V2O5, MoO3, and WO3, and a fourth subcomponent including an oxide of R1 (where R1 is at least one element selected from Sc, Er, Tm, Yb, and Lu), a fifth subcomponent including an oxide of R2 (where R2 is at least one element selected from Y, Dy, Ho, Tb, Gb and Eu), wherein the ratios of the subcomponents to 100 moles of the main component of BaTiO3 are first subcomponent of 0.1 to 3 moles, second subcomponent of 2 to 10 moles, third subcomponent of 0.01 to 0.5 mole, fourth subcomponent of 0.

Abstract: A method of making a ceramic composite wherein a polymeric ceramic precursor or fiber reinforcement infiltrated with a polymeric ceramic precursor is associated with at least one metallic element to form a preceramic composite and the said composite is pyrolyzed by high frequency microwave radiation, preferably in the form of a beam, until the polymeric ceramic precursor is converted into a ceramic having the at least one metallic element integrally formed as part of said ceramic. The products obtained by such method comprising ceramic metal composites formed by pyrolyzing a preceramic composite to high frequency microwave radiation until the polymeric ceramic precursor is converted into a ceramic having at least one metallic element integrally formed as a part of said component.

Abstract: There is provided a zeolite bound zeolite catalyst which does not contain significant amount of non-zeolitic binder and can be tailored to optimize its performance and a process for converting hydrocarbons utilizing the zeolite bound zeolite catalyst. The zeolite bound zeolite catalyst comprises core crystals containing first crystals of a first zeolite and optionally second crystals of a second zeolite having a composition, structure type, or both that is different from said first zeolite and binder crystals containing third crystals of a third zeolite and optionally fourth crystals of a fourth zeolite having a composition, structure type, or both that is different from said third zeolite. If the core crystals do not contain the second crystals of the second zeolite, then the binder crystals must contain the fourth crystals of the fourth zeolite. The zeolite bound zeolite finds application in hydrocarbon conversion processes, e.g.

Abstract: Epoxidation catalyst based on titanium zeolite in the form of extruded granules. Use of this catalyst in the synthesis of epoxides, preferably 1,2-epoxy-3-chloropropane or 1,2-epoxypropane, by reacting an olefinic compound, preferably allyl chloride or propylene, with a peroxide compound, preferably hydrogen peroxide. Process for the preparation of an epoxide, preferably 1,2-epoxy-3-chloropropane or 1,2-epoxypropane, by reacting an olefinic compound, preferably allyl chloride or propylene, with a peroxide compound, preferably hydrogen peroxide, in the presence of the aforementioned catalyst.

Abstract: A catalyst composition that is the combination of or the reaction product of ingredients comprising (a) an lanthanide compound, (b) an alkylating agent, (c) a nickel-containing compound, and optionally (d) a halogen-containing compound, with the proviso that the halogen-containing compound must be present where none of the lanthanide compound, the alkylating agent, and the nickel-containing compound contain a labile halogen atom.

Abstract: The present invention relates to catalysts particularly suitable for the sterospecific polymermerization of olefins, comprising Ti, Mg, halogen and an electron donor compound selected from heteroatoms containing esters of malonic acids. Polymers produced by the catalysts have high isotactic index expressed in terms of high xylene insolubility.

Abstract: A noble metal catalyst supported on boron nitride (BN) is used for the deep oxidation of organic compounds. The superior activity of the catalyst provides an extreme low light-off temperature and a short induction period at the deep oxidation reaction of organic compounds in air stream. The catalyst outperforms the traditional oxide-supported Pt catalysts with respect to the life and activity. The specific surface area of BN ranges from 1 to 100 m2/g, and the loading of the noble metal is in the range of 0.1 to 5.0 wt %. The noble metal can be selected from a group consisting of platinum (Pt), palladium (Pd), rhodium (Rh), Ruthenium (Ru) and a mixture thereof.

Abstract: A heat-sensitive recording material in which a heat-sensitive color-developing layer containing at least an electron-donating colorless dye, an electron-accepting compound, a sensitizer and preferably an image stabilizer is disposed on a support, the heat-sensitive color-developing layer containing (1) 4-hydroxybenzenesulfonanilide as the electron-accepting compound and (2) 2-benzyloxynaphthalene and ethylenebisstearic acid amide or methylolstearic acid amide as the sensitizer, and (3) the 2-benzyloxynaphthalene (x) to ethylenebisstearic acid amide or methylolstearic acid amide (y) mass ratio (x/y) being within 95/5 to 40/60 range.

Abstract: A thermal transfer recording sheet having a high resistance to denting due to the nipping pressure and/or thermal printing pressure has a substrate sheet including a core sheet and polyester films laminated on the two surfaces of the core sheet and an image receiving layer formed on a surface of the substrate sheet and containing a dyeable polymeric material, and exhibits a compression modulus of 50 MPa or less.

Abstract: Novel trifluoromethylpyrrolcarboxamides of the formula (I) wherein R1, R2, and A are as defined in the specification, which are suitable for protecting plants against infestations by phytopathogenic microorganisms.

Abstract: A superconductor having at least one Hg—M—Cu—O (M=Ba, Sr and/or Ca) superconducting film provided on a substrate and having a thickness of between 300 Å to 950 Å. The superconductor may be prepared by forming, on a substrate, a precursor laminate composed of a first, M—Cu—O film and a second, Hg—O film. The precursor laminate film-bearing substrate is placed in a closed vacuum chamber together with a first pellet of HgO, MO and CuO and a second pellet of MO and CuO. The contents in the chamber are heated to form, on the substrate, a superconducting Hg—M—Cu—O film. The thickness of the first M—Cu—O film of the precursor is controlled so that the thickness of the superconducting Hg—M—Cu—O film is in the range of between 300 Å to 950 Å.

Abstract: The present invention concerns the improvement of the supercurrent carrying capabilities, i.e. the increase of critical current densities, of bicrystalline or polycrystalline superconductor structures, especially of high-Tc superconductors. By providing an appropriate predetermined dopant profile across the superconductor structure, in particular within or in the vicinity of the grain boundaries, the space-charge layers at the grain boundaries are reduced and thereby the current transport properties of the superconductor significantly improved. Simultaneously, the influence of magnetic fields on the critical current densities is significantly reduced, which in turn enhances the overall supercurrent carrying capabilities while keeping the supercurrent transport properties of the grains at good values.

Abstract: A Nb3Al superconducting wire and method for fabricating the same wherein Nb and Al powders in combination, or Nb—Al alloy powders are encapsulated in a metal tube, preferably copper or copper-alloy (e.g., CuNi), and the resultant composite is processed by conventional means to fine wire. Multifilamentary composites are produced by rebundling of the powder-filled wires into metal tubes followed by conventional processing to wire of a desired size. It is required for the use of Nb and Al powders in combination that the Nb and Al powder particle size be less than 100 nm. In the use of Nb—Al alloy powders, it is preferred, but not required, that the powder particle size be similarly of a nanometer scale. The use of nanometer-scale powders is beneficial to wire fabrication, allowing the production of long wire piece-lengths. At final wire size, the wires produced by practice of the present invention are heat treated at temperatures below the melting point of copper (1083° C.

Abstract: Sulfated dicarboxylic acids, amine salts thereof, or inorganic salts thereof may be used in various applications, including use as corrosion-inhibiting additives (e.g., in oil-field drilling applications and in metalworking applications), as emulsifiers (e.g., in metalworking applications), and as lubricity-enhancing additives (e.g., in metalworking applications).