Abstract: In fast imaging of a multi-echo method represented by a fast spin echo (FSE) method, a pulse sequence is arranged such that a basic condition relating to a CPMG method is satisfied and a spoiler gradient magnetic field pulse is independently applied immediately after a flop pulse. The spoiler gradient magnetic field pulse for suppressing an undesired signal is applied by a predetermined amount or more so as to prevent superimposition of other gradient magnetic field components such as a phase encoding component, a rewind component, etc., and to prevent a residual component of an FID signal caused by a certain RF pulse from being refocused by a subsequent RF pulse.

Abstract: To correct static magnetic field intensity and homogeneity of an MRI system, B0 correction coil driving power sources respectively supply correction electric currents to B0 correction coils added to a pair of pillar yokes at the position where an imaging region is interposed therebetween, and the pair of B0 correction coils produce correction magnetic fields in which at least one of the direction and intensity is different, which are then applied to static magnetic fields produced by permanent magnets.

Abstract: A shim device for a magnetic resonance apparatus has a cavity for the acceptance of shim elements, the cavity being arranged in an antenna conductor.

Abstract: A magnetic resonance imaging coil structure includes a main magnetic field generating magnet, a gradient magnetic field generating coil, a shield, a magnetic field correcting shim plate and a transmission coil stacked in this order. At least the shield and the transmission coil are integrally formed with a joint portion made of a material including FRP that maintains a constant distance between the shield and the transmission coil.

Abstract: An NMR method of analyzing an analyte comprises feeding an analyte sample fluid to an NMR flow cell. The NMR flow cell comprises an RF microcoil operably associated with an enlarged containment region. The mobile phase of the analyte sample flowing through the NMR flow cell has a solvent gradient greater than 10% per minute. The analyte sample fluid can be fed to the NMR flow cell from an analyte extraction chamber, e.g., operative to perform liquid chromatography, capillary electrophoresis, or the like, especially a capillary-based analyte extraction chamber integrated in an NMR probe with the NMR flow cell. A sample volume is held in the NMR flow cell for equilibration less than 1 hour, preferably less than 30 minutes prior to actuating NMR analysis of the observe volume in the microcoil.

Abstract: To locate via electromagnetic signaling each of a plurality of buried side leg conveyances (141-146) coupled to a common underground backbone conveyance (12), a cable locating signal generator (17) applies a plurality of different frequency conveyance locating signals to the backbone conveyance. A separate one of a plurality of filter arrestors (181-186) selective passes a particular one of the plurality of different frequency locating signals onto a corresponding one of the side leg conveyances. In this way, each side leg conveyance carries only a particular frequency locating signal whose strength remains unaffected by the locating signal on the other side leg conveyances.

Abstract: An apparatus for locating a target object using parametric inversion employs a signal injector capable of injecting a signal into the target object, wherein at least a portion of the target object is buried, a magnetic field receiver, a matching processor for matching to a magnetic field received by the magnetic field receiver a parametric magnetic field distribution model corresponding to the target object and at least one other object, and a locating processor for locating the target object using parameters from the parametric magnetic field distribution model.

Abstract: An interrogation of a switched state of a switch is carried out with a high interrogation current until a closed switch is detected. The following interrogations of the switched state are then carried out with a low interrogation current until a definable time period which runs starting from a detection of the closed switch or until a definable number of interrogations which is counted starting from the detection of the closed switch is exceeded. After the expiry of the time period or the number of interrogations, the interrogation is continued with the high interrogation current until a closed switch state of the switch is detected again.

Abstract: A method of detecting and resolving a memory effect capable of detecting the memory effect with ease and with high precision and resolving even when the vehicle is in motion is provided. A current in a secondary battery is detected, a variation &Dgr;SOC in a residual battery capacity for a predetermined time period is calculated according to at least current integration by multiplying the detected current by a predetermined charge efficiency (S302), a temperature of the secondary battery is detected and a variation &Dgr;V in a no-load voltage for the predetermined time period is calculated based on the detected current, and an internal resistance corresponding to the detected temperature and the SOC is calculated (S303). A ratio k of the variation in the no-load voltage to the variation in the residual battery capacity is calculated (S304).

Abstract: A power source device comprises a cell unit 12 comprising a plurality of cells 12a. Connected between a positive side terminal and a negative side terminal of the cell unit 12 is a first current line 34 having two voltage dividing resistors 30, 32 interposed therebetween, and is a second current line 22 having two protection resistors 14, 16 and two detection resistors 18, 20 interposed therebetween. An intermediate point 24 of the second line 22 is grounded to a grounding 26 via an insulation resistor 28. The voltage difference between a voltage (V1, V2) detected by the detection resistors 18, 20 and a reference voltage (Vc) obtained from a point of connection 35 between the voltage dividing resistors is input to two Op-Amps 36, 38 serving as the input voltage (V1IN, V2IN). Based on the output voltage (V1OUT, V2OUT) obtained from the Op-Amps 36, 38, leakage occurrence is detected.

Abstract: The present invention provides a device for in-situ measurement and recording of various environmental parameters in a semiconductor fabrication process. The device comprises sensors for detecting the parameters and converting them to sensor outputs; and a data logger coupled to the sensors for receiving the sensor outputs and logging them in a file. The device may also comprise an analog to digital converter to convert the sensor outputs to digital data and a communication module to communicate the digital data with other devices. When applied to reticles used in a semiconductor fabrication process comprising a plurality of stages, the device may be used to monitor electrostatic field and electrostatic discharge activities on and around the reticle, convert the monitored parameters into data, and log the data along with a timestamp and an identification of each individual stage.

Abstract: If there is an error in the feeding system and the error condition allows the motor vehicle to run, the power to electric load systems having a low priority is cut off. If the error condition does not allow the motor vehicle to run, the power to all electric loads is cut off. If there is an error in an electric load system having a high priority, the power to all electric loads is cut off. If there is an error in an electric load system having a low priority, the power to this electric load is cut off.

Abstract: The present invention synthesizes a prescribed impedance. The impedance is synthesized by generating a current having a value substantially equal to a voltage divided by a prescribed impedance. Sensing the line voltage and converting that sensed line voltage to its digital equivalent accomplish this first step. The digital line voltage is processed by a factor related to the prescribed impedance to produce an output voltage that has a value substantially equal to the sensed voltage divided by the prescribed impedance. The output voltage controls a voltage to current converter that generates the appropriate current across the points or terminals where the line voltage was measured. Thus, the prescribed impedance is generated across these points or terminals because the line voltage divided by the generated current is substantially equal to the prescribed impedance.

Abstract: An EMI testing scheme involves analyzing an analog input signal in frequency band segments. The input signal is passband filtered and digitally sampled before being converted to a complex analytic signal via a Hilbert transform filter and then transformed into a frequency domain signal via a Discrete Fourier Transform (DFT). Pre-stored frequency window filters are then applied to the frequency domain signal. The set of discrete filter sample points which form the window filters are designed such that particular frequency sub-bands of a desired bandwidth within the frequency segment are selected for EMI analysis. By applying different frequency window filters to the frequency domain signal, different frequency sub-bands are sequentially selected for analysis. An inverse DFT transforms the filtered signal back to the time domain, and the peak voltage of the time domain signal is compared with a threshold to determine whether EMI levels within the selected sub-band are acceptable.

Abstract: This invention discloses an apparatus and method of determining the temperature of the core of an inductive coil sensor so that the effective inductance of the coil sensor can be temperature compensated to thereby provide an accurate measure of the level of fuel in a tank. The method comprises energizing the sensor with a prescribed voltage, de-energizing the sensor, measuring the resultant voltage across the sensor, and determining the core temperature from the measured resultant voltage across the sensor.

Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: A distance measuring system (1) is provided with a capacitive sensor (7a, 7b), designed in the form of a differential capacitor (18), for which the partial capacitors (C1, C2 have capacitances that depend on the position to be determined. The system also includes a processing device (5) for determining the desired distance that contains, for example, a sigma/delta demodulator. The partial capacitors (C1, C2) are triggered periodically with binary signals, wherein the trigger signals from the one partial capacitor (C1) are transmitted with a phase offset to the signals from the other partial capacitor (C2). The processing device (5) determines which trigger signals must be used for the evaluation. Within time windows that are synchronized with the edges of the trigger signals, a switch unit (22) allows the associated receiving signals to pass through to the processing unit (5) and blanks out all other signals.

Abstract: A circuit and system for sensing and measuring the mutual capacitance between a sensor capacitor having one grounded lead and a target and providing a direct digital output of the measured capacitance is disclosed. The circuit and system includes a relaxation oscillator coupled to a sensor capacitor and a fixed resistor. The fixed resistor and the sensor capacitor in conjunction with the relaxation oscillator provide a time varying output signal that has a period that is proportional to the mutual capacitance of the sensor capacitor and a target and resistance of the fixed resistor. The circuit and system can also include circuitry to compensate for the input capacitance of one or more amplifiers used in the relaxation oscillator. The circuit and system can also include circuitry to effectively increase the resistance of the fixed resistor by a predetermined constant.

Abstract: A capacitive sensor assembly is disclosed. In an exemplary embodiment, the assembly includes a capacitive strip having an elongated body for flexible mounting to a panel along a bottom surface of the elongated body. A first elongated planar conductor is contained within an upper section of the elongated body, while a longitudinal cavity is formed through a central portion of the elongated body. The longitudinal cavity is disposed between the planar conductor and the bottom surface. A capacitance detector module is inserted within the longitudinal cavity, the capacitance detector module including a capacitance detector circuit therein that is coupled to the first elongated planar conductor.

Abstract: A device (10) for use in monitoring or measuring properties of a moving bed (11) of particulate material includes a sled (12) that rides or floats on the top surface (15) of the moving bed (11). A mounting structure (14) holds the sled (12) stationary with respect to the linear movement of the particulate bed (11), but permits movement of the sled (12) in a direction perpendicular to the movement of the bed (11), such as up and down when the bed (11) is moving horizontally. The sled (12) can carry on board sensors (76) to monitor the particulate material properties. Other sensors (72, 54) can be located remote from the sled (12) such as a sensor (54) to indicate displacement of the sled (12) in a direction perpendicular to the direction of travel of the moving bed (11). In one embodiment, the device includes a flume-like collector that directs particulate material through a sampling cell comprised of parallel side walls (47, 48) with the sensor sled (12) located between the sidewalls.

Abstract: A soil moisture indicator device for alerting a user when the soil in a pot needs to be watered to sustain a plant. The soil moisture indicator device includes a body member having a first end and a second end. The first end of the body member is designed for being inserted into the soil of the pot. A sensing elements is designed for sensing the relative moisture of the soil in at the pot. The sensing elements is positioned in the body member whereby the sensing elements is designed for being submerged into the soil when the body member is inserted into the soil. A low moisture light is operationally coupled to the sensing elements. The low moisture light emits light when the sensing elements detects the moisture in the soil being greater than a predetermined dry level.

Abstract: A method and apparatus for a micromachine relay is provided. A pin controller comprises at least one spring pin designed to movably couple the pin controller to a device under test (DUT) to provide signals to the DUT. The pin controller further includes a micromachine relay coupled to the at least one spring pin to control the movement of the at least one spring pin and an integrated circuit for controlling the micromachine relay.

Abstract: The invention relates to a probe assembly for a wafer probe station having a probe holder and a replaceable probe tip. The probe holder is triaxially configured with a laterally extending center signal conductor, an intermediate guard conductor extending along the length of the center conductor and spaced radially therefrom by a tubular insulator member, and an outer shield member extending along a portion of the guard conductor and spaced radially therefrom by a second tubular insulator member. A coaxially configured probe tip has a center conductor extending to a probe point and a guard conductor radially spaced from the center conductor by an intermediate insulator. A releasable connection provides a rigid attachment between the probe tip and the probe holder and provides electrical interfaces between the center and guard conductors thereof.

Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) overlying a substrate of the wafer; biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed; determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter; biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

Abstract: A constant detecting apparatus 15 comprising a detecting unit 26 and a calculating unit 27. The detecting unit 26 is structured comprising a rotation sensor 41, a torque sensor 42, a position sensor 43, a rotor temperature sensor 44, a winding temperature sensor 45, a phase voltage detector 46, and phase current detectors 47 and 47. The calculating unit 27 calculates the induced voltage constant Ke that changes depending on the motor temperature Tmag while the motor 11 is being driven based on each of the detected signals from the detecting unit 26, and at the same time, the d axis current Id and the q axis current Iq are calculated after elimination of the iron loss, and the d axis inductance Ld and the q axis inductance Lq in the actual operating state of the motor 11 are calculated.

Abstract: There is disclosed a reduced noise line driver for driving a signal line in an integrated circuit. The reduced-noise line driver comprises: 1) an N-type transistor having a source coupled to ground and a drain coupled to the signal line; 2) a P-type transistor having a source coupled to a power supply rail and a drain coupled to the signal line; 3) a first controller having an input for receiving an incoming signal and an output coupled to a gate of the N-type transistor; and 4) a second controller having an input for receiving the incoming signal and an output coupled to a gate of the P-type transistor, wherein the first controller and the second controller selectively switch the N-type transistor and the P-type transistor ON and OFF such that the N-type transistor and the P-type transistor are never ON simultaneously.

Abstract: There is provided an output control circuit provided in an integrated circuit that enables any arbitrary internal signal to be specified and output from any output terminal, and hence enable the monitoring of a large number of internal signals even if only a small number of output terminals are provided. A plurality of external output terminals output a plurality of signals existing in the integrated circuit. A plurality of signal output circuits are provided, to which the plurality of internal signals are mutually input. Each of the signal output circuits comprises a signal group select circuit that selects a predetermined signal group from the plurality of internal signals, a logic circuit that carries out logical operations on the selected signal group, and an external output circuit that outputs signals resulting from the logical operations via one of the external output terminals.

Abstract: Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Abstract: An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column.

Abstract: A logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit 12 for receiving a first logic signal A and a second logic signal B taking a logic “1” or “0” and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit 11 for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B, and an interpolation circuit 13 for compulsorily setting the output level of the dual signal at the level of the logic “1” when the output level of the exclusive-OR is the logic “0”, while compulsorily setting the output level of the exclusive-OR at the level of the

Abstract: This three-valued inverter includes first and second P-channel MOS transistors connected in series between a line of a first power supply potential and an output node, and each having a gate receiving a first signal; third and fourth P-channel MOS transistors connected in series between a line of a second power supply potential and the output node, and each having a gate receiving a second signal; and an N-channel MOS transistor connected between the output node and a line of a ground potential, and having a gate receiving a third signal. Back gates of the first and third P-channel MOS transistors are applied with the first power supply potential and the second power supply potential, respectively, and back gates of the second and fourth P-channel MOS transistors are both connected to the output node. Therefore, even in a power-up period or the like, no latch-up occurs.

Abstract: An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage that is less than the external power supply and greater than the internal power supply; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data.

Abstract: The data transmission circuit has a test mode for offsetting variation of crossover voltages of the first and second data signals, which rises from threshold voltage distribution of plural transistors embedded in a transceiver. The transceiver converts an external test clock signal into the first and second data signals to be transferred to the first and second data lines, setting the first and second data signals with predetermined delay times. The delay times of the first and second data signals are adjusted when those crossover voltages deviate from a predetermined range, so that the crossover voltages of bus-specific data signals generated from the USB low-speed transceiver are always positioned within a normal range.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit contains a pipeline comprised of a number of stages of domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage. The present stage includes a control circuit that is configured to ensure that the present stage enters a precharging state before entering an evaluation state—in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit operates by receiving a prior control signal from the prior stage and sending a present control signal to the next stage. During this process, the control circuit ensures that a minimum cycle time between successive evaluation states is six gate delays.

Abstract: An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

Abstract: The invention provides a semiconductor device which can efficiently suppress current consumption arising from a band to band tunneling phenomenon without causing a drop of the operation speed of the circuit. A NAND circuit includes, as a MOS transistor which is controlled to an off state while a predetermined potential difference is provided between the gate and the drain thereof, an n-type MOS transistor which has a band to band leak preventing countermeasure applied to the drain thereof. Consequently, even if an input signal to the MOS transistor exhibits the L level in the standby mode and the n-type MOS transistor is placed in a state wherein band to band leak can occur, occurrence of band to band leak is suppressed in the n-type MOS transistor.

Abstract: A symmetric current mode logic with symmetric input loads as well as identical input logic levels at the input terminals so as to prevent phase error due to level adjustment and to further avoid signal surges due to current steering by parallel switching.

Abstract: A double phase comparator sets both first and second signals to an “L” level in order to delay a phase of a feedback clock signal when the feedback clock signal is at the “H” level and the “L” level at the rising and falling edges of an internal clock signal, respectively. The double phase comparator also sets both first and third signals to the “L” levels in order to advance a phase of a feedback clock signal when the feedback clock signal is at the “L” level and the “H” level at the rising and falling edges of an internal clock signal, respectively. Moreover, the double phase comparator sets the first signal to the “H” level in order to stop a phase control of the feedback clock signal when the feedback clock signal is at the same level at the rising and falling edges of an internal clock signal.

Abstract: A sense amplifier that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output. The sense amplifier has two feedback paths including a first feedback path having a transistor with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path for providing voltage swing control. In the first operating mode, the “turbo” mode, both feedback paths are in operation to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the “non-turbo” mode, only the first feedback path is in operation which allows for greater stability and a reduction in power consumption.

Abstract: An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements.

Abstract: A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: A driving circuit for outputting high-frequency signal. The first NMOS transistor includes a first drain coupled to a first voltage level, a first gate coupled to the output terminal of the first operational amplifier and a first source coupled to the input terminal of the first operational amplifier. The first PMOS transistor includes a second drain coupled to a second voltage level, a second gate coupled to the output terminal of the second operational amplifier and a second source coupled to the input terminal of the second operational amplifier. The matching resistor having a predetermined resistance is coupled between the first source and the second source. The second NMOS transistor includes a third drain coupled to the first voltage level, a third gate coupled to the output terminal of the first operational amplifier and a third source.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal.

Abstract: The present invention provides an apparatus for increasing the slew rate. The apparatus for increasing the slew rate comprises an operational amplifier and a push-pull output stage. The present invention is operated under the principle of when there is a big difference between the output signal and the input signal, either the pull-up transistor or the pull-down transistor in the push-pull output stage is ON, so that the pushed or pulled current is provided to a load on the output terminal. When the difference between the output signal and the input signal becomes smaller, the operation of the push-pull output stage stops, and the load on the output terminal is directly driven by the operational amplifier at this time. Since the present invention only deploys an operational amplifier and a push-pull output stage and does not deploy error amplifier, the present invention reduces occupied area and saves consumed power, and also avoids offset voltage and oscillation problems.

Abstract: A circuit for controlling pulse width of a signal for driving a light emitting element, includes a pulse width control circuit capable of responding to multi-bit rates in the same circuit structure. For this purpose, the pulse width control circuit has a Tr/Tf control section controlling at least one of a rise time Tr and a fall time Tf of an input signal according to the bit rate of the input signal; a waveform shaping section shaping a signal output from the Tr/Tf control section to generate an output signal; and a control signal generating section generating a control signal for controlling an operation of the Tr/Tf control section based on pulse width control information.

Abstract: An input buffer for an optical receiver or transceiver which provides symmetrical hysteresis and zero static current, comprises two field effect transistors (FETs) which form the basic buffer logic circuit, two FETs which respectively provide offset voltages to the buffer logic FETs, and two FETs which provide positive feedback. In the preferred embodiment the input buffer provides multiple-channels, each channel comprising a component inverter designed to provide zero static current and symmetrical hysteresis for a different input signal mode.