Patents Issued in March 2, 2004
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Patent number: 6700175Abstract: There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n−-type semiconductor region and a p−-type semiconductor region are arranged alternately without filling trenches by epitaxial growth. A p−-type silicon layer (13) which becomes a p−-type semiconductor region (12) is formed. An n−-type semiconductor region (11) is formed by diffusing n-type impurities into the p−-type silicon layer (13) through the sidewalls of first trenches (22) formed in the p−-type silicon layer (13).Type: GrantFiled: December 31, 2001Date of Patent: March 2, 2004Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Masahito Kodama, Tsutomu Uesugi
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Patent number: 6700176Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: GrantFiled: July 18, 2002Date of Patent: March 2, 2004Assignee: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
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Patent number: 6700177Abstract: In a surface-mounting-type electronic-circuit unit, circuit elements, including capacitors, resistors, and inductive devices, and electrically conductive patterns connected to the circuit elements are formed on an alumina board as thin films. Semiconductor bare chips for a diode and a transistor are wire-bonded to connection lands in electrically conductive patterns. And end-face electrodes connected to grounding electrodes, input electrodes, and output electrodes of electrically conductive patterns are formed at side faces of the alumina board.Type: GrantFiled: May 29, 2001Date of Patent: March 2, 2004Assignee: Alps Electric Co., Ltd.Inventors: Akiyuki Yoshisato, Kazuhiko Ueda, Hiroshi Sakuma, Akihiko Inoue
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Patent number: 6700178Abstract: A chip with beveled edges suitable for adhering onto a surface of a die pad by an adhesive material. The chip has an active surface and a corresponding back surface, wherein the active surface has beveled edges. The back surface of the chip is adhered onto the surface of the die pad by the adhesive material.Type: GrantFiled: April 19, 2001Date of Patent: March 2, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jian-Cheng Chen, Wei-Min Hsiao
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Patent number: 6700179Abstract: The state of a surface of a substrate 11 or a GaN group compound semiconductor film 12 formed on the substrate 11 is modified with an anti-surfactant material and a GaN group compound semiconductor material is supplied by a vapor phase growth method to form dot structures made of the GaN group compound semiconductor on the surface of the semiconductor film 12, and the growth is continued until the dot structures join and the surface becomes flat. In this case, the dot structures join while forming a cavity 21 on an anti-surfactant region. A dislocation line 22 extending from the underlayer is blocked by the cavity 21, and therefore, the dislocation density of an epitaxial film surface can be reduced. As a result, the dislocation density of the GaN group compound semiconductor crystal can be reduced without using a masking material in the epitaxial growth, whereby a high quality epitaxial film can be obtained.Type: GrantFiled: December 18, 2001Date of Patent: March 2, 2004Assignee: Mitsubishi Cable Industries, Ltd.Inventors: Yoichiro Ouchi, Hiroaki Okagawa, Masahiro Koto, Kazuyuki Tadatomo
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Patent number: 6700180Abstract: A semiconductor diode has a low bandgap layer (10) and an intermediate region (4) with a plurality of field relief regions (6, 8) extending between the low bandgap layer (10) and a first region (2) of opposite conductivity type. The field relief regions deplete the intermediate region in the off state of the diode.Type: GrantFiled: November 26, 2002Date of Patent: March 2, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Eddie Huang
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Patent number: 6700181Abstract: A method and system for broadband transition between an integrated circuit (IC) package and a printed wiring board (PWB). A vertical quasi-coaxial cable structure is created connecting the transmission line inside the package to the transmission line on the PWB. The solder ball is eliminated and replaced with ad hoc layout on the bottom of the package, with mating layout on the top layer of the PWB. Complete transition from package to PWB is considered, giving particular attention not only to the impedance of the lines and the transition but also to the continuity of the current flow along the signal path.Type: GrantFiled: November 19, 2002Date of Patent: March 2, 2004Assignee: Inphi CorporationInventor: Roberto Coccioli
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Thermally conductive substrate, thermally conductive substrate manufacturing method and power module
Patent number: 6700182Abstract: By providing an end portion of a radiation plate located on and near an end portion of an insulator sheet, to which a lead frame extends, at a position away from the end portion of the insulator sheet inside of the insulator sheet in a plane direction of the insulator sheet, it is possible to secure a creeping distance between the lead frame and the radiation plate without decreasing a lead frame area on which components can be actually mounted.Type: GrantFiled: June 1, 2001Date of Patent: March 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Yamashita, Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo -
Patent number: 6700183Abstract: An apparatus and method is provided for forming a board-on-chip (BOC) package. An adhesive material including a carrier and microcapsules distributed in the carrier is used to bond a semiconductor component to a mounting surface in a BOC package. The microcapsules contain a hardener and/or a catalyst that, when combined with the carrier, initiate a bonding reaction. The contents of the microcapsules are released via application of an external influence, such as pressure or heat, when the bonding reaction is desired to begin. The use of microcapsules permits the formulation of adhesive blends with a substantially increased pot life, increased stability and reliability at high temperatures, and favorable low temperature reaction and bonding characteristics.Type: GrantFiled: December 6, 2001Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventor: Tongbi Jiang
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Patent number: 6700184Abstract: There is provided a semiconductor device and a lead frame that form a stable external ring structure wherein bonding strength and mechanical strength between the external ring and sealing resin is improved. A semiconductor device (1) is formed which comprises a semiconductor chip (2) having a plurality of electrode pads (3) formed at the periphery of a front surface thereof, a wiring film (5) located and formed on the front surface side of the semiconductor chip (2) by laminating an insulation film (7) on a lead pattern (6), outer connection terminals (8) formed so as to protrude above the wiring film (5), a plurality of leads (9) extending form the wiring film (5) and connected to the electrode pads (3) on the semiconductor chip (2) at extended tip ends thereof, an external ring (11) provided so as to surround the semiconductor chip (2) and formed with a plurality of through holes or blind holes (15), and a sealing resin (12) filled between the semiconductor chip (2) and the external ring (11).Type: GrantFiled: January 20, 1998Date of Patent: March 2, 2004Assignee: Sony CorporationInventors: Kenji Osawa, Haruhiko Makino
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Patent number: 6700185Abstract: An adhesive film for semiconductor, which comprises at least one resin layer, and, after bonded to a lead frame, has at 25° C. a 90°-peel strength of at least 5 N/m between the resin layer and the lead frame, and, after a lead frame is bonded to the adhesive film for semiconductor and sealed with a sealing material, has at least at one point of temperatures ranging from 0 to 250° C. a 90°-peel strength of at most 1000 N/m between the resin layer and each of the lead frame and the sealing material; a lead frame and a semiconductor device using the adhesive film for semiconductor; and a method of producing a semiconductor device.Type: GrantFiled: April 23, 2002Date of Patent: March 2, 2004Assignee: Hitachi Chemical Co., Ltd.Inventors: Toshiyasu Kawai, Hidekazu Matsuura
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Patent number: 6700186Abstract: A lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semiconductor chip and at least one lead space from the support. The sheet has a tie bar network which connects a) the support to the at least one lead on each of the first and second lead frames and b) the first and second lead frames, each to the other. The sheet has a dividing line along which the sheet can be cut to separate the first and second lead frames from each other. The tie bar network consists of at least one tie bar extending along a substantial length of the dividing line. The support has a first thickness between the oppositely facing sides of the sheet. The at least one tie bar has a second thickness between the oppositely facing sides of the sheet over a substantial length of the dividing line that is less than the first thickness.Type: GrantFiled: December 17, 2001Date of Patent: March 2, 2004Assignee: Mitsui High-tec, Inc.Inventors: Shoshi Yasunaga, Hideshi Hanada, Takahiro Ishibashi, Jun Sugimoto, Yuichi Dohki, Hitoshi Etoh
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Patent number: 6700187Abstract: A semiconductor package comprising a semiconductor die having opposed, generally planar first and second surfaces and a peripheral edge. Formed on the second surface of the semiconductor die in close proximity to the peripheral edge thereof are a plurality of bond pads. The semiconductor package further comprises a plurality of leads which are positioned about the peripheral edge of the semiconductor die in spaced relation to the second surface thereof. Each of the leads includes opposed, generally planar first and second surfaces, and a generally planar third surface which is oriented between the first and second surfaces in opposed relation to a portion of the second surface. In the semiconductor package, a plurality of conductive bumps are used to electrically and mechanically connect the bond pads of the semiconductor die to the third surfaces of respective ones of the leads. An encapsulating portion is applied to and partially encapsulates the leads, the semiconductor die, and the conductive bumps.Type: GrantFiled: March 21, 2002Date of Patent: March 2, 2004Assignee: Amkor Technology, Inc.Inventor: Jong Sik Paek
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Patent number: 6700188Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.Type: GrantFiled: May 15, 2001Date of Patent: March 2, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chun Hung Lin
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Patent number: 6700189Abstract: A semiconductor device in which a lead frame having inner connecting portions and outer connecting portions, a semiconductor chip having electrodes on the surface thereof, and metal wires for electrically connecting electrodes on the semiconductor chip and the inner connecting portions of the lead frame are sealed with a sealing resin. The bottom side of the sealing resin of the inner connecting portion is covered with an inner connecting portion sealing resin.Type: GrantFiled: October 4, 2001Date of Patent: March 2, 2004Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
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Patent number: 6700190Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; and 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed.Type: GrantFiled: July 26, 2002Date of Patent: March 2, 2004Assignee: STMicroelectronics, Inc.Inventors: Harry M. Siegel, Anthony M. Chiu
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Patent number: 6700191Abstract: An electronic power circuit includes several power modules (1) and is especially for controlling an electrical machine. Each power module (1) includes a plate-shaped integrated electronic circuit arrangement (2) having several electrical terminals. A perpendicular bent-over electrically conducting side leg (3) is arranged on each of two opposite-lying sides of the plate-shaped circuit arrangement (2). The side leg (3) forms an electrical contact and, in this way, the power module (1) has a U-shaped cross section. Each side leg (3) is provided with connecting elements via which two or several power modules (1) can be electrically and mechanically fixedly connected to each other while forming a mutual spacing between the plate-shaped circuit arrangement (2) via the side legs (3) for forming the electronic power circuit.Type: GrantFiled: March 22, 2002Date of Patent: March 2, 2004Assignee: Continental ISAD Electronic Systems GmbH & Co. OHGInventors: Ralf Schmid, Marco Schmidt, Johann Sontheim, Helmut Perkounigg
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Patent number: 6700192Abstract: A leadframe used for a leadless package (a semiconductor device) such as a quad flat non-leaded package (QFN) includes a die-pad portion disposed in a center of an opening defined by a frame portion, and a plurality of lead portions extending from the frame portion toward the die-pad portion in a comb shape. A lead width of a portion along a circumference of a region to be ultimately divided as a semiconductor device, of each of the lead portions, is formed narrower than that of the other portion of the corresponding lead portions. In the leadframe, a plurality of die-pad portions are disposed, the frame portion is provided so as to surround each of the die-pad portions, and a plurality of lead portions corresponding to each of the die-pad portions extend from the frame portion surrounding the corresponding die-pad portion toward the corresponding die-pad portion. Moreover, an adhesive tape is attached to one surface of the leadframe.Type: GrantFiled: October 7, 2002Date of Patent: March 2, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Matsuzawa, Shintaro Hayashi
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Patent number: 6700193Abstract: The semiconductor device includes tub 5 that is smaller than semiconductor chip 8, and which supports semiconductor chip 8; molded section 12 that is formed by resin-molding around semiconductor chip 8; suspension leads 4, including supporting portions 4a that support tub 5 and exposed portions 4b that are connected to supporting portions 4a and are exposed on back surface 12a of molded section 12, and are elevation processed in supporting portions 4a; leads 2 that are located around tub 5; and wires 10 that connect pads 7 of semiconductor chip 8 with the corresponding leads 2; wherein the thickness of tub 5 and supporting portions 4a of suspension leads 4 is less than the thickness of exposed portions 4b, and back surface 8b of semiconductor chip 8 is firmly in contact with molding resin 11.Type: GrantFiled: November 20, 2001Date of Patent: March 2, 2004Assignees: Renesas Technology Corporation, Hitachi Yonezawa Electronics Co., Ltd.Inventor: Yoshihiko Shimanuki
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Patent number: 6700194Abstract: A semiconductor device which satisfies both the requirements for radiation performance and for miniaturization while having a semiconductor element for a heavy current. The semiconductor device has an IGBT element (1) and diode element (2) which are provided on the main surface of the heat spreader (25) in a strip form formed of a metal with excellent heat conductivity and electricity conductivity. In addition, a relay terminal block (20) is provided outside of the IGBT element (1) on the main surface of the heat spreader (25) and the relay terminal block (20), the IGBT element (1) and the diode element (2) are aligned. Then, the external connection electrode plates (81) and (82) are, respectively, provided on both sides of this alignment.Type: GrantFiled: March 29, 2002Date of Patent: March 2, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Dai Nakajima, Hideaki Chuma
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Patent number: 6700195Abstract: An electronic assembly for conducting heat from a semiconductor device, such as a power flip chip, attached to a substrate. The substrate has a first region with conductors thereon, a second region surrounding and supporting the first region, and a third region surrounding and supporting the second region, with the second region being more flexible than the first and third regions. The chip is mounted to the first region of the substrate, and has solder connections on a first surface thereof that are registered with the conductors on the first region of the substrate. A heat-conductive member thermally contacts a second surface of the chip oppositely disposed from the first surface. A biasing element contacts the first region of the substrate to bias the chip into thermal contact with the heat-conductive member.Type: GrantFiled: March 26, 2003Date of Patent: March 2, 2004Assignee: Delphi Technologies, Inc.Inventor: Larry M Mandel
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Patent number: 6700196Abstract: A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components, wherein this segregation of components allows for hermetically sealing the active components with a cover while leaving accessible the passive components, and wherein the passive components are secured using a reflow soldering technique and are removable and replaceable so as to make the multi-chip module substantially programmable with regard to the passive components.Type: GrantFiled: September 23, 2002Date of Patent: March 2, 2004Assignee: Honeywell Federal Manufacturing & TechnologiesInventors: David Kautz, Howard Morgenstern, Roy J. Blazek
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Patent number: 6700197Abstract: A clip-attaching structure is provided, which includes: an attachment body; a mating attachment body to which the attachment body is attached; and a clip provided, in accordance with an outer shape of the attachment body, with a baseplate, a first side plate extending from one side of the baseplate and having an engaging portion, and a second side plate extending from the other side of the baseplate, which clip fixing the attachment body to the mating attachment body, wherein an engagement portion to which the engaging portion engages is provided on the mating attachment body, and the attachment body is fixed to the mating attachment body by fixing the clip to the mating attachment body.Type: GrantFiled: December 10, 2002Date of Patent: March 2, 2004Assignee: Yazaki CorporationInventors: Hidetoshi Sato, Koji Miyakoshi, Tsutomu Ishimaru
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Patent number: 6700198Abstract: In order to improve adhesion between a plated film which functions as an external connection terminal of a semiconductor device and a surface of a resin protuberance and to improve reliability, a carrier substrate includes a metal substrate which is shaped into a sheet form, to which a semiconductor chip is fixed, and which is removed before the semiconductor device is completed, a recess formed at a position of the metal substrate corresponding to the resin protuberance and having a rugged bottom surface and/or a rugged side surface, and a plated film formed on the inner surface of the recess.Type: GrantFiled: October 5, 2001Date of Patent: March 2, 2004Assignees: Shinko Electric Industries Co., Ltd., Fujitsu LimitedInventors: Hideki Toya, Mitsuyoshi Imai, Masaki Sakaguchi, Naoki Yamabe, Mamoru Suwa, Toshiyuki Motooka, Hideharu Sakoda, Muneharu Morioka
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Patent number: 6700199Abstract: A gold-silver alloy bonding wire for a semiconductor device is provided. The bonding wire contains: a Au-Ag alloy including 5-40% Ag by weight in Au having a purity of 99.999% or greater; at least one element of a first group consisting of Pd, Rh, Pt, and Ir in an amount of about 50-10,000 ppm by weight; at least one element of a second group consisting of B, Be, and Ca in an amount of about 1-50 ppm by weight; at least one element of a third group consisting of P, Sb, and Bi in an amount of about 1-50 ppm by weight; and at least one element of a fourth group consisting of Mg, TI, Zn, and Sn in an amount of about 5-50 ppm by weight. The bonding wire is highly reliable with a strong tensile strength at room temperature and high temperature and favourable bondability. When the bonding wire is looped, no rupture occurs in a ball neck region. Also, no chip cracking occurs since the ball is soft.Type: GrantFiled: March 7, 2003Date of Patent: March 2, 2004Assignee: MK Electron Co., Ltd.Inventors: Jeong-Tak Moon, Jong-Soo Cho, Dong-Ho Joung
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Patent number: 6700200Abstract: Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical dehydroxylation operation, wherein the halogen compound may be NH4F or CCl4.Type: GrantFiled: November 16, 2000Date of Patent: March 2, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Rao V. Annapragada
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Patent number: 6700201Abstract: In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines. The sector connecting lines include a first set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across the sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., the sector connecting lines are in a staggered relation.Type: GrantFiled: December 11, 2001Date of Patent: March 2, 2004Assignee: Advanced Micro Devices Inc.Inventors: Richard Fastow, Yue-Song He, Sameer Haddad
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Patent number: 6700202Abstract: A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. The method includes the steps of providing the first layer having a partially oxidized interface; introducing a hydrogen-containing plasma to the interface; reducing the oxidized interface and introducing second-layer-forming compounds to the hydrogen-containing plasma. A concomitant apparatus (i.e., a semiconductor device interface) has a first insulating layer, one or more conductive devices disposed within the insulating layer, the insulating layer and conductive devices defining the interface, wherein the interface is treated with a continuous plasma treatment to remove oxidation and deposit a second layer thereupon.Type: GrantFiled: December 7, 2001Date of Patent: March 2, 2004Assignee: Applied Materials, Inc.Inventors: Judy H. Huang, Christopher Dennis Bencher, Sudha Rathi, Christopher S. Ngai, Bok Hoen Kim
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Patent number: 6700203Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.Type: GrantFiled: October 11, 2000Date of Patent: March 2, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Lawrence Clevenger, Louis Lu-Chen Hsu, Keith Kwong Hon Wong
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Patent number: 6700204Abstract: A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.Type: GrantFiled: January 2, 2002Date of Patent: March 2, 2004Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chien-Te Chen
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Patent number: 6700205Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.Type: GrantFiled: July 8, 2002Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Daniel Smith, Jason Taylor
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Patent number: 6700206Abstract: A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is adhered to the underside of the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die may be adhered to the upper side of the die paddle along a surface which is opposite to its active surface and is electrically coupled with one or more of the plurality of lead fingers. The die paddle may be formed to exhibit a smaller peripheral outline than that of the first semiconductor die such that the die paddle does not interfere with any peripherally located bond pads of the first semiconductor die. The die paddle may further serve as a heat spreader, resulting in a more thermally stable package.Type: GrantFiled: August 2, 2002Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventor: Larry D. Kinsman
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Patent number: 6700207Abstract: A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.Type: GrantFiled: August 5, 2002Date of Patent: March 2, 2004Assignee: LSI Logic CorporationInventors: Senol Pekin, Anand Govind, Carl Iwashita
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Patent number: 6700208Abstract: A surface mounting substrate is configured to surface mount a semiconductor element thereon, the semiconductor element having a plurality of protruding electrodes arranged in a staggered arrangement of two rows. A plurality of bonding pads formed on a substrate are arranged in a staggered arrangement corresponding to the staggered arrangement of the protruding electrodes of the semiconductor element. Each of the bonding pads includes a pad portion having a substantially uniform width and an end portion extending from the pad portion toward the other row of the bonding pads. The end portion of each of the bonding pads lacks a portion extending beyond a boundary between the end portion and the pad portion of the bonding pads arranged in the other row. Accordingly, a reliable mounting can be achieved even if the protruding electrodes are offset from bonding pads.Type: GrantFiled: October 18, 2000Date of Patent: March 2, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yoshihiro Yoneda
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Patent number: 6700209Abstract: An integrated circuit package that contains an underfill material between an integrated circuit and a substrate. The integrated circuit may be mounted to the substrate with solder bumps in a C4 process. The underfill material may extend from an edge of the integrated circuit a length that is no less than approximately 25% of the length between the integrated circuit edge and the integrated circuit center. It has been discovered that a length greater than approximately 25% does not provide a significant reduction in the strain of the solder bumps.Type: GrantFiled: December 29, 1999Date of Patent: March 2, 2004Assignee: Intel CorporationInventors: George F. Raiser, Bob Sundahl, Ravi Mahajan
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Patent number: 6700210Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.Type: GrantFiled: August 2, 2002Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventor: Steven R. Smith
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Patent number: 6700211Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.Type: GrantFiled: December 23, 2002Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Gurtej S. Sandhu, Mike P. Violette
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Patent number: 6700212Abstract: A method for optimizing the starting torque and for reducing the electrical power usage of a starter-generator of an internal combustion engine. The starter-generator is configured as an electrical machine, which is operated using an inverter or an indirect a.c. converter the electrical power Pel being made available by a vehicle battery. Before the imaginary turning point (31) on the torque curve (4) of the starter-generator is reached, the phase current of the electrical machine is limited. The electrical machine is controlled from the point at which a limiting point (32) is reached along the electrical limiting power curve (30) (P=const), such that the electrical power Pel corresponds to that at the stationary operating point (25) of the electrical machine.Type: GrantFiled: January 8, 2002Date of Patent: March 2, 2004Assignee: Robert Bosch GmbHInventors: Manfred Ackermann, Beqir Pushkolli
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Patent number: 6700213Abstract: A control system provided in a hybrid vehicle with a combustion engine for outputting a driving force, an electric motor for generating a force for assisting the output from the engine, depending on driving conditions, a power storage unit for storing electric energy generated by the motor acting as a generator using the output from the engine and electric energy regenerated by the motor when the vehicle decelerates. The control system includes an output assist determination means for determining, based on a determination threshold value as the standard, whether to assist the output from the engine by the motor, depending on the driving conditions of the vehicle. An air-fuel controller is provided for changing the air-fuel ratio of the mixture, which is to be supplied to the engine, to a condition leaner or richer than the stoichiometric air-fuel ratio.Type: GrantFiled: October 26, 2000Date of Patent: March 2, 2004Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Teruo Wakashiro, Atsushi Izumiura, Kan Nakaune, Takashi Iwamoto, Asao Ukai, Katsuhiro Kumagai
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Patent number: 6700214Abstract: A power generation system is described for supplying electrical power to a load from at least one of a generator and a battery. The power generation system includes a power bus coupled to the generator and a bi-directional conversion unit coupled between the power bus and the battery. The bi-directional conversion unit is capable of transitioning between a first direction wherein electrical power flows from the power bus to the battery and a second direction wherein electrical power flows from the battery to the power bus.Type: GrantFiled: August 24, 2001Date of Patent: March 2, 2004Assignee: Aura Systems, Inc.Inventors: Richard J. Ulinski, Khaliqur Rahman, Hugh C. Clarke, W. Stephen Heitz
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Patent number: 6700215Abstract: Generators for use with a fossil fuel- and electric-powered vehicle having a plurality of different types of generator units mounted on a vehicle to supplement the power supply of the vehicle. Propeller generator units and turbine generator units utilize the force of oncoming wind to output electricity. The rolling wheel generator units consist of installing an additional fifth wheel, sixth wheel, seventh wheel, and eighth wheel of a dedicated generator roller wheel set on any of the main wheel axles disposed on the vehicle undercarriage such that by circumvolution around the axle when the vehicle is proceeding forward, the additionally installed generator roller wheel set rotates generator to produce electricity. A matching rectifier center caches the electric power produced by each generator unit and, following accumulation, directly supplies electricity to the vehicle or recharges its storage battery.Type: GrantFiled: September 21, 2001Date of Patent: March 2, 2004Inventor: Shiang-Huei Wu
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Patent number: 6700216Abstract: Windmill blades are magnetically levitated such that there is no physical contact with the support, avoiding friction. Furthermore, the electromagnetic resistance is varied relative to the rotation speed of the blades. When the blades are at rest, the electromagnetic circuit is inactivated such that the blades have no force to prevent their rotation, friction or electromagnetic, enabling the blades to start rotating at near zero wind speed. As the blades gain rotational momentum, the electromagnetic generators are progressively activated, providing the maximum power generation without stalling the windmill.Type: GrantFiled: March 3, 2003Date of Patent: March 2, 2004Inventor: Charles S. Vann
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Patent number: 6700217Abstract: A power transfer system for converting recurring wave movement within the ocean to electrical energy. The system comprises pressure sensing structure such as a pressure transducer 10 or combination movable magnet and coil 50, positioned below water level and at a location 20 of wave movement for (i) registering changes in height of water 18 and 19 above the pressure sensing structure 10, 50 and (ii) providing electrical power output at the ocean floor corresponding to changes in gravity force associated with the changes in the height of water. A transfer medium 12 is coupled at one end to the pressure sensing structure and extends at a second end to a shore location. A power receiving device such as a bank of storage batteries 14 or electrical load is coupled to the transfer medium at the shore location for receiving the power output from the transfer medium and for processing the power for use.Type: GrantFiled: February 21, 2001Date of Patent: March 2, 2004Inventors: Vaughn W. North, James J. Croft, III, Kenneth Lawrence DeVries
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Patent number: 6700218Abstract: A wind energy catchment device comprising a central vertical shaft that rotates, the bottom end of which is secured by means of bearings to a rigid support fixed to the ground, the upper and lower part of the shaft have radial arms secured to it, evenly spaced one from the other, the outer ends of the upper arms are connected by cables or cords with its contiguous outer ends of the lower arms, between the upper and lower radial arms and the central shaft there are rectangular parallelepiped sails secured at their outer vertices. In all cases the furthest external vertical side of these sails or plates is secured and the sails or plates rotates from 90° to 180° with or around their shafts, cables or ropes that connect the ends of the arms, having both internal vertices loose, between the central shaft and two contiguous arms are arranged some parallel cords or mesh that support the sails or plates when they receive the air on the side of the mesh furthest from the wind.Type: GrantFiled: March 12, 2002Date of Patent: March 2, 2004Inventor: Manuel Munoz Saiz
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Patent number: 6700219Abstract: A steering column module for a motor vehicle includes functional units such as steering angle sensors and torque sensors adjacently arranged on a steering column. The functional units deliver respective output signals and requiring respective control signals. An electronics unit is connected with an onboard power supply of a motor vehicle for receiving power. The electronics unit is operable for processing the output signals of the functional units and operable for generating control signals for the functional units. A first one of the functional units is connected to the electronics unit via electrical plug-in connector parts with correspondingly arranged counter electrical plug-in connector parts situated on the electronics unit. A second one of the functional units is combined with the electronics unit to form an inseparable assembly.Type: GrantFiled: September 20, 2002Date of Patent: March 2, 2004Assignee: Leopold Kostal GmbH & Co. KGInventors: Klaus Hirschfeld, Holger Lettmann, Markus Adam
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Patent number: 6700220Abstract: A pass-key electronic module is provided for enabling remote control of a function in a motor vehicle equipped with a key identity code verifying anti-theft system, under control of a vehicle control unit connected to a key identity code receiving sensor through a data communication link and an enable line. The module comprises (a) a communication circuit enabling communication with the vehicle control unit through the data communication link, (b) an input receiver circuit for receiving a command signal from a remote control system controller, (c) a switching circuit for disabling the sensor from communicating with the vehicle control unit upon sensing of the command signal through the input circuit, and (d) a memory circuit storing an operating program and an identity code subject to validation by the vehicle control unit.Type: GrantFiled: May 30, 2002Date of Patent: March 2, 2004Assignee: Accessories Electroniques Bomar Inc.Inventors: Richard Bayeur, Christian Coutu
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Patent number: 6700221Abstract: An electronic unit in a motor vehicle has a connection for the negative onboard power supply voltage and a connection for the positive onboard power supply voltage, as well as an internal electric supply unit that can be used independently of the polarity of the onboard power supply voltage and independently of the onboard power supply voltage. The unit includes a function block which compares the actual voltage at the connection for the negative onboard power supply voltage with the actual voltage at the connection for the positive onboard power supply voltage. A polarity inversion of the onboard power supply voltage is detected (and a storage of the polarity inversion detection data is caused) if the actual voltage at the connection for the negative onboard power supply voltage is higher than the actual voltage at the connection for the positive power supply voltage, or if the respective actual voltages exceed preset reference values.Type: GrantFiled: July 16, 2001Date of Patent: March 2, 2004Assignee: Bayerische Motoren Werke AktiengesellschaftInventors: Armin Wagner, Christina Seidel, Christoph Luthe, Hans-Ulrich Stahl
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Patent number: 6700222Abstract: Solid state switching devices, such as power IGBT's, are used to switch a load from one AC generator to another. The switching is controlled to occur only when the phase and voltage of the two generator outputs are within acceptable limited, thus minimizing voltage and current transients.Type: GrantFiled: December 14, 2001Date of Patent: March 2, 2004Assignee: Lucas Industries LimitedInventor: Simon Turvey
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Patent number: 6700223Abstract: An active booster transformer system with a booster transformer core (S, 10, 17) of the type which is applied around an electrical cable (K, 1, 13) for reducing stray currents and in which the booster transformer core is a body built up of a magnetizable material provided with a continuous channel intended to accommodate the cable. The system includes a current sensor (G, 2-3, 14-15) which senses the net current in the cable (K, 1, 13), an amplifier unit (F, 4-7), the input signal of which is controlled by the current (Iv) sensed by the current sensor, and a magnetizing winding (L, 3, 15) situated on the booster transformer core (S, 10, 17). The output of the amplifier unit is arranged to drive the magnetizing winding and to create a magnetic flow in the booster transformer core, the flow, in turn, inducing a longitudinal voltage in the cable which counteracts the stray current.Type: GrantFiled: November 26, 2001Date of Patent: March 2, 2004Assignee: EnviroMentor ABInventors: Bengt Johansson, Yngve Hamnerius
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Patent number: 6700224Abstract: A presence detection and control system (2) outputs an identification code related to an individual, a motion signal in response to detecting motion in a field of view and/or a temperature signal related to an ambient temperature. A main control device (4) generates at least one wireless control signal based on the ID code, the motion signal and/or the temperature signal. A smart outlet (6) or a phone interrupter/dialer (8) can receive at least one wireless control signal. If the smart outlet (6) is responsive to the one wireless control signal, it connects an energy source to an energy consumption device (60, 62 or 64). If the phone interrupter/dialer (8) is responsive to the one wireless control signal, it conveys a message to a conductive communication line. This message is received by a central controller (90) which can log the message and/or a time the message was received.Type: GrantFiled: November 1, 2002Date of Patent: March 2, 2004Assignee: Energy Technologies, L.L.C.Inventors: James H. Biskup, Sr., Rohn A. Sambol, Sr., David V. Martin