Abstract: Multi-phase clock generators include a master-slave flip flop that generates a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency. The master-slave flip-flop includes a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs. A slave stage is also provided. The slave stage is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled and fed back to the first pair of differential inputs of the master stage.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: A filter means (36) which forms a frequency-selective attenuator (FSA) to attenuate the series resistance compensation signal (Vcomp) of a voltage clamp (5) having an undesired series resistance (Rs). Filter means (36) increases the stability and eliminates the steady-state error of series resistance compensation without compromising the compensated bandwidth, and without requiring excessive bandwidth of the compensation signal (Vcomp) to ensure stability. Filter means (36) also enables the compensated bandwidth and the rate of steady-state error elimination to be selected. Filter means (36) is particularly suited to improving the series resistance compensation of voltage clamps that measure ionic current in biological preparations, allowing rapid ionic current in excitable cells to be voltage clamped.

Abstract: A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first drive input for applying a first drive signal, and a first semiconductor switching element having a first load terminal connected to the first connecting terminal, a second load terminal connected to the second connecting terminal and a drive terminal coupled to the drive input. A voltage limiting circuit is provided and is connected between the first load terminal and the drive terminal of the first semiconductor switching element.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.

Abstract: A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gates of the biasing transistors and the pad to turn the biasing transistors off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.

Abstract: A two-terminal switch circuit (1) for periodically energizing a load (20) from a voltage supply includes a controllable switch (4) connected between the switch terminals (2,3), a resistance (8) and a capacitor (9) connected in series between the terminals (2,3), and a voltage threshold responsive arrangement (26) having a hysterisis characteristic. The voltage threshold responsive arrangement has a signal input (27) and a power supply input (29) connected to the common point (12) of the resistance and the capacitor, and a signal output (28) connected to a control input (13) of the controllable switch. The voltage threshold responsive arrangement is powered by the capacitor voltage. The threshold responsive arrangement closes the switch when the capacitor charges to a first threshold voltage and opens the switch when the capacitor thereafter discharges to a second threshold voltage which is lower than the first threshold voltage.

Abstract: The present application and invention provides a selectively enabled bias for the pass NMOS transistor (10) of an RF switch. Two bias supplies are selectively switched to connect to the source of the NMOS transistor (10). The first higher bias supply turns the NMOS transistor (10) off and the second lower bias supply turns the NMOS transistor (10) on. The selective switch performs a single pole double throw function and may include PMOS transistors (14, 16) with inverse logic signals connected respective gates. Diodes may be used between the PMOS and the NMOS gate to reduce the capacitance load at the NMOS gate. The bias circuitry provides for lower capacitance values in the NMOS transistor (10) for reducing insertion loss, and lower parasitic input to output capacitance thereby providing better isolation when the switch is off. Moreover, when the switch is on the source to substrate and the drain to substrate capacitances are decreased thereby providing better high frequency isolation.

Abstract: Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.

Abstract: Digital CMOS integrated circuit (120) comprising an analog signal processing circuitry with a series of two or more field-effect transistors (FETs). The FETs have a maximum allowed supply voltage value (Vmax). The digital CMOS integrated circuit (120) further comprises a local charge pump (135) for generating an elevated supply voltage (Vsupplydiff) larger than the maximum allowed supply voltage value (Vmax). The local charge pump (135) is arranged such that this elevated supply voltage (Vsupplydiff) is applied to the series of two or more of the field-effect transistors (FETs).

Abstract: A high voltage generating circuit is described that includes, a control signal generating circuit for generating a first control signal in a first time period, and for generating second, third and fourth control signals in second, third and fourth time periods in this order; first, second and third pre-charge circuit for pre-charging first, second and third nodes in response to the first control signal; first and second step-up and charge transferring circuits for stepping up the first and third nodes in response to the second control signal and for performing a charge sharing operation between the first and second nodes and between the third and fourth nodes; a third step-up and charge transferring circuit for stepping up the second node in response to the third control signal and for performing a charge sharing operation between the second and fourth nodes; a pre-charge and charge supplying circuit for pre-charging the fourth node and for supplying charges to the fourth node; and a fourth step-up and charge

Abstract: A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

Abstract: A data comparator using a dynamic reference voltage and an input buffer using the same. The data comparator comprises a comparator circuit for receiving a data signal and a pair of non-inverting/inverting signals, which are periodic and complementary. The output signal is generated by comparing twice the data signal with the sum of the non-inverting signal and the inverting signal. The non-inverting/inverting signals are used as a dynamic reference voltage in the data comparator.

Abstract: A zero bypass apparatus for a low noise amplifier includes a bypass circuit, and a switching circuit coupled with a low noise amplifier and with the bypass circuit. The switching circuit includes one or more solid state devices responsive to absence of a control bias for switching an RF input signal from said amplifier to the bypass circuit with a low insertion loss and high isolation.

Abstract: A high-frequency power amplifier system including a plurality of individual amplifiers connected in parallel, the amplifiers including switching-driven FET's. A fixed drain voltage is applied to one amplifier and a variable drain voltage is applied to another amplifier through a section including a DC-DC converter that converts the voltage according to a control value of a control signal. The turning on and off of the operation of the power amplifier is controlled by a control signal. Also, the circuit constants of a matching circuit are variable. In a high output power region, the power amplifier is turned on and, in a low output power region, turned off. Thereby, the decrease of efficiency of the power amplifier, owing to the DC-DC converter, may be suppressed to a minimum. The matching of the amplifier is adjusted when the power amplifier is switched on or off so as to improve efficiency. Consequently, it becomes possible to continuously control the output of the amplifier.

Abstract: A feed forward amplifier performs a carrier cancellation tuning process separate from an IM reduction tuning process, wherein the carrier cancellation tuning process is performed without reference modulations that are utilized to modulate a feed forward amplifier input signal during the IM reduction tuning process. By decoupling the reference modulations during the carrier cancellation process, the feed forward amplifier is able to eliminate the instantaneous carrier cancellation degradation that would otherwise be caused by the reference modulations.

Abstract: A low distortion power amplifier, where N is greater than 1, comprising an input divider (10) for dividing a received input signal (100), and outputting a first signal (104) and a main signal (102), a carrier cancellation component (50) connected to the input divider (10) for receiving the first signal (104) and outputting a distortion signal (114), an input attenuator (22) receiving the main signal (102) and outputting an attenuated main signal (118) to an input delay device (24) yielding a delayed, attenuated main signal (118), and an N way distortion cancellation component (52) having a first input connected to the carrier cancellation component (50) for receiving the distortion signal (114) and a second input connected to the input delay device (24) for receiving the delayed, attenuated main signal (118) and an output for outputting an amplified output signal (144) having low distortion.

Abstract: The invention relates to a method of amplifying an input signal having a DC component and an AC component. The method includes the steps of: comparing the input signal with a reference value, generating an intermediate signal by subtracting from the input signal a correction signal resulting from the comparison step, rectifying the intermediate signal, evaluating a mean value of the rectified intermediate signal, and multiplying the input signal by the mean value. The invention allows a reduction in the sensitivity of the amplifier to the DC component of the input signal.

Abstract: An RF power amplifier for amplifying an RF signal over a broad range of power with improved efficiency includes a main amplifier for amplifying an RF signal over a first range of power and with a power saturation level below the maximum of the broad range of power. A plurality of auxiliary amplifiers are connected in parallel with the main amplifier with each of the auxiliary amplifiers being biased to sequentially provide an amplified output signal after the main amplifier approaches saturation. The input signal is applied through a signal splitter to the main amplifier and the plurality of auxiliary amplifiers, and an output for receiving amplified output signals from the main amplifier and the plurality of auxiliary amplifiers includes a resistive load R/2. The split input signal is applied through a 90° transformer to the main amplifier, and the outputs of the auxiliary amplifiers are applied through 90° transformers to a output load.

Abstract: A filter circuit uses a trans-conductor circuit coupled to a control circuit having similar characteristics as the trans-conductor circuit. The control circuit is used to set and/or control the quiescent voltage of the trans-conductor circuit. As a result, the trans-conductor circuit may be designed to operate across a large frequency range while consuming minimal power. The control circuit may be operated using direct current (dc) voltage and may be implemented similar to the trans-conductor circuit implemented in the filter circuit.

Abstract: A phase-locked loop frequency synthesizer includes a first variable frequency divider connected between a reference signal generator and a first controllable synchronous frequency divider. A second frequency divider is connected between a second controllable synchronous frequency divider and a voltage controlled oscillator. A phase-frequency comparator compares first and second low frequency signals from the first and second controllable synchronous frequency dividers and outputs an adjust signal according to a detected difference therebetween. A phase-locked detector outputs a phase-locked signal in response to the adjust signal. A switching control logic is operable so as to supply a frequency dividing control signal to the first and second controllable synchronous frequency dividers with reference to a divided reference signal from the first variable frequency divider upon receiving the phase-locked signal from the phase-locked detector.

Abstract: A frequency sythesizer and a method for synthesizing a signal having a given output frequency includes providing a controlled oscillator having a frequency control input and a feedback loop, applying a frequency control signal to the frequency control input, and compensating gain variation of the controlled oscillator outside of the feedback loop.

Abstract: A dual-range crystal oscillator module comprises lower and upper wiring board panels each having a component side, a surface mount side, a central portion and an outer edge portion including a plurality of input-output contacts. A lower set of crystal oscillator components is mounted to the lower wiring board panel such that the lower set and the lower wiring board panel define a first crystal oscillator circuit. An upper set of crystal oscillator components is mounted to upper wiring board panel such that the upper set of crystal oscillator components and the upper wiring board panel together define a second crystal oscillator circuit. A side-wall frame is attached between the upper and the lower wiring boards providing connections between the input-output contacts of the upper wiring board panel and the input-output contacts of the lower wiring panel.

Abstract: An oscillation circuit uses a SAW oscillator and is able to control the oscillation frequency easily and correct the temperature characteristic of the oscillator so that an oscillation signal with high temperature stability can be generated. A clock signal CLK having a prescribed frequency difference from the ideal oscillation frequency is generated by the SAW oscillator 10. Register 30 is driven by a frequency-divided clock signal obtained by dividing the frequency of the clock signal at a predetermined frequency division rate. In-phase signal SI and quadrature signal SQ generated corresponding to the data Da that is incremented by a prescribed addition value F every period of the frequency-divided clock signal are output, and the clock signal is IQ-modulated on the basis of these signals. The frequency error of clock signal CLK can be corrected, and an output signal Sout having near ideal oscillation frequency can be obtained.

Abstract: A VCO having an automatic amplitude control circuit In the form of a sensing amplifier provided in the feedback loop to sense the oscillator amplitude and draw current away only when the positive peak voltage Is above a certain value. In general, any amplifier may be used in the feedback loop that outputs current proportional to a peak positive input (in a non-linear and asymmetric fashion with respect to the changing voltage). In one example, the amplifier in the feedback loop comprises first and second transistors that are set nominally in cut off and behave as class C amplifiers. The advantage of this amplifier transistor configuration is that the amplifier they form has a low load on the LC tank circuit and a high input impedance.

Abstract: A cross-coupled cascode voltage controlled oscillator including a variable-frequency tank circuit, first and second cascode-coupled active devices coupled to the tank circuit, and third and fourth cascode-coupled active devices coupled to the tank circuit, the first and second active devices being cross-coupled to the third and fourth active devices. The invention produces lower drain the gate voltages resulting in fewer device failures.

Abstract: A method and apparatus for producing high-frequency oscillations is disclosed. A new resonator architecture minimizes via losses and supports a compact layout of active circuitry. The resonator architecture incorporates dual resonant transmission lines to reduce resonator loss and facilitate compact layout. The oscillations of two oscillators are cross-coupled in a way that compensates for the delay in the active devices of the oscillator, thus permitting accurate alignment of the active circuitry response with the oscillation waveform. The cross-coupling of the two oscillators improves phase noise performance and eliminates spurious oscillations. An active circuit architecture provides very narrow pulses for the operation of the oscillator. This architecture provides for accurate cross-coupling and pulsed-mode operation to improve manufacturing stability and phase noise performance.

Abstract: A method and an arrangement for compensating for amplitude imbalance of a quadrature modulator including: determining a first correlation on the basis of a first modulation signal and an output signal of the quadrature modulator; determining a second correlation on the basis of a second modulation signal and the output signal of the quadrature modulator; producing a compensation signal proportional to the amplitude imbalance on the basis of a ratio of the determined correlations and the first and second modulation signals; and processing at least one of the modulation signals of the quadrature modulator with the compensation signal; wherein determining the correlations uses unprocessed modulation signals of the quadrature modulator for determining the correlations.

Abstract: An array of carbon nanotube electron sources to make an integrated array of RF (radio frequency) sources in a single vacuum envelope. The RF sources can be printed circuit traveling wave tubes.

Abstract: A method and apparatus for reducing electromagnetic emissions from a high-speed differential data connector is disclosed. The method and apparatus are as effective as a 360° enclosure, while being easier and less expensive to manufacture and does not require a direct electrical connection between the Transistor-to-Transistor logic (TTL) or logic ground and the system chassis ground.

Abstract: A high-frequency module of the present invention includes a laminate ceramic layer including a first layer smaller in area than the other layers. Parts constituting high-frequency circuitry are mounted on the laminate ceramic layer. A single interface substrate is juxtaposed to the first layer and connects the high-frequency circuitry and a waveguide. A metallic casing supports the laminate ceramic substrate and interface substrate with ground held in contact. The metallic casing is formed with at least one waveguide hole. A cover covers the waveguide hole and forms a waveguide end cavity. The interface substrate is positioned on the second layer of the laminate ceramic substrate, which just underlies the first layer, at one side and protrudes from the metallic casing into the waveguide hole at the other side.

Abstract: In some embodiments, the invention includes system comprising a circuit board including a circuit board trace. This system includes a packaged chip supported by the circuit board including, the packaged chip having a package, wherein the circuit board trace is connected to the package in a circuit board breakout region, and wherein the circuit board trace includes a fan-out trace section having an impedance Zo1, a matching region trace section having an impedance Zo2, and a package trace compensation section having an impedance Zo3, wherein an effective impedance of the matching region trace section and the package trace compensation section is approximately equal to impedance Zo1, where Zo3<Zo1<Zo2.

Abstract: An AC power feed device for conducting electrical power from a source to a load. The feed device has a constant characteristic impedance along its length and an outer periphery that varies in size progressively along its length, or the feed device has an input end connected to the match network and an output end connected to an electrode, and has a characteristic impedance which varies from a value substantially equal to the output impedance of a match network coupled at the input end to a value equal to the impedance of the electrode.

Abstract: A dual-mode resonator comprises a dielectric substrate having a region divided into four quadrants, and a ring resonator forming quadrangularly symmetrical configurations within the four quadrants of the region. The symmetrical configurations may be formed from folded sections of the resonator, so that parallel lines with opposite currents that cancel to minimize the far-field radiation of the filter structures. The symmetrical configuration can also be meandered, so that opposite currents in parallel line segments within each meander and the line segments that interconnect the meanders cancel to minimize the far-field radiation of the filter structures. One resonator can be used in a two-pole dual-mode filter structures, or multiple resonators can be used in more complex dual-mode filter structures.

Abstract: A longitudinally-coupled resonator mode SAW filter portion having at least two interdigital transducers (IDTs) is disposed on a piezoelectric substrate. At least one SAW resonator is electrically connected in parallel with the SAW filter portion such that the at least one SAW resonator is disposed between an input terminal or an output terminal and the SAW filter portion. The resonance point of the SAW resonator is disposed in the pass band of the SAW filter portion.

Abstract: A dielectric resonator filter comprises dielectric resonators, an enclosure having a main body, a lid, and partition walls, interstage-coupling tuning windows, interstage-coupling tuning bolts, input/output terminals, and input/output coupling probes. Resonance-frequency tuning members each composed of a conductor plate and a bolt coupled integrally thereto are attached to the enclosure lid. Undesired-mode suppressing means such as rings attached to the bolts of the resonance-frequency tuning members or bolts attached to the conductor plates or to the enclosure lid are disposed in an undesired-mode excitation space, whereby the occurrence of a disturbed characteristic in the pass band (or stop band) is suppressed.

Abstract: A plurality of composite elements are arranged in parallel with each other on a substrate. The composite elements each include a rectangular microstrip line element, an input microstrip line and an output microstrip line. The microstrip line element has one longer side, the other longer side, one end and the other end, and the input microstrip line is connected at the one end to the one longer side while the output microstrip line is connected at the other end to the other longer side. The composite elements are cascaded to constitute a low-pass filter.

Abstract: A transmission line structure for reduced coupling of signals between circuit elements. The structure includes an RF transmission line disposed on a circuit board (100) formed from a dielectric substrate material. The RF transmission line includes an elongated conductive metal trace (110) and has opposed elongated edge portions. The structure also includes a pair of elongated substrate boundary regions (105) coextensive with at least a portion of the elongated conductive metal trace (110). Each of the boundary regions (105) is positioned adjacent to a respective one of the opposing edge portions to define an elongated substrate channel region (205). A pair of conductive metal traces (410) can be disposed on the substrate channel region (205) within the substrate boundary regions (105). The conductive metal traces (410) are spaced apart by an intermediate substrate region (405) and are parallel to each other.

Abstract: An apparatus comprising a direct board-to-board coaxial connection fabricated from metal parts that have been stamped and formed is disclosed. The connection allows direct board-to-board coaxial connections with a low cost and ease of manufacturing.

Abstract: A micro-switching device actuated by a low voltage is provided. The micro-switching device includes a spring operating elastically; a membrane formed on one side of the spring, being held by the spring; and a lower electrode formed below the membrane, for generating an electrostatic attraction when a voltage is applied thereto, wherein the membrane is non-planar. This micro-switching device is advantageous in that it can be actuated by a low voltage and prevents the adhesion that occurs commonly in micro devices.

Abstract: A contact apparatus is provided having a permanent magnet disposed in a region where a fixing contact point is mounted to a fixing contact and a movable contact to which a movable contact point is mounted. An arc generated between both the contact points is moved in a lateral direction by the magnetic force of the permanent magnet and stretched. An arc-extinguishing member which is heated by the arc for generating arc-extinguishing gas is provided such as to surround the fixing contact point and the movable contact point.

Abstract: An operating mechanism controls and trips a separable contact structure arranged in a protected circuit. The mechanism includes a frame, a drive member pivotally coupled to the frame, a spring pivotally connecting the drive member to a drive connector, an upper link pivotally seated on the drive connector, a lower link member pivotally coupled to the drive connector, a crank member pivotally coupled to the lower link member for interfacing the separable contact structure, and a cradle member pivotally secured to the frame and pivotally securing the upper link. The cradle member is configured for being releasably engaged by a latch assembly, which is displaced upon occurrence of a predetermined condition in the circuit such as a trip condition. The mechanism is movable between a tripped position, a reset position, an off position, and an on position. Spacers are operatively positioned between movable members, and protrusions are operatively formed on the enclosure of the contact structure.

Abstract: Asymmetric, compact non-superconducting magnets for magnetic resonance imaging are provided. The magnets have a homogeneous region (the “dsv”) which can be located close to one end of the magnet so as to reduce the sensation of claustrophobia experienced by patients undergoing MRI procedures. The magnets can be designed using a hybrid process in which current density analysis is performed to obtain an initial coil configuration which is then refined using non-linear optimization techniques to obtain a final coil configuration. The hybrid method can incorporate various constraints, including, the location and size of the dsv, the uniformity and strength of the B0 field, stray field strengths outside of the non-superconducting magnet, and field strengths within the magnet's coils. The hybrid technique can also be used to design compact symmetric non-superconducting magnets.

Abstract: A magnet assembly for generating a magnetic field (H) in the direction of a z axis in a working volume (AV) disposed on the z axis about z=0 with an actively shielded superconducting magnet coil system (M) and at least one current path (P1, . . . , Pn) which is superconductingly closed in the operating state, wherein the actively shielded superconducting magnet coil system (M) comprises a radially inner partial coil system (C1) and a radially outer partial coil system (C2) disposed coaxially with respect to each other and whose magnetic dipole moments have opposite signs in the operating state and differ by an amount &Dgr;m, with |&Dgr;m|<2.5% of the magnitude of the magnetic dipole moment of the radially inner partial coil system (C1), is characterized in that the current paths (P1, . . . ,Pn) are at least temporally superconductingly short-circuited during charging of the actively shielded superconducting magnet coil system (M) and that the current paths (P1, . . .

Abstract: An ignition apparatus includes a central core extending along a main axis, and a primary winding disposed radially outwardly thereof. The ignition apparatus further includes a secondary winding. The primary winding has a greater axial length than the secondary winding, this additional axial length being implemented on the low-voltage axial end of the ignition apparatus, relative to the main axis. The extended primary winding provides an increased leakage inductance spike, which may be used by an ion sense system to (i) obtain increased bias voltages, and, (ii) increase the effective turns ratio, thereby reducing the amount of wire required for the secondary winding.

Abstract: A current transformer fixing device comprises a current transformer cylinder surrounding the periphery of a central conductor to be connected to an electric power line, a cylindrical container surrounding the outer peripheral side of a current transformer arranged on the outer peripheral side of the current transformer mounting cylinder and containing the current transformer, a transformer mounting plate connecting the bottom side of the current transformer mounting cylinder and the bottom side of the cylindrical container to each other and restricting axial movement of the current transformer, a sealing flange connected to the upper end of the cylindrical container with a gap between the sealing flange and the upper end of the current transformer mounting cylinder, and fixing bolts fastened to the sealing flange in an axial direction of the conductor and restricting axial movement of the current transformer.

Abstract: The present invention relates to inductors with improved inductance and quality factor. In one embodiment, a magnetic thin film inductor is disclosed. In this embodiment, magnetic thin film inductor includes a plurality of elongated conducting regions and magnetic material. The plurality of elongated conducting regions are positioned parallel with each other and at a predetermined spaced distance apart from each other. The magnetic material encases the plurality of conducting regions, wherein when currents are applied to the conductors, current paths in each of the conductors cause the currents to generally flow in the same direction thereby enhancing mutual inductance.

Abstract: A dielectrically isolated temperature compensated pressure transducer including: a wafer including a deflectable diaphragm formed therein, the diaphragm being capable of deflecting in response to an applied pressure, and the diaphragm defining an active region surrounded by an inactive region of the wafer; a plurality of dielectrically isolated piezoresistive elements formed on the active region of the wafer and coupled together to form a Wheatstone bridge configuration so as to cooperatively provide an output signal in response to and indicative of an amount of deflection of the diaphragm, the plurality of piezoresistive elements being undesirably operative to introduce an undesirable error into the output according to exposure of the wafer to an environmental condition; and, a dielectrically isolated resistor formed on the inactive region of the wafer and electrically coupled in series to the plurality of piezoresistive elements so as to at least partially compensate for the undesirable error.

Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care.