Abstract: A cover for use on an electric meter is disclosed which includes an optical port which aids in transmission of optical signals from an optical transmitter, such as a light emitting diode, to an optical receiver, such as a photodiode or similar. The optical port further includes lenses located in the optical transmission path to focus the optical signal, either convergently or divergently, proximate to the optical receiver thereby improving signal reception.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A drop-in environmental control material carrier assembly 55, which improves the performance and lowers he cost of semiconductor packages. The disclosed approach positions the environmental control materials inside the package cavity by means of a drop-in environmental control material carrier assembly 54, which can hold up to eight materials. In the case of a packaged micromirror, the getters consist of at least three types; i.e., (1) one for absorbing moisture inside the package, (2) one for absorbing adhesive outgassing constituents inside the package, and (3) one for storing the PFDA lubricant used to prevent the micromirror mirrors from sticking. The performance and lifetime of the micromirror devices are improved and the cost of projection display systems, in which these micromirrors are central components, is lowered.

Abstract: A tone wheel for generating electrical pulses at a rate proportional to the rotational speed of a road wheel. The tone wheel is stamped from sheet steel stock and is characterized by elongated, axially extending teeth supported in cantilever fashion from one end on roots extending radially from a center portion of the tone wheel. The teeth are spaced from each other and for a major portion of their length are free of adjacent structure so that they produce a sharp pulse when scanned by a sensor and are self-cleaning to reduce the risk of accumulating dirt and debris which can otherwise result in destruction of the sensor.

Abstract: To minimize change in duty ratio of an output signal brought about by a leakage flux and to obtain a sensor output stabilized even under an environment of use abundant of the leakage fluxes, a sensor-equipped bearing assembly 31 includes a rotatable race member 32 provided with a to-be-detected portion 1 having a magnetic characteristic in which N and S magnetic poles alternate with each other. In face-to-face relation with this to-be-detected portion 1, a magnetic detecting portion 2 is secured to a stationary race member 33. The magnetic detecting portion 2 is made up of magnetic sensors arranged in a direction circumferentially of the race members 32, 33 and each capable of providing an analog output. A differential output generating means 7 is provided for processing a differential output of the adjoining two magnetic sensors 2a and 2b as an encoder signal for one phase.

Abstract: A rotation angle sensing device for detecting a relative rotation angle between a rotor and a stator includes main magnets, fixed in the rotor, and hole ICs, fixed in the stator. The hole ICs detect magnetic flux of the main magnets , and the relative rotation angle therebetween is detected. A supportive magnet is disposed between the hole ICs so as to offset the magnetic flux of the main magnets. Accordingly, a rotation angle in which the magnetic flux density detected in the hole ICs becomes 0[mT] can be changed by the supportive magnet. Therefore, a 0° position of the rotation angle can be set to the rotation angle in which the magnetic flux density is detected as 0[mT], and moreover the detectable range of the rotation angle can be enlarged to be more than 90°.

Abstract: Magnetic resonance imaging uses a pulse sequence formed to include a pre-pulse, an RF excitation pulse, an encoding gradient pulse, and a reading gradient pulse. The encoding gradient pulse has an encoding amount determined to allow a data acquisition position in a k-space to be directed outward from a center of the k-space. A train of pulses including the RF excitation pulse, the encoding gradient pulse, and the reading gradient pulse is repeated to allow the number of times of data acquisition in the k-space to become larger as approaching to a central region of the k-space. The pre-pulse is formed to be reduced in an application rate to the RF excitation pulse as approaching to an outward position in the k-space. By way of example, this pulse sequence is used for contrast enhanced MRA carried out under a dynamic scan.

Abstract: The present invention presents a new approach to rapidly obtaining precise high-dimensional NMR spectral information, named “GFT NMR spectroscopy”, which is based on the phase sensitive joint sampling of the indirect dimensions spanning a subspace of a conventional NMR experiment. The phase-sensitive joint sampling of several indirect dimensions of a high-dimensional NMR experiment leads to largely reduced minimum measurement times when compared to FT NMR. This allows one to avoid the “sampling limited” data collection regime. Concomitantly, the analysis of the resulting chemical shift multiplets, which are edited by the G-matrix transformation, yields increased precision for the measurement of the chemical shifts. Additionally, methods of conducting specific GFT NMR experiments as well as methods of conducting a combination of GFT NMR experiments for rapidly obtaining precise chemical shift assignment and determining the structure of proteins or other molecules are disclosed.

Abstract: To provide a diagnostic apparatus utilizing nuclear magnetic resonance suitable for interventional MRI which is not limited as to selection of an imaging section and an phase-encoding axis, the reception coil thereof includes three loop coils arranged so as to surround an object to be examined and to be within a plane including a line segment parallel to a static magnetic field direction, and two surface coils arranged in the vicinity of the surface of the object within a plane including a line segment perpendicular to the static magnetic field direction. In the reception coil, two or more sub-coils have nonuniform sensitivity profiles along an arbitrary axis. Therefore, the reception coil configured to have sensitivity throughout the imaging areas can be realized.

Abstract: A magnetic resonance device includes a hollow with an internal surface, a gradient coil system having an outer surface being arranged in the hollow with an interval space being formed between the boundary surface of the hollow and an outer surface of the gradient coil and at least one form-flexible hollow body being arranged between the boundary surface and the outer surface and having an arrangement for adjusting the inner pressure so that the interval space can be sealed from the outside.

Abstract: A new method for determining an actual steering wheel angle is provided that does not require re-calculation of a steering center upon each ignition of the vehicle. Accordingly, the vehicle dynamic controller may be activated very quickly after ignition, while a less costly relative steering wheel angle sensor may be employed.

Abstract: A detecting device for detecting electromagnetic waves generated by electric facilities includes a support having a peripheral surface for attaching a number of wave detectors which detect the electromagnetic waves generated by the electric facilities. The support may include a housing having a chamber for receiving the electric facilities, or having a curved outer peripheral surface for supporting the wave detectors. The wave detectors each has a number of light devices for indicating the strength of the received electromagnetic waves.

Abstract: Embodiments of high-resolution optical encoders having phased-array photodetectors and integrated on semiconductor chips. Emitters, detectors, and encoders disks are described which can be easily produced with semiconductor processes, such as a detector array provided with lens to collimate light and enhance detection. Integrated sensor chips include an array of photodetectors that receive energy from a beam emitted from an emitter and modulated by an encoder disk, analog-to-digital converters, state machines, counters, a communication module, a sensor processing unit, and a force computation unit. One embodiment includes low resolution and high resolution modes and an emitter controlled by sensor circuitry. A detector for an optical encoder can be provided on a single chip that includes a first array of photodetectors used for absolute sensing of a moving object, and a second array of photodetectors used for incremental sensing of the moving object.

Abstract: A method for inspecting relay open/close contacts for a contact weld is provided, each relay open/close contact being connected serially to each of a plurality of battery pack blocks. Battery ECUs for controlling the operating condition of each of the battery pack blocks employ one battery pack block for transmitting an inspection signal and the other battery pack blocks for receiving the inspection signal, such that the transmitting battery ECU transmits the inspection signal with its open/close contact closed. When any one of the other battery pack blocks receives the inspection signal at its battery ECU in which its open/close contact has not been closed, the open/close contact is determined to be welded. This inspection is performed successively with the transmitting and receiving battery ECUs being employed alternately in order to check the plurality of open/close contacts and their secondary open/close contacts for a contact weld.

Abstract: The aim of the invention is to improve the interrupting capacity of a vacuum switch, to achieve this, the contact parts (4, 5) that can be displaced in relation to each other are separated at a variable speed. Separation takes place in such a way that during a predetermined time period a predetermined distance between the contacts is not exceeded. To prevent said predetermined distance from being exceeded, a braking element is allocated to the vacuum circuit breaker.

Abstract: A system for detecting a board-insertion power-on versus a chassis power-on is disclosed. By using recessed circuit board sense contacts, recessed chassis sense contacts, or equivalent, a circuit can detect when power reaches a circuit board's power contacts before the circuit board sense contacts mate with corresponding chassis sense contacts. On the other hand, if a circuit board is fully seated when chassis power is first applied, the circuit will not detect that power has reached the power contacts before the sense contacts are mated, resulting in a different output. The circuit can include a latch, the output of the latch representing either a board-insertion power-on or a chassis power-on. The output of the latch can be used to modify a software or hardware condition or state, resulting in improved operation.

Abstract: In order to measure the current in a shunt, the voltage drop in the resistor of said shunt is evaluated as a measurement of the current. Normally, galvanic separation of the measuring device is required for high-potential shunts. According to the invention, a digital measuring signal provides the clock pulse for modulated supply current for the measuring device after an A/D conversion. The modulated supply current is also used as a carrier for the measuring information. In the associated evaluation device, an A/D converter (3) and a modulation unit (4) are arranged downstream from an amplifier (2) for the voltage signal which is picked off from the shunt (1).

Abstract: Disclosed is a method of measuring the time signal of an electronic device including steps for measuring a true signal and an inverted signal. The measured true path signal and inverted path signal are combined to reduce measurement error and provide an accurate measurement of the time signal of the device under test. Also disclosed is an interface for use between a device-under-test and test equipment. The interface includes means for alternately switching a time signal from the device-under-test to provide a true signal path and an inverted signal path for measurement. A system embodiment of the invention is also disclosed in which an interface and measuring means are used to alternately measure and combine a true signal and an inverted signal to provide an accurate time measurement result.

Abstract: In a system and method for testing and displaying the abnormalities, includes opens, shorts, bridged-taps and wet sections, of a copper pair line for xDSL service use, the abnormalities are amplified and normalized so as to be displayed within a predetermined observation range. The normalization steps include piecewise gaining and biasing the reflected pulse of various gains to create a first normalized reflected trace which match the reflected traces within a predetermined observation range and thereby constitute a total smooth curve; and amplifying the first normalized reflected trace according to a function of time to create a second normalized reflected trace so as to eliminate an exponential gain decay curve of a no-fault copper pair line with the same predetermined characteristic parameters from the first normalized reflected trace to thereby obtain a second normalized reflected trace showing any amplified abnormalities.

Abstract: A moving object detection apparatus in which an oscillating output, from a gate of an FET functioning as an oscillator, is coupled via a resonant line to a transmit-receive antenna, a wave, transmitted from the antenna and returned as a reflected wave, is received at the gate, and a beat signal component output from the gate, due to a phase difference between the transmitted wave and the reflected wave, is taken as a moving object detection signal.

Abstract: A method of monitoring or predicting corrosion using a field signature method is provided which is intended to be applicable to non-linear locations, such as bends, junctions and the like. The method includes obtaining information on a relationship which links voltage measurements, obtained for a location, between two or more electrical contacts in contact with the location at a first time and one or more other times when a current is passed through the location, to the loss of material from the location. The information on the relationship is used in a modelling process which includes the generation of a model of the location, two or more points on that location and modelling the values generated for the voltages which will be measured between the two or more points with a current applied to the location at a first and at least at a second time.

Abstract: A triangular wave generating circuit (21) generates a sweep voltage of a triangular wave, a VCO (22) generates a sweep of a frequency according to the sweep voltage, and a driving coil (4) is driven by the sweep voltage. From the current flowing through the driving coil (4), an interference component is extracted and rectified by a rectifier circuit (27). A peak hold circuit (28) holds a peak value of an interference voltage within a period corresponding to one sweep. The peak value thus held is compared by a comparator circuit (29) with a predetermined value and accordingly, a relay circuit (30) outputs a signal indicative of whether an object is present or not.

Abstract: A testing method for an electronic component in which a predetermined load is set, which is determined by a burn-in temperature, a burn-in voltage, and a burn-in period of time, and burn-in of an electronic component is carried out in such a manner that a load equal to the predetermined load is applied to the electronic component, with the method including a first step of placing an electronic component having a negative resistance-temperature characteristic in a heating atmosphere so that the temperature of the electronic component reaches a predetermined temperature which is lower than the burn-in temperature, a second step of supplying constant current to flow through the electronic component so that the predetermined temperature of the electronic component is increased to the burn-in temperature, and a third step of comparing the voltage actually applied to the electronic component to the burn-in voltage, correcting the burn-in time-period based on the comparison to determine a corrected burn-in time-peri

Abstract: A probe tower for an automatic test system includes an insulative retainer for holding an array of differential probe assemblies. Each differential probe assembly is an elongated structure having first and second ends and first and second coaxial portions. Each coaxial portion includes an outer conductor and a pair of annular insulators positioned therein for holding a center conductor. First and second contact pins extend from the center conductor at the first and second ends, respectively. First and second ground pins, which are electrically connected to the outer conductors of the first and second coaxial portions, extend from the first and second ends for conveying ground connections.

Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.

Abstract: A flip chip test structure is disclosed. The flip chip test structure utilizes a substrate used in flip chip package to replace the conventional transformer of a flip chip wafer probe card. The substrate-transformer replacement reduces the cost and simplifies the flip chip wafer probe card manufacturing process since the substrate is already available and matches the chip being tested while the transformer needs additional design and custom fabrication which are expensive and time-wasting for corresponding chip being tested.

Abstract: A multi-chip package device includes package terminals, a semiconductor memory chip and an interface chip. The semiconductor memory chip has a test circuit and a test terminal. The test circuit is enabled when a high voltage level is applied to the test terminal. The interface chip is connected to the package terminals and the semiconductor memory. The interface chip includes a control circuit, a high voltage generating circuit and a transferring circuit. The control circuit has memory terminals connected to the package terminals. The control circuit generates a test signal and an enable signal in response to signals received from the memory terminals. The high voltage generating circuit generates a high voltage signal having the high voltage level in response to the enable signal. The transferring circuit provides the high voltage signal to the memory chip in response to the test signal.

Abstract: A test method for the detection of redundant tests and inefficient tests (RITs) used for testing integrated circuits (ICs) and a subsequent optimization of test complexity and test time duration. Empirical data from an execution of all tests of interest in a test plan, flow or suite of tests is collected. The empirical data is collected without stopping at errors. This empirical data is then used to determine the identity of one or more redundant and/or inefficient tests in the test plan. In order to reduce testing time and optimize the test flow, one of more of the following occurs. Redundant tests may be selectively removed, inefficient tests may be re-ordered to allow more efficient tests to be executed earlier in the test flow of the ICs, or some combination of this. RIT information is thus used to optimize the test flow, resulting in a reduction in test complexity and in test duration.

Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.

Abstract: The present invention provides a circuit to shift the level of an arbitrary input signal level higher than the power supply voltage to a reference logic level controlled by the power supply voltage quickly, reliably, and accurately. When a signal input to port A changes from the low level to the high level, the potential at node S1 is immediately increased to a potential significantly higher than the power supply voltage due to the capacitive coupling of the drain-gate capacitance of NMOS transistor 10, so that NMOS transistor 14 turns on at bias circuit 12 in order to allow current to flow from node S1 to power supply voltage terminal C, and the potential of node S1 is clamped to level (VCC+VTN14), that is, above power supply voltage VCC by threshold voltage VTN14. As a result, a high level equal to the level below gate potential (VCC+VTN14) by threshold voltage VTN10, that is, the potential of VCC, is obtained at source of NMOS transistor 10, that is, port B.

Abstract: A digital level shift circuit includes a level shifting device such as a high voltage MOS device and can also include feedback circuitry. The level shifting device is turned on to make an output transition, and the feedback circuitry obtains a feedback or acknowledge signal indicating that the transition was made. In response, the feedback circuitry turns off the level shifting device, which can reduce power dissipation. A digital level shift circuit that includes two n-channel devices and two p-channel devices can also include sense/prevent circuitry that senses when current greater than a threshold flows through both devices of one channel type and, in response, prevents output transitions from being made, which can avoid false transmissions due to rapid changes in offset voltage. Control circuitry in a digital level shift circuit can include both feedback circuitry and sense-prevent circuitry.

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Abstract: The voltage level shifting circuit includes a complimentary signal input circuit having a pair of MOSs of a first withstand voltage and a load circuit having a pair of MOSs of a second withstand voltage, a first voltage down-converting element which prevents a potential level exceeding the first withstand voltage from supplying to a complimentary signal input circuit, and a third MOS of the second withstand voltage electrically connecting a third power supply node to an output node in response to a voltage potential from the load circuit. The voltage level shifting circuit also includes a fourth MOS of the first withstand voltage electrically connecting a first power supply node to the output node in response to one of the voltage potentials of the complimentary signal, and a second voltage down-converting element which prevents a potential level exceeding the first withstand voltage from supplying to the fourth MOS.

Abstract: A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

Abstract: A CMOS circuit arrangement. In this arrangement, relatively thick oxide devices are fabricated along with relatively thin oxide devices on the same chip. High speed logic circuits are fabricated with thin oxide devices as differential logic operating with a low voltage swing. A current source is fabricated using thick oxide devices to drop a large percentage of the supply voltage, protecting the thin oxide devices from damage caused by large voltage swings. An adaptive bias control circuit receives inputs from the logic circuit or elsewhere to control the bias current available from the current source to permit larger currents to pass through the current source at switching times.

Abstract: Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple devices coupled thereto. The data on a first data bus is transferred at a first voltage level and the data on a second data bus is transferred at a second voltage level. For example, the first data bus may transfer data at 3.3V and the second data bus may transfer data at 5V. A logic device (e.g., a CPLD) is connected between the first and the second data buses for transferring the data between the first and second voltage levels. The logic device is also configured for multiplexing the data with the second voltage level between first and second devices (e.g., one or more LEDs and/or NVSRAMs) connected to the second data bus.

Abstract: In a status scheme signal processing circuit which obtains a desired output signal on the basis of an OR signal between a pulse output from a one-shot pulse circuit at an edge of an input signal and a status signal, since the input signal and the status signal are not synchronized with each other, the output timing of the output signal changes depending on the timing of the input signal. Therefore, in the present invention, a mask signal generator which outputs a mask signal having a predetermined bandwidth T1 in response to a signal leading edge and a signal trailing edge of the input signal, and said desired output signal is masked (disabled) with the mask signal, so that an output signal is always obtained a predetermined period (T1) after the input timing of the input signal.

Abstract: A clock conversion apparatus includes a memory that can perform writing and reading independently from each other, a first counter circuit for controlling write addresses, a delay adjustment circuit for adjusting a delay time of a reading start reference signal from a writing start reference signal, and a second counter circuit for controlling read addresses from the reading start reference signal, wherein data corresponding to a horizontal sync period are written in the memory over plural times to reduce the capacity of the memory, and a writing start position and a reading start position are delay-adjusted.

Abstract: A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.

Abstract: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

Abstract: A pad driver method and apparatus is presented. The pad driver includes a dual path configuration. The dual path includes a first path and a second path. Both paths include a pre-driver. The first path and the second path communicate high voltage signals and low voltage signals. The pre-driver in the first path drives a pFET device. The pre-driver in the second path drives an nFET device. The pFET and nFET devices provide an output signal, which drives a pad. Each pre-driver further includes a first path and a second path. The first path in the pre-driver supports high voltage operation and the second path in the pre-driver supports low voltage operation.

Abstract: A driving circuit having a p-n-p transistor and an n-p-n transistor which are connected in series between a high-voltage side source terminal (VB) and a ground terminal, and a plurality of inverters provided on a path through which an input signal is transmitted to both the transistors. One of both the transistors is turned on, and the other is turned off, by means of the inverters to bring an output terminal connected between both the transistors, to any of a high voltage level and a low voltage level. The inverters are each constituted of a bipolar transistor which is element-isolated by silicon oxide layers in an n-silicon layer, and, in addition to inverters each having in the n-silicon layer a p+ substrate region for drawing out electric charges, inverters which do not have the p+ substrate region are provided in combination with the former.

Abstract: A circuit including a signal input to receive a signal, a buffer circuit to receive the input signal and to generate a buffer circuit output, and a voltage following circuit to receive the signal input and to generate a voltage following output. The buffer circuit output and the voltage following circuit output are coupled to a circuit output node.

Abstract: A phase locked loop circuit includes a phase comparator, a loop filter, a controlled oscillator, a limiter, a frequency divider, an unlock detecting circuit and a switch. The phase comparator compares an index signal and a reference signal. The loop filter smoothes an output signal of the phase comparator. The controlled oscillator oscillates at a frequency in accordance with an output signal of the loop filter. The limiter connected between an output of the phase comparator and an input of the controlled oscillator. The limiter limits level of a signal passing therethrough at a predetermined range. The frequency divider divides an output signal of the controlled oscillator and generates the reference signal. The unlock detecting circuit outputs the unlocking of a phase lock based on the index signal and the reference signal. The switch shuts up an output signal of the loop filter based on an unlock detecting signal.

Abstract: A loop powered process instrument comprises a control circuit measuring a process variable and developing a control signal representing the process variable. An output circuit for connection to a two-wire process loop controls current on the loop in accordance with the control signal. A power supply circuit is connected to the output circuit and the control circuit for receiving power from the two-wire process loop and supplying power to the control circuit. The power supply comprises cascaded charge pump circuits.

Abstract: A random number generator comprising a counter circuit configured to be supplied with a clock signal and a random signal, and to provide a count value of the clock signal with respect to a transition of the random signal, and a first latch circuit configured to latch the count value with respect to the transition of the random signal, and to provide a first random number signal.

Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.