Abstract: In a device for producing an image with a high light intensity by means of an image reproduction apparatus (9) which contains light valves, a light source comprising a light-emitting diode matrix (1, 2, 3) is provided for background lighting of the image reproduction apparatus (9). An optical device (5, 8, 10) for focussing and scattering the light which is produced by the light-emitting diodes (1) is arranged between the light source (1, 2, 3) and the image reproduction apparatus (9).

Abstract: An LED light tube for replacement for fluorescent light tubes includes an elongated cylindrical transparent envelope, a base cap at each end of the envelope, and at least one LED device in electrical communication with the base cap. The LED light tube is adapted for use in troffer light fixtures.

Abstract: A light source device includes a discharge tube, a reflector for reflecting a light radiated from the discharge tube, and support members for supporting the discharge tube to the reflector. The support member or the discharge tube is formed of a heat insulating structure so as to prevent a temperature drop of a portion of the discharge tube near electrodes thereof. By this arrangement, it is possible to prolong the operational life of the discharge tube.

Abstract: A light integrator is mounted in a housing or cover that allows aligning the light integrator relative to a color wheel or other sequential color element. In some embodiments, a plate is attached to one end of a light rod and supports the light rod in the cover in a cantilever fashion or in combination with other support. The light rod is aligned to a light source, such as a lamp, and then the color wheel is aligned to the output of the light rod without altering the relationship between the light rod and the lamp.

Abstract: An illumination apparatus comprises a small-plane light source having diffusion radiation characteristics, a columnar light leading member, having an incident end surface, an outgoing radiation end surface and a reflection surface, configured to reflect on the reflection surface at least a part of a light ray from the small-plane light source collected from the incident end surface, thereby leading the light to the outgoing radiation end surface, and an angle position converting member configured to convert an outgoing light angle intensity of the outgoing light from the outgoing radiation end surface of the columnar light leading member into a position intensity in a predetermined irradiation area.

Abstract: A structure for reflection of light comprising a curved surface reflector for reflecting the light emitted from a light source located on a focus of the curved surface reflector, and a semi-sphere surface for reflecting the light emitted from the light source located on a center of the semi-sphere surface. In specific, the focus of the curved surface reflector and the center of the semi-sphere surface are so positioned as to be substantially on the same location, thus after the light emitted from the light source is reflected by the semi-sphere surface, the reflected light passes through the center to illuminate on the curved surface reflector, so that all of the light emitted from the light source can pass through the center to illuminate on the curved surface reflector and is then reflected by the same so as to obtain a condensed light beam with the smaller converging angle and spot size.

Abstract: A light box is presented having a first frame and a second frame. The first and second frames each have many attaching rods. At least one removable fire retardant cover is connected to edges of the first and second frames. Many expanding rods are slidably connected to the expanding rods. Many light fixture attaching brackets are suitable for attaching to the second frame. The light fixture attaching brackets are adaptable to connect to a light bar having at least one light. The light bar is disposed between the first and second frames.

Abstract: A lighted handle includes an elongate light transmitting member that has first and second end portions. First and second support surface engageable mounting brackets carry the first and second end portions of the light transmitting member. A narrow beam light emitter is located in the first mounting bracket and has a light beam emitting end. The light beam emitting end faces the adjacent first end portion of the light transmitting member and is aimed longitudinally along the light transmitting member to make the same more visible.

Abstract: The floor lamp of the present invention includes a dimmer switch at a mid-point of the main supporting post in order to allow maximum accessibility for the users. The dimmer switch is contained within a compact and aesthetically pleasing dimmer housing, and is appropriately connected via electrical connections which extend through the main supporting post. An additional supporting post is provided, which runs from the base portion of the floor lamp to the dimmer housing to add structural stability to the floor lamp. By utilizing the dimmer switch in an elevated location, the need for mechanical connecting rods is eliminated. Further, additional design freedom is obtained.

Abstract: A display system comprising a high-intensity discharge lamp system equipped with a stabilizer, a reflector mirror coated with a heat-absorption film, a shutter, and a light-gathering lens; and a pole holding the high-intensity discharge lamp system at a desired height above the road or its vicinity. The display system of the invention enables drivers to easily see and locate the centerline, road shoulder, crosswalk, and traffic signs, even in the midst of rainstorm, dense fog, or blizzard.

Abstract: A navigation light system for a watercraft including an accessory light located at the bow or the stern that operates as a masthead or stern light, respectively, and that is located relative to the hull perimeter and shear line of the hull to reduce the glare perceived by an occupant of the watercraft. The glare is further reduced by the use of suitable masks to control the horizontal and vertical beam spread sectors of emitted light to minimize glare as perceived by an occupant of the watercraft. A docking light system that includes an accessory lamp that may be operated as a masthead light or as a stern light which is positioned to reduce glare as perceived by an operator of the watercraft and to increase visibility to other watercraft.

Abstract: An auxiliary rearview mirror and light assembly includes a non-incandescent light source, an auxiliary rearview mirror, a power source adapter, and a primary rearview mirror mounting assembly. The primary rearview mirror mounting assembly includes at least one fixed appendage and at least one adjustable appendage. The fixed appendage and the adjustable appendage are positioned in an opposing direction. The adjustable appendage has a bias element that exerts a force on the adjustable appendage in a direction towards the fixed appendage. The adjustable appendage is extensible to fit the primary rearview mirror.

Abstract: A light assembly, particularly for a motor vehicle, essentially consists of a housing covered by a clear, optically inactive covering pane in which at least one light unit is arranged which is formed of a light with a pertaining reflector. A screen, which is constructed as a semireflecting mirror, is arranged between the covering pane and the light unit. The screen separates a rearward light unit space accommodating the light unit from a forward light unit space formed by the screen and the covering pane, so that the rearward light unit space cannot be seen on the inside by a viewer looking in the direction of the light unit. The screen is transparent for the light emitted by the light when the light is switched on.

Abstract: The present invention relates to a vehicle headlight assembly having a lamp housing that is pivotally mounted to the vehicle body. One embodiment of the invention includes a lamp housing that is pivotally mounted to the vehicle body and includes a threaded aperture for receiving a threaded adjustment mechanism that is inserted through an aperture in the vehicle body and into the housing aperture. Rotation of the adjustment mechanism adjusts a position of the lamp housing relative to the vehicle body. Typically, a head portion of the adjustment mechanism is positioned on an exterior of the vehicle and is accessible by an operator of the vehicle from a normal operating position of the vehicle for adjusting the position of the housing relative to the vehicle body.

Abstract: An interior trim component for a vehicle includes a main body having an exterior surface for facing the interior of the vehicle. The body defines an internal cavity formed therein and an opening in the exterior surface. The cavity and the opening are in communication with each other. A source of light is mounted in the cavity such that the source of light is hidden from direct normal viewing within the interior of the vehicle.

Abstract: The invention relates to LED-based lamps, luminaires and lighting systems for buildings particularly, though not exclusively; for providing emergency light in the event of power failure. In particular it provides a light-emitting diode lamp comprising a support (26) and an array of light emitting diodes (58) on the support, an optical axis (72) passing through the middle of the array (58) and diodes increasing in number and increasing in inclination with distance from the optical axis (72). It also provides a luminaire (24) comprising a lamp as described above and a lens (30) having facets for generally un-deviated and un-reflected passage of light from off-axis diodes, and a building emergency lighting system comprising luminaires (24) as described above. In an alternative embodiment inclination of the light is through progressively increasing inclination of the facets.

Abstract: In a dermatoscope having a number of light-emitting diodes (7), which are arranged around optics (6), for indirect illumination of an examination area, an optical waveguide (1) is arranged in front of each light-emitting diode (7), the light input surface of which optical waveguide (1) faces the associated light-emitting diode (7) and on whose outer wall the light which is emitted from the light-emitting diode (7) is totally reflected toward the examination area. Instead of a number of optical waveguides (1), a single conical prism is preferably provided, whose base faces the light-emitting diodes (7) and whose cone angle is designed such that the light injected into the base surface from the light-emitting diodes (7) is totally reflected on the outer cone surface.

Abstract: In a liquid crystal display device according to the present invention, an upper end portion of a lamp housing is fixed on a main supporter so that the lamp housing can be made to face a side edge of a light guide. Light that can cause bright lines is eliminated or minimized through absorption or scattering by a main supporter. The main supporter is also thermally insulating and is placed between the lamp housing and a liquid crystal panel. Further, a thermally conducting bottom cover is placed under the backlight. Therefore, heat generated from the lamp is effectively channeled away from the light guide to prevent liquid crystal panel deterioration. Still further, although the upper and lower surfaces of the light guide is tightly fit between the lamp housing and the main supporter, wrinkles on a sheet reflector are prevented because the sheet reflector is not stacked between the lamp housing and a lower surface of the light guide.

Abstract: A power conversion unit and method for efficient conversion of power for one or more variable loads are disclosed herein. Power having a first form is supplied to one or more power conversion units (PCUs) connected to the one or more variable loads. The PCUs are adapted to convert the power from the first form to other forms suitable for use by the components of the destination system. Based at least in part on a predicted load requirement of the variable load, the operation of the PCUs can be controlled to provide sufficient power to the one or more loads at the appropriate time while minimizing wasted power generation by deactivating any unnecessary PCUs during a decrease in power consumption or by activating PCUs during an increase in power consumption.

Abstract: A power system, such as an integrated power module comprising a bi-directional converter, functionally combines a power inverter and a charger such as a charger for charging one or more electrical storage devices such as batteries and/or super- or ultra-capacitors. A first switch selectively couples one or more AC devices to the bi-directional converter, and/or a second switch selectively couples a boosting circuit to one or more DC devices and/or reverses polarity of the coupling. The power system may have electric vehicle and/or vehicle-to-grid applications.

Abstract: A switching power supply causes fewer losses, being capable of suppressing surges generated at a switching element, and providing improved conduction noise characteristics.

Abstract: A bi-directional flyback circuit includes a primary side switch that regulates the re-circulated energy to achieve substantially zero voltage switching and a secondary-side switch that regulates the output voltage. No feedback circuit between an output side and an input side of the bi-directional flyback circuit is needed for regulating the output voltage.

Abstract: A method for dynamically controlling regenerating energy flow and direct current bus voltage for an adjustable frequency drive system includes sensing a direct current voltage of a direct current bus; and sensing a plurality of alternating currents at outputs of an inverter. The sensed alternating currents are transformed to a stationary current vector. Voltage and frequency values are converted to a stationary voltage vector and an angle. The angle and the stationary current vector are transformed to a rotating current vector including torque and flux producing current components. An induction machine generating mode is determined when the torque producing current component reverses polarity. The voltage and frequency values limit the direct current voltage of the direct current bus at a predetermined threshold responsive to the generating mode. The stationary voltage vector and the angle are converted to pulse width modulated control inputs of the inverter.

Abstract: A power recycling system receives input power at an input and feeds back through an auxiliary output recycled power to the input for supplementing the input power for recycling energy of the recycled power that would normally be wasted so as to provide improved power efficiency. The system can have several configurations, including a system for testing power supplies under test, or can be any electrical device, system, appliance or electronic load having a power input and auxiliary output for feeding back recycled energy to the power input.

Abstract: An electromagnetic interference filter for filtering common mode current in an inverter device, the filter comprising: an inductor coupled in a least one power supply line to the inverter device; the inverter device having a ground return line, a capacitor coupled between the inductor and the ground return line; and a controlled switch coupled in series with the capacitor between the inductor and ground return line, and a control unit controlled in accordance with commutations in said inverter device whereby said switch is turned on when common mode current is drawn by said inverter device and turned off when common mode current ceases substantially to be drawn by said inverter device.

Abstract: The present invention relates a waveform transformation method and apparatus. It uses multilevel transformation module in series, and the output voltages of power modules at all levels are superposed to get the total output voltage, whereas each power transformation module realizes AC-to-AC direct conversion. The deviation between the output voltage and setting reference voltage at any time point is made as small as possible by selecting different transformation modules as current working circuit and selecting output voltage waveform of the each different transformation modules. The invention includes outputting n groups of electrical insulating AC and n transformation modules connected with AC. The wave transformation method and device of present invention eliminates the intermediate DC stage, so that the circuit is greatly simplified, the cost is reduced obviously. and improve working efficiency. It makes voltage and current harmonics to be reduced and obtains higher power factor.

Abstract: In a first aspect, a switched-mode power supply circuit topology electrical power can be transferred between a source and a load across an antisymmetric transformer having a primary coil and a secondary coil. First and second switches are provided for respectively switchably coupling the primary coil across the source and the secondary coil, the switches being bi-directional. A controller controls the switches so that they can act synchronously with a predetermined mark-to-space ratio, which determines the voltage ratio between, the circuit topology comprises an inductor and is for transferring power between a source and a load, a common rail coupling one voltage terminal of the source and one voltage terminal of the load. Bi-directional switches are controlled to couple the ends of the inductor to the voltage terminals of the source and the load to control the power transfer.

Abstract: An AC/DC adaptor module for preventing from inducing noises is provided. The adaptor for transforming an AC power from a socket having a grounded terminal into a DC power and providing an equipment having an input terminal, a negative terminal and a grounded piece with the DC power, includes a transformer having a positive output terminal and a negative output terminal for being electrically connected to the positive input terminal and the negative input terminal of the equipment respectively, wherein the negative input terminal of the equipment is connected to the grounded piece of the equipment, and a grounded wire having a first terminal electrically connected to the grounded piece of the equipment and a second terminal connected to the grounded terminal of the socket.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.

Abstract: A nonvolatile semiconductor memory includes a plurality of nonvolatile memory cells each having a gate, a drain and a source to hold data corresponding to a threshold voltage level. The memory further includes a reference current generation circuit which generates a reference current, the reference current generation circuit including at least one reference cell and an amplification circuit which amplifies a current flowing through the reference cell, and a ratio of an amplification factor of current in a program verify mode to an amplification factor of current in a data read mode is larger than 1, and a sense amplifier which compares the reference current with a current flowing through selected ones of the nonvolatile memory cells and reads data held in the selected ones of the nonvolatile memory cells.

Abstract: A system for pre-charging and equalizing potentials on a bitline pair in a DRAM integrated circuit. The system includes an equalization circuit at one position on the bitline pair and another equalization circuit at another position on the bitline pair. As charge is distributed between the bitlines and to/from the pre-charge potential source through multiple conduction paths, the pre-charge and equalization time of the bitlines is reduced.

Abstract: A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.

Abstract: An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.

Abstract: A flash memory structure and method of fabrication is introduced. The flash memory structure includes a plurality of parallel word lines positioned on a semiconductor substrate, a plurality of parallel source lines with first conductivity type positioned perpendicularly to the word lines and within the semiconductor substrate, two bit lines with first conductivity type positioned on two sides of each source line and within the semiconductor substrate, a doped region with second conductivity type positioned beneath and surrounding each bit line, a contact plug positioned in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line, and a gate positioned on an overlapped region of the semiconductor substrate and each word line.

Abstract: A bit line is connected to a data circuit for use in a program/read time. The data circuit includes first, second, and third data storage units. The first data storage unit is connected to the bit line. A first data transfer circuit is connected between the first and third data storage units. A second data transfer circuit is connected between the second and third data storage units. The second data storage unit has a function of forcibly changing a value of data of the first data storage unit based on the data stored in the second data storage unit.

Abstract: A nonvolatile semiconductor memory device includes a plurality of blocks each having a nonvolatile memory cell array, and a program potential generating circuit which supplies a program potential to the nonvolatile memory cell array, wherein the program potential generating circuit adjusts the program potential according to a first address signal selecting one of the blocks and a second address signal indicating a position of a write-accessed memory cell in the noted one of the blocks.

Abstract: A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

Abstract: A memory block of this flash memory includes 64×8 MONOS type memory cells arranged in 64 rows and 8 columns, 64 word lines respectively provided corresponding to 64 rows, bit lines respectively provided corresponding to 8 columns, and a source line commonly provided to all the memory cells. Accordingly, since the MONOS type memory cell is utilized as a one bit/cell memory cell and a conventional array configuration is employed, the manufacturing process and the configuration can be simplified.

Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory sub-blocks. During erase verification, the memory programs the erase register when a non-erased memory cell is located in a corresponding sub-block. Additional erase pulses can be selectively applied to sub-blocks based upon the erase register data. Likewise, erase verification operations can be selectively performed on sub-blocks based upon the erase register data. An address register is provided to store an address of a non-erased memory cell identified during verification. The address from the register is used as a start address for subsequent verification operations on the same array location.

Abstract: A method for predetermining the initial state of the memory cells of a static random access memory such that when the memory is powered up the predetermined initial states are attained. The initial states can be predetermined by modifying one or more physical or operational parameters of the MOSFETS comprising the memory cells.

Abstract: A method of identifying an integrated circuit device based on the initial state of certain memory cells within a memory array of the integrated circuit device. For many cells in the memory array the initial state is relatively consistent at each power-up, due to mismatches between the transistors that form each memory cell. Thus these consistent initial states provide a signature of the memory array and the integrated circuit device.

Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.

Abstract: A memory module recovery method involves previously storing a defective row address and a defective column address corresponding to a memory cell in a volatile memory determined as defective, and defective device information for discriminating the volatile memory determined as defective in a non-volatile memory, transferring the defective row address, defective column address and defective device information stored in the non-volatile memory to a volatile memory upon start-up of a system for holding the information in the volatile memory, and accessing a redundant memory cell instead of the memory cell determined as defective when receiving an address corresponding to the memory cell determined as defective, based on the defective row address, defective column address and defective device information held in the volatile memory.

Abstract: A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.

Abstract: A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

Abstract: There are provided at least one read word line 15, 16 and 17 for transmitting a read control signal to a memory cell, at least one read bit line 18, 19 and 20 for transmitting information of the memory cell to an outside according to activation of the read control signal corresponding to the read word line, at least one write word line 11 and 12 for transmitting a write control signal to the memory cell, and at least one write bit line 13 and 14 for transmitting external information to the memory cell according to activation of the write control signal corresponding to the write word line, wherein the read bit line and the write bit line are provided as alternately as possible and the read control signal and the write control signal are controlled so as not to be activated at the same time.