Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A constant current supply circuit generates a constant current according to a control voltage. A data read current passing through a tunneling magneto-resistance element constituting a memory cell during data write is set according to the constant current. Constant current supply circuit includes a voltage adjustment circuit generating a reference voltage adjustable according to an external input, a current source generating the constant current according to the reference voltage, and a voltage switch circuit transmitting the reference voltage to the current source as a control voltage during a normal operation.

Abstract: Disclosed are a data writing apparatus and a data writing/reading apparatus which can allow an upper-rank unit to properly complete data writing and reading when a double failure occurs, reads data from an address at which a failure has occurred during data correction at that address and completes writing data in a hard disk device when correction of data at the address at which the failure has occurred is completed. When data writing at a logical address of a logical disk is disabled due to a double failure, logical disk writing/reading means writes the data in a memory and reports proper completion of writing to an upper-rank unit. The upper-rank unit reads the data from the memory. When reported from write-enableness reporting means that writing at the logical address becomes enabled, the logical disk writing/reading means writes the data in the memory at the logical address of the logical disk.

Abstract: A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

Abstract: A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.

Abstract: A semiconductor memory device has an array of memory cells, an array of sense amplifiers selected at least two at a time by column lines, data bus lines that receive data read from the memory cell array by the selected sense amplifiers, a decision circuit that compares data read by two of the selected sense amplifiers, and an input-output buffer. Normally, the input-output buffer receives and outputs data from one or more of the data bus lines. In a test output mode, the input-output buffer receives and outputs comparison result data from the decision circuit. In a semiconductor memory device with multiple memory cell arrays, this arrangement enables data read from different memory cells in the same memory cell array to be compared, so that redundancy repair can be carried out efficiently.

Abstract: Disclosed is a magnetic memory apparatus which comprises a patterned magnetic recording medium in which multilayered films each having a first magnetic layer, a nonmagnetic metal layer or a nonmagnetic insulating layer and a second magnetic layer deposited discretely on a conductive electrode layer formed on a substrate, and a cantilever array having a plurality of cantilevers each having a conductive chip at its distal end. This provides a magnetic solid memory apparatus that has a large memory capacity and a super fast transfer rate, the merits of a hard disk apparatus, and a nanostructure and low power consumption, which are the merits of a semiconductor memory.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory sub-blocks. During erase verification, the memory programs the erase register when a non-erased memory cell is located in a corresponding sub-block. Additional erase pulses can be selectively applied to sub-blocks based upon the erase register data. Likewise, erase verification operations can be selectively performed on sub-blocks based upon the erase register data. An address register is provided to store an address of a non-erased memory cell identified during verification. The address from the register is used as a start address for subsequent verification operations on the same array location.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of latch circuits, first circuit, second circuit and third circuit. The memory cell array has electrically rewritable nonvolatile memory cells arranged therein. The plurality of latch circuits temporarily hold data read out from the memory cell array. The first circuit is configured to generate a first current varying in proportion to “1” or “0” of binary logical data of one end of the plurality of latch circuits. The second circuit is configured to generate a second preset current. The third circuit is configured to compare the first current with the second current. The number of “1” or “0” of binary logical data of one end of the plurality of latch circuits is detected based on the result of comparison between the first current and the second current.

Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

Abstract: A memory cell array of a semiconductor memory device includes a first sub array configured by a plurality of first cell units, a second sub array configured by a plurality of second cell units, and a non-memory cell region used for a backgate and arranged between the two sub arrays. Memory cells located on each side of the non-memory cell region are oriented in the same direction. Pairs of bit lines have substantially the same number of bit line contacts.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract: The invention relates to a memory circuit having a memory cell array. Memory cells in the memory cell array can be addressed via word lines and bit lines and can be written to via write amplifiers. Each of the write amplifiers is assigned to a plurality of bit lines. A datum can be written, in accordance with a write address, to a memory cell via the addressed bit line using the assigned write amplifier. An address decoding circuit is provided to simultaneously activate a plurality of the write amplifiers depending on a test mode signal so that the plurality of write amplifiers write the test datum present via the respectively assigned bit lines.

Abstract: A test cell for use in a semiconductor manufacturing operation allowing alignment of semiconductor devices to be tested to a test station. The test cell is well suited for testing semiconductor devices on carrier strips. To aid in alignment, the test cell includes a down-ward looking camera and a simple upward looking sensor. Fiducials are acurately positioned relative to the test site, which are easily detected by the simple sensor. A controller within the test cell uses the output of the camera and the sensor, in conjunction with position sensors on a robotic assembly, to determine relative positions of the devices to be tested and the test station and issue the appropriate commands to align the devices to the test station.

Abstract: A semiconductor memory device having an active restore weak write test mode for resistive bitline contacts. During the write margin test a circuit is used to block the bitline restore devices from turning off during the SRAM write cycle.

Abstract: A method for retrieving information from a database includes identifying a cylinder. The cylinder includes a plurality of data segments. The method also includes retrieving the plurality of data segments from the cylinder during a single retrieval operation. In addition, the method includes storing the plurality of data segments in a cache.

Abstract: Memory devices and methods are disclosed for selectively reading or writing rows or columns of memory cells in a ferroelectric memory array, wherein sense amps are selectively coupled with row lines or column lines and decoder outputs are coupled with column lines or row lines for row or column memory access operations, respectively.

Abstract: The semiconductor memory device includes a non-volatile programmable and electrically erasable memory cell with a single layer of gate material and a floating gate transistor and a control gate, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of gate material in which the floating gate is made extends integrally above the active area without overlapping part of the isolation region, and the transistor is electrically isolated from the control gate by PN junctions that will be inverse polarized.

Abstract: A small, flat rectangularly shaped electronic circuit card, such as one containing non-volatile memory, has a row of contacts mounted on bottom surfaces of a row of recesses extending along a short edge and an adjacent angled corner. At least one of the recesses opens to the angled corner and the remaining recesses open to the short edge. Two surface contacts are included in at least one of the recesses, while the remaining recesses each contain a single contact.

Abstract: A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.

Abstract: A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.

Abstract: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first case and a second case, a planar outline of the memory body is smaller than half of a planar outline of the memory card. The memory body is disposed so as to be positioned closer to a first end side as one short side of the memory card with respect to a midline between the first end side and a second end side as an opposite short side of the memory card positioned on the side opposite to the first end side. The other area than the memory body-disposed area in the first and the second case is used as another functional area.

Abstract: One semiconductor memory device according to the invention comprises a plurality of memory blocks, signal lines respectively connected to the plurality of memory blocks, and a control circuit connected to the signal lines, and the control circuit includes selection signal generator circuits for generating selection signals for selecting one memory block of the plurality of memory blocks by externally input address signals and for outputting the selection signals to the signal lines, and the lengths of the signal lines from the selection signal generator circuits to the respective memory blocks are longer in proportion to distances from the control circuit to the memory blocks. Thereby, parasitic load capacitances of the signal lines connected to the respective memory blocks in the wiring direction can be reduced, and the semiconductor memory device that operates with lower current consumption can be provided.

Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

Abstract: A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

Abstract: A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator.

Abstract: An adjustable current mode differential sense amplifier is provided. The amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier.

Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: A method, system and apparatus for management of dynamic memory in battery-powered devices. Information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.

Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

Abstract: A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle.

Abstract: A semiconductor memory having memory banks is disclosed. The memory banks each having memory cells arranged in X and Y directions, Y decoder for selecting Y-direction addresses of the memory cells and X decoder for selecting X-direction addresses of the memory cells are predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2, . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in anther one of the banks.

Abstract: A nonvolatile semiconductor memory device has a memory cell array having a memory cell and arranged in an array shape by connecting this memory cell to a bit line and a word line, an address input terminal inputting an address thereto, and a test mode circuit for outputting a test mode signal when a signal is inputted to a predetermined terminal among this address input terminal. The nonvolatile semiconductor memory device further has a row decoder connected to the test mode circuit and applying a voltage for a test to all the word lines in response to the test mode signal, a column decoder connected to the test mode circuit and setting all the bit lines to a non-selecting state in response to the test mode signal, and a monitor terminal connected to the test mode circuit and outputting the test mode signal.

Abstract: A memory cell configuration connects two trench capacitors to a bit line through a contact bit terminal. Trench capacitors are disposed in a regular grid. Word and bit lines are disposed in a mutually perpendicular crossover structure. An active region in which a selection transistor of an adjoining trench capacitor is introduced is disposed respectively between two trench capacitors of a row. Trench capacitors of two rows are laterally offset with respect to one another. Two active regions of adjacent rows are electrically connected to one another through a connecting line. Connected active regions form a common terminal region connected to a contact bit terminal, which is connected to a bit line. Bit lines are disposed between rows of trench capacitors and parallel thereto. By reducing the contact bit terminals, capacitances of the bit lines are reduced and interference signal transmission between word line and contact bit terminals is reduced.

Abstract: A ferromagnetic data layer of a magnetic memory element is formed with a controlled nucleation site. A Magnetic Random Access Memory (“MRAM”) device may include an array of such magnetic memory elements.

Abstract: A memory controller converts controller output signals output from a controller int memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A method for high precision charge pump regulation. The method of one embodiment comprises comparing an output feedback voltage with a reference voltage to determine whether the output feedback voltage is greater than or less than the reference voltage. In response to the comparison, either increasing a frequency for a clock signal if the output feedback voltage is less than the reference voltage, decreasing the frequency for the clock signal if the output feedback voltage is greater than the reference voltage; or disabling the clock signal if the output feedback voltage is much greater than the reference voltage. A pumped voltage is generated in response to changes to the clock signal.

Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

Abstract: Methods for enhancing the efficiency of SDRAM include dividing all of the data blocks into at least two parts and storing each part in a different bank of memory. Specifically, the first part of each data block is stored in the first bank of memory and subsequent parts are stored in other banks. Since every data block begins in one bank and ends in another bank, no memory bank is ever accessed twice consecutively. In this manner it is always possible to perform precharge and row activation for the next data access while finishing the present data access. The methods of the invention are illustrated in conjunction with the storage and retrieval of ATM cells.

Abstract: A system and method for updating electronic files and file components are provided. An upgrade client of a remote device receives a delta file block that codes differences between an original and a new version of a file. The upgrade client stores the delta file block in a first memory area. The upgrade client writes an original file block corresponding to the delta file block from an original memory area to a second memory area. A file updating algorithm generates an updated file block in the host device using the received delta file block and the original file block. This updated file block corresponds to the original file block, and is stored in a third memory area. The upgrade client updates the original file block of the remote device by writing the updated file block over the original file block in the original memory area of the remote device.

Abstract: With respect to gate wires 34P arranged in a P-ROM decoder 216P, two confronting gate wires 34P to which one bit of a digital signal representing a gradation level is input with being non-inverted or inverted are paired, and the width of the gate wire that contains the upper portion of the depletion type transistor 2P (kept under ON-state at all times) and from the depletion type transistor 2P until the enhancement type transistors 1P adjacent to the depletion type transistor 2P is set to a half of the gate wire width L on the transistor 1P inside the gate wires 34P.

Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits, each one allowing the selection of a respective group of matrix lines according to an address; each matrix line group includes at least one matrix line. Flag means are associated with each line group, that can be set to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

Abstract: To prevent process centralization to a master unit at the time of communications channel setting to slave units. Included are: a plurality of biometric information detection devices for detecting biometric information about attaching body such as heartbeat, and wirelessly transmitting corresponding biometric data; biometric information processing device for receiving the biometric data from each of the biometric information detection devices., and going through various types of processes such as a display process; and an information processing unit for receiving the biometric data of the biometric information detection devices from the biometric information processing device via a transmission/reception section. The biometric information detection devices determine their own communications channels, and transmit the biometric data to the biometric information processing device.

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: A semiconductor integrated circuit device is provided that enables testing of an optimum test unit in a memory macro under optimum test conditions when testing the memory macro provided in the semiconductor integrated circuit device. An inner bus IB is connected to a self-test circuit, and a self-test is performed on each physical region, which is a basic region in a physical address space of a memory cell array 11. The test is performed constantly with a physical region as a basic unit and redundancy remedy of each basic unit can be performed, irrespective of an outer bus OB set in a logical address space under the control of a logical macro. At the time of the self-test, a memory macro 1 can be tested using an internal clock signal iCLK or second-latency-value information L1 that is optimum for the memory macro.

Abstract: A method of using a memory chip that includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system.

Abstract: Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Abstract: A method of operating a memory system that includes generating an operating signal, controlling one or more electrical components with the operating signal and having a memory chip detect at the least a range of values for the operating frequency.

Abstract: A soluble stir stick composed of an edible material that is soluble in a beverage. The soluble stir stick is especially useful with hot beverages such as coffee or tea. The consumer stirs their hot beverage with the soluble stir stick and the soluble stir stick dissolves into the beverage, resulting in no waste. The soluble stir stick can be a solid stick made from one main soluble material. The soluble stir stick can be flavored or unflavored. For example, such flavorings could be chocolate or vanilla. The main soluble material of the soluble stir stick can also encapsulate columns of additives for the beverage.