Abstract: The invention particularly concerns a method for evaluating the Wobbe index of a fuel gas (G1) belonging to a given family of gases.

Abstract: Provided is a thermometer that is mounted on an engine incorporated in a vehicle and that measures the temperature of the engine during running of the vehicle. A temperature/resistance element included in the thermometer senses the temperature of the engine all the time. The sensed temperature is displayed on a display. Furthermore, a temperature warning indicator indicates whether the sensed temperature exceeds a warning set temperature. While monitoring the sensed temperature and temperature warning indication, a driver can accelerate the vehicle or shift the transmission gear so as to retain a load on the engine in an optimal state.

Abstract: Circuits and methods for generating a temperature dependent signal are described involving: generating a thermal voltage referenced positive temperature coefficient signal using a pair of transistors operating at different current densities; generating a transistor voltage referenced negative temperature coefficient signal using a transistor voltage of one of said pair of transistors; and subtracting one of said positive and negative temperature coefficient signals from the other of said signals to generate said temperature dependent signal, whereby the temperature dependence of said temperature dependent signal is greater than either of said subtracted signals.

Abstract: A method and system for automated temperature measurement is described. The system includes a programmable logic controller, a temperature measurement diode, an analog-to-digital converter coupled to the diode and the programmable logic controller, a current source coupled to the diode and configured to generate a first current and a second current different from said first current, and a processor coupled to the current source and to the analog-to-digital converter. The processor controls the current source such that the current source sequentially applies the first current to the diode at a first point in time and applies the second current to the diode at a second point in time. The processor also receives a first voltage across the diode measured when the first current is applied to the diode and a second voltage across the diode measured when the second current is applied to the diode. Based on the first and second voltages, the processor determines the temperature proximate the diode.

Abstract: A device for detecting and/or transmitting at least one environmental influence, and a method for producing the same. The device comprises at least one receiver element and an evaluation circuit that is substantially composed of organic functional material.

Abstract: Access noise in a spread spectrum communication system (100) is reduced by broadcasting a resource indicator message (116) from a base station (102) and is received by mobile stations (104) in the serving area (103) of the base station. The resource indicator message indicates which resources are supported (202) by the base station, as well as their present availability (204, 206, 208, 210). If a desired resource is not presently available (408), mobile stations will avoid requesting access to that resource (410). When the resource becomes available, access noise can be controlled by having mobile stations wait a randomly selected period of time (414).

Abstract: The existence of non-linearities in a spread-spectrum communications system can result in a transmitter generating code spurs projecting onto channels used to communicate information symbols between a transmitter and a receiver. The present invention provides a method of predicting at least one signalling code corresponding to at least one respective code spur by performing vector products of signalling codes expressed in a bipolar form to yield a signalling code where a code spur will occur.

Abstract: System and method for performing symbol boundary aligned searches of signals. A preferred embodiment comprises a search control unit (such as search control unit 725) that can determine a start and stop condition for a correlation based on a hypothesis, a searcher (such as searcher 705) which includes a multiplexer that can select a subset of samples of a received sequence based on the hypothesis and start and stop conditions. The search control unit can then wait for the occurrence of the start condition and assign the hypothesis to a correlator, which will correlate the subset of samples with a locally generated pseudo-random number sequence based upon the hypothesis.

Abstract: System and method for using pipelined vector processing in the detection of direct sequence spread spectrum signals. A preferred embodiment comprises a memory (such as memory 507) used to store a plurality of hypotheses, a PN sequence generator (such as PN generator 527) that can generate PN sequences for each of the hypotheses, and vector processing correlators and accumulators (both coherent and non-coherent). The PN sequence generator can arbitrarily generate PN sequences for any hypothesis, permitting the simultaneous testing of multiple hypotheses. A searcher controller (such as search control unit 319) can schedule access to different units in a pipelined fashion to increase the number of hypotheses tested in a given period of time.

Abstract: System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher. A preferred embodiment comprises the specification of a hypothesis for a particular communications network. The hypothesis can then be used to generate a pseudo-random number (PN) sequence that is provided to a searcher. The searcher can then make adjustments to the PN sequence to bring the PN sequence to conformity with requirements of the particular communications network. The adjustment to the PN sequence permits the use of a multi-mode searcher to perform searches for signals of various communications networks with minimal hardware dedicated to each communications network.

Abstract: System and method for efficient detecting of direct sequence spread spectrum signals using a searcher with batched processing. A preferred embodiment comprises a controller (such as the MCU 310) that writes sets of search parameters to a memory (such as the memory 315) to specify a group of hypotheses. A searcher (such as the searcher 305) reads the sets of search parameters from the memory and generates the groups of hypotheses from the sets of search parameters. The searcher then assigns the hypotheses to correlators and tests each of the hypotheses. Results from the testing can be written back to the memory.

Abstract: A jitter measurement apparatus for measuring a jitter of a signal under measurement includes: a delay circuit which generates a delayed signal that is delayed from the signal under measurement by a predetermined delay time; and a phase detector which detects an instantaneous phase error between the signal under measurement and the delayed signal.

Abstract: In an adaptive equalizing apparatus for MIMO (Multi-Input Multi-Output) turbo reception, an interference component in a received signal is subtracted therefrom using a replica of an interference component in an interference canceling part 31n, the subtracted output is filtered by a filter 32n, to cancel the remaining interference component and to perform multi-path combining, and in a degree-of-interference-cancellation estimation part 41n the degree of interference cancellation &bgr;(i) is set such that it is 0 for the iteration number i=1, 0.8+0.05 (i−1) for 5≧i≧2 and 1 for i≧6, and at the beginning of each iteration filter coefficients are calculated using &bgr;(i) and a channel estimation value in a filter coefficient calculating part 33n and the filter coefficient thus calculated are set in the filter 32n. An average value of soft decision symbol estimation values used in the interference canceling part may be used as &bgr;.

Abstract: Systems and methods are described for full bridge integral noise shaping for quantization of pulse width modulated signals. A method for full bridge integral noise shaping comprises: receiving a first and a second reference PWM signal; summing the first and second reference PWM signals with a quantization error correction; quantizing the sum into a first and a second output PWM signal; differentially integrating the first and second reference PWM signals and the first and second output PWM signals according to a full bridge integral noise shaping algorithm to obtain the quantization error correction. An apparatus for performing a full bridge integral noise shaping quantization of a pulse modulated signal, includes: a single-ended to differential conversion circuit; and a full bridge INS quantizer circuit, coupled to the single-ended to differential conversion circuit.

Abstract: A method of optimising the quality of a B picture by temporal scalability for an enhancement layer of a video bit stream, wherein the B picture B0.5 is predicted based on an SNR enhancement picture EI0 appearing in the highest enhancement layer of the bit stream. A prediction is achieved using foward prediction based on an enhanced picture already appearing in the same enhancement layer. As a result, information contained in the enhanced picture is not wasted.

Abstract: A video compression system is disclosed that is optimized to take advantage of the types of redundancies typically occurring on computer screens and the types of video loss acceptable to real time interactive computer users. It automatically adapts to a wide variety of changing network bandwidth conditions and can accommodate any video resolution and an unlimited number of colors. The disclosed video compression encoder can be implemented with either hardware or software and it compresses the source video into a series of data packets that are a fixed length of 8 bits or more. Sequences of one or more of these packets create unique encoding “commands” that can be sent over any network and easily decoded (decompressed) with either software or hardware. The commands include 3 dimensional copying (horizontal, vertical and time) and unique efficiencies for screen segments that are comprised of only two colors (such as text).

Abstract: The encoding rate controlling apparatus (9) is provided with a controlling device (9a, 9b) for performing a control for the encoding rate by changing a quantization scale code for quantizing the dynamic image information, and for conversing an average value of the encoding rate through all of the dynamic image information to an average value corresponding to a predetermined average value. The controlling device establishes on a time axis a plurality of change timings, each of which is a timing when the quantization scale code is changed, calculates the average value of the encoding rate corresponding to each of the established change timings, and performs the control for the encoding rate on the basis of the calculated average value.

Abstract: A method and system for coding a video sequence based on motion compensated prediction, wherein an interpolation filter is used to generate predicted pixel values for picture blocks in the video sequence. The interpolation filter for use in conjunction with a multi-picture type is shorter or having fewer coefficients than the interpolation filter for use in conjunction with a single-picture type. As such, the complexity of the interpolation filter for the multi-picture type can be reduced. Furthermore, the interpolation filter may be changed based on the characteristics of the block, the size and/or the shape of the block.

Abstract: A method and a system for accelerating the calculation of a motion estimation metric are described. During a single clock cycle, a first word and a second word of packed unsigned bytes are provided. Each byte in the first word represents a pixel in an image to be encoded and each byte in the second word represents a pixel in previously encoded image. Each byte in the second word of packed unsigned bytes is paired with one of the bytes in the first word of packed unsigned bytes. An error measure is calculated for each pair of bytes to compute a portion of the motion estimation metric for multiple pixels during a single clock cycle.

Abstract: In the case of a method for transformation encoding of moving-image sequences, motion vectors are estimated block-by-block, with which said motion vectors a motion compensation is carried out. The prediction error is transformation-encoded. According to the invention, the block size of the transformation encoding is coupled to the block size used in each case for the motion compensation.

Abstract: Mosaic-shaped block noise occurs when a compressed video signal is reproduced. This block noise is removed, but removing block noise from every block using a deblocking filter imposes a significant load on the deblocking filter. This load is therefore reduced by determining whether coding distortion removal (deblocking) is necessary, and applying a deblocking filter only when needed.

Abstract: An arithmetic block generates sum signal DVad and difference signal DVsu between the frames of image signals for every two frames from input image signal DVin. A bit rate proportion control block generates control signals CRad, CRsu for controlling the encoding bit rate proportion of the sum signal and the difference signal based on the sum signal DVad and the difference signal Dvsu. An encoding block generates encoded signal DTad with the encoding bit rate based on control signal CRad from the sum signal DVad using encoding process wherein the encoding bit rate can be altered on the basis of the control signals CRad. An encoding block also generates encoded signal DTsu with the encoding bit rate based on control signal CRsu from the difference signal DVsu.

Abstract: A method for transmitting a vector having at least two vector components, each of the vector components described in a frequency. Each vector is represented as a bit number with a predetermined number of bit levels. The bit numbers are encoded according to a priority of the bit levels and the encoded bit numbers are transmitted.

Abstract: A rate controller in a transcoder, which receives a stream of compressed frames carried in a bit stream, selectively determines whether to quantize and/or threshold slices of a frame carried in the stream of frames. The rate controller determines the input size of the frame and based at least in part upon at least a desired size, requantizes and/or thresholds the frame such that the output size of the frame is approximately the desired size.

Abstract: An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. An integrated circuit that services two satellite programs must generate and distribute corresponding time domain clocks to the various components of the integrated circuit. The transport block that receives one or more satellite signals from a demodulating block will extract program clock recover values from each signal being decoded and use these values to produce an error signal or control word that serves as an input to a clock generator. Based upon this input, the clock circuit will produce a corresponding time domain clock for each channel serviced by the integrated circuit. The output of the clock circuit is distributed to the various processing blocks within the integrated circuit that operate upon channel content received and processed by the transport block.

Abstract: The present invention relates to a device and a process for the stamping in real time by means of a stamping clock (2) of programs, as well as to a receiver and a broadcasting system containing such a device and a packet string obtained by such a process.

Abstract: A method for pre-suppress noise of an image at least includes the following steps: detecting whether the currently processed DCT coefficient value is equal to or less than a corresponding threshold used for this time during quantizing DCT (Discrete Cosine Transform) coefficients of a CIF (Common Intermediate Format) image blocks in sequence, if it is, setting the DCT coefficient to zero, then increasing the threshold of this time to be used as a threshold of next time for the DCT coefficient processing, otherwise recovering the threshold used for this time to a predetermined initial threshold, which will be used as the next time threshold for the next processing of DCT coefficient; detecting whether the increased threshold is greater than a predetermined upper limit of a threshold, if it is, substituting the increased threshold with the predetermined upper limit.

Abstract: A replica generating section 109 creates replicas of path #3 and path #4 for effective symbol A. A convolutional operation section 111 finds an interference part by performing convolution of the impulse response in the path #3 and path #4 replicas. This interference part is output to a subtraction section 104. In the subtraction section 104, the interference part is subtracted from the next OFDM symbol. That is to say, an interference part is found using effective symbol A, and that interference part (the part that leaks into the range in which an FFT of effective symbol B is performed) is eliminated from effective symbol B. By this means, the occurrence of distortion in effective symbol B can be prevented.

Abstract: A method and apparatus for deshuffling received shuffled data in a communication system supporting multi-level modulation. A transmitter encodes information bits and shuffles code symbols so that systematic symbols having a relatively high priority are disposed at high-transmission reliability positions and parity symbols having a relatively low priority are disposed at low-transmission reliability positions in a modulation symbol. A receiver demodulates received data and outputs a modulation symbol having a plurality of code symbols, stores the code symbols separately as systematic symbols and parity symbols in corresponding memory areas according to a deshuffling order corresponding to the shuffling, reads the stored code symbols, decodes the stored code symbols at a predetermined code rate, and thus outputs an packet.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: An encoder uses orthogonal dispersion sequences to encode symbols of an applied symbol stream as a series of microbursts that are separated by variable time intervals established by the time dispersion sequences. A decoder selects one or more series of microbursts from a composite set of microbursts received by the decoder, based on dispersion sequences at the decoder that match the dispersion sequences used to encode the one or more series of microbursts. Each selected series of microbursts is then conditioned to extract a corresponding symbol stream.

Abstract: A base station including a transmitting and receiving amplifier for amplifying CDMA signals exchanged with a mobile station; a radio stage connected to the transmitting and receiving amplifier for carrying out D/A conversion of a transmitted signal that undergoes baseband spreading, followed by quadrature modulation, and for carrying out quasi-coherent detection of a received signal, followed by A/D conversion; a baseband signal processor connected with the radio stage for carrying out baseband signal processing of the transmitted signal and the received signal; a transmission interface connected with the baseband signal processor for implementing interface with external channels; and a base station controller for carrying out control such as management of radio channels and establishment and release of the radio channels. The base station communicates with the external channels by mapping logical channels into physical channels. The CDMA signals are spread using a short code and a long code.

Abstract: A phase error corrector circuit and method are disclosed. In one embodiment, a phase error corrector circuit delays a PSK modulated signal and multiplies the delayed PSK modulated signal by the PSK modulated signal in order to generate a forward phase correction signal. The input signal is then mixed with the forward phase correction signal. In another embodiment, a phase error corrector circuit calculates a forward phase offset of a complex PSK modulated signal. The complex PSK modulated signal is phase shifted in a mixer by a phase difference offset in order to generate a phase corrected signal. A backward phase correction means calculates a backward phase offset based on the phase corrected signal. A subtractor subtracts the forward phase offset from the backward phase offset for outputting a difference phase offset to the mixer.

Abstract: A source-synchronous data receiver includes a storage device for sequentially storing data received from a data source, a data output device for sequentially outputting the data that is stored in the storage device, and a control for controlling the data output device, so that the data output device makes available particular data previously stored by the data storage device a programmable predetermined number of clock states after data is called for, e.g., a read command to the data source is initiated.

Abstract: Briefly, a method and apparatus to calculate cross-correlation values of complex binary sequences are provided. The apparatus may include a transformation unit and a cross-correlator. The cross-correlator may include a cross-correlation controller to provide, based on a type bit and a sign bit, a real component and/or an imaginary component of signals of complex binary sequences to a real accumulator and/or to an imaginary accumulator.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to detect and decode information is provided, wherein the method includes sampling a radio frequency (RF) impulse signal to generate a sample signal and storing the sample signal for a predetermined amount of time.

Abstract: An automatic gain control system combining both analog and digital gain units, both controlled by a common digital control system. The overall system gain settings are selected by a combination of analog gain settings and digital gain settings. The number of analog gain settings is less than the total number of system gain settings, so that the board or chip area required for the analog gain settings is reduced, while sufficient range is provided to maintain a good signal to noise ratio from an A/D converter. When a required gain adjustment exceeds one step of the analog gain stage, the system simultaneously adjusts the analog gain and the digital gain unit to provide a smooth transition.

Abstract: A multipath RAKE receiver, for combining various significant component signals of a multipath fading signal and correcting the frequency error and the phase error associated with each significant component signal, consists of a multipath splitter, a plurality of delay devices, a plurality of complex multipliers, a plurality of path strength estimators, a plurality of error signal generators, a plurality of complex scaling signal updating devices, an adder, a decision circuit, and a controller. First, the controller extracts information about each significant component signal and generates initial complex scaling signals and other control and timing signals. Under the control of the controller, each delay device delays a corresponding significant component signal for a different amount of time so that all the delayed significant component signals can be aligned up.

Abstract: A receiver of digital data bursts is provided comprising an antenna array, a first space time filter having filter coefficients initialised by estimation over just training data in a received burst and providing symbol estimates and a second space time filter having filter coefficients initialised by estimation over the received burst and providing symbol estimates. In use at least one pass to determine a symbol estimate in the received burst is undertaken by each space time filter and a selector operates to determine which of the first and second filters provides the symbol estimate closer to an expected value.

Abstract: In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

Abstract: A system, method, and apparatus for a multiple data rate communication system is presented herein. The communication system receives data samples that are either sampled at a narrowband rate or a wideband rate and provides various functions and services, such as echo cancellation, DTMF detection and generation, and call discrimination. For wideband signals, a down-sampled signal is provided for each of the foregoing function and service. The output of the function or services is then recombined with the wideband signal.

Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.

Abstract: A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.

Abstract: A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at least one clock control signal, wherein said control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels.

Abstract: Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.

Abstract: A technique for performing a frequency error correction process is provided that may be used in receivers of wireless local area network systems. The technique comprises a three-phase process generating a frequency approximation value based on a frequency error estimate, starting a channel estimation process that uses the generated frequency approximation value, refining the generated frequency approximation value, and compensating a frequency error using the refined frequency approximation value. Further, a corresponding integrated circuit chip and an operation method are provided. Using the technique for performing a frequency error correction process may provide high reliability, high precision and improved operation speed.

Abstract: The invention concerns an optical transmitter and receiver, and provides an improved timing extraction circuit for use in an optical receiver that uses a clock of a frequency equal to one half the data transmission rate, and a duty cycle deviation handling circuit for use in the optical transmitter and receiver. The timing extraction circuit uses a PLL circuit containing a phase comparator circuit for performing a phase comparison between a data signal of bit rate B (bits/s) and a clock signal of B/2 (Hz) at intervals of 2/B (sec), and comprises: a detection circuit for detecting the absence of an output of phase comparison information from the phase comparator circuit by receiving a data signal of a prescribed pattern; and a control circuit for controlling, upon detecting the absence, the phase of the clock signal in order to maintain synchronization.

Abstract: A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Abstract: Heat conductive fins are welded along both sides of a belt-like member with a margin left along edges of the both sides, thereby to form a unit. The unit is welded to a body with the heat conductive fins from the outside of each fin. Next, another belt-like member is covered over a gap between adjacent belt-like members, and these members are welded from the outside. With this arrangement, there is no need to weld in a narrow and long space and the entire welding step is carried out from the outside, which makes it easier to assemble a cask.

Abstract: Method for controlling the level of iron in feedwater of a BWR wherein an iron-containing sacrificial electrode in placed contact with the feed water dissolution of the electrode is induced at a rate which provides a desired level of iron in the feedwater