Abstract: One embodiment of the invention is directed to a semiconductor die package including a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.

Abstract: A socket (10) for a semiconductor package having a plurality of solder balls (5) at its bottom surface. The socket (10) includes a socket body having a plurality of contacts (11) arranged in a shape to correspond in arrangement to the solder balls (5) of the semiconductor package. Each of the contacts (11) has a first and second contact piece contactable with the corresponding solder ball (5) while clamping the corresponding solder ball (5) from both side. The socket (10) includes a placing plate (13) capable of moving between a first position and a second position. The first, or semiconductor placing, position is where the semiconductor package is placed on the placing plate (13) without contact of the solder balls (5) of the semiconductor package with the first and second contact pieces, and the second, or contact, position is where the solder balls (5) of the placed semiconductor package are contactable with the corresponding first and second contact pieces.

Abstract: A semiconductor multi-package module having a second package stacked over a lower ball grid array first package, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a ball grid array first package including a substrate and a die, affixing a second package including a substrate and a die onto an upper surface of the lower package, and forming z-interconnects between the first and lower substrates.

Abstract: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit with a semiconductor device, providing a plurality of semiconductor devices on said jig to house the devices into the openings, and fixing on a substrate then cutting the substrate to provide independent electronic devices. When the semiconductor device is in a form of chip, a support member attached to the chip will facilitate the handling of chips.

Abstract: Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the leadframe. The opposing niches are arranged such that an aperture and a mechanical key are formed within the leadframe material by the partial intersection of the niches. The key is encapsulated with mold compound to form a lock. An IC package mold lock in a leadframe is also disclosed, the lock having an aperture, a key, and mold compound encapsulating the key. Additionally, an IC package employing the leadframe-to-plastic lock is disclosed.

Abstract: The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-down flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: In a stacked package in which semiconductor chips are stacked in layers, in order to mount the semiconductor chips without damaging the semiconductor chips even when an upper semiconductor chip has a greater size, a first chip 12 is mounted on an interposer substrate 11. A second chip 13 having a larger size than that of the first chip 12 is mounted on the rear surface of the first chip 12. The second chip 13 is wire-bonded with respect to the interposer substrate 11 by wires 15. A base member 17 is disposed outside the first chip 12. The first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16. Solder balls 18 are provided on the opposite side of the chip-mounting side of the interposer substrate 11.

Abstract: An electronic package comprised of multiple chip stacks attached together to form a single, compact electronic module. The module is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A structure that allows for densely-packed, multiple chip stack electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic packages.

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Abstract: The present invention relates to a process and an apparatus for producing patterns, particularly high-resolution patterns, in films which are exposed to temperature gradients. In particular, there is provided a process for producing lithographic structures by exposing at least one film on a substrate to a temperature gradient, the temperature gradient generating forces in the film which cause a mass transfer in the film to thereby produce a lithographic pattern.

Abstract: A bonding method is provided in which an electronic component is connected via bumps to a substrate and the electronic component is packaged on the substrate. A surface of the substrate that packages the electronic component, a surface of the electronic component that is connected to the substrate, and a surface of the bumps undergo plasma processing. Subsequently, the bumps are heated to a temperature lower than a melting point of the bumps, and the substrate and the electronic component are compression bonded via the bumps.

Abstract: A semiconductor device using a lead frame as a wiring base member, in which a plurality of lead electrodes connected to a semiconductor chip through a connecting lead are arranged around the semiconductor chip having an upper surface and an under surface, and the semiconductor chip, connecting means and lead electrodes are integrally sealed. Each of the lead electrodes includes a thin internal lead portion having a connection part with the connecting means on the upper surface side, and a thick external electrode portion protruding toward the under surface side to form a connection part to outside. The seal resin layer has an underside which forms substantially the same surface as the under surface of the internal lead portion of the lead electrodes, and the external electrode portion protrudes downward from the underside of the seal resin layer.

Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate electrode electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1MV/cm to 2MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.

Abstract: The invention provides a method of manufacturing a thin film transistor capable of reducing the induced photo-electric current and thus improving the quality of the liquid crystal display, and reducing the number of required photo masks saving on the cost of fabrication. A stack structure is formed first, by successively depositing a gate electrode, a first insulation layer, a semiconductor layer, an ohmic contact layer, and a photoresist layer. Subsequently, a second insulation layer is deposited on the substrate, and the photoresist layer and the second insulation layer on the photoresist layer are removed in a lift-off process. Last, a source electrode, a drain electrode, a passivation layer, and a transparent electrode layer, are formed to complete the thin film transistor process.

Abstract: The present invention improves the quality of the TFT structure by avoiding photo-induced current, and lowers manufacturing costs by decreasing the number of masks required in the process, wherein the former is achieved by the stacked structure including a gate layer, an insulation layer, an amorphous silicon layer and an ohmic contact layer, and the latter is achieved by using the stacked structure as a mask and by exposing the substrate from the back surface.

Abstract: The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electrode and the damage of an element due to plasma are reduced as much as possible during anisotropic etching of an LDD formation process, by forming an LDD region in the state that a conductive protecting film is formed to cover a whole area of a substrate. Further, damage by charged particles during a process of doping a high concentration of impurity is also reduced.

Abstract: In the fabrication of a CMOS-TFT, non-selectively doping (for both of p- and n-type TFTS) and selectively doping (only for the n-type TFT) with p-type impurities (B: boron) are successively performed at very low concentrations to control the threshold voltages (Vthp and Vthn). More specifically, the Id-Vg characteristics of the p- and n-type TFTs are initially negatively shifted. In this state, non-selectively doping is performed positively to shift the p- and n-type TFTs first to adjust the Vthp to a specified value. Selectively doping is then performed/positively to shift only the n-type TFT to adjust the Vthn to a specified value. The threshold voltages of the p- and n-type TFTs constructing the CMOS-TFT can be independently and efficiently (with minimum photolithography) controlled with high accuracy.

Abstract: To realize TFT enabling high-speed operation by fabricating a crystalline semiconductor film in which positions and sizes of crystal grains are controlled and using the crystalline semiconductor film in a channel forming region of TFT, a film thickness is stepped by providing a stepped difference in at least one layer of a matrix insulating film among a plurality of matrix insulating films having refractive indices different from each other. By irradiating laser beam from a rear face side of a substrate (or both sides of a surface side and the rear face side of the substrate), there is formed an effective intensity distribution of laser beam with regard to a semiconductor film and there is produced a temperature gradient in correspondence with a shape of the stepped difference and a distribution of the film thickness of the matrix insulating film in the semiconductor film.

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).

Abstract: A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form carbon contain silicon oxide layers (110) and carbon containing silicon nitride layers (120) during the sidewall formation process. The carbon containing layers (110) (120) introduce carbon into the extension regions (100) and the gate region (30) during thermal annealing.

Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist patter of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist patter of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.

Abstract: A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect to the surface of the substrate is varied according to a predefined time schedule comprising a plurality of implanting periods.

Abstract: A silicon oxide film is formed on the back side of a semiconductor substrate by using a CVD apparatus of a single wafer processing type, with a silicon oxide film deposited on the upper part of trenches on the semiconductor substrate placed downward, to form element isolation comprising the silicon oxide film, and then a MISFET is formed. As a result, even in a manufacturing process using mainly the single wafer processing, in which a film is not formed or hardly formed on the back side of the semiconductor substrate, deterioration of a gate insulating film due to charging-up of the semiconductor substrate, which occurs at the time of plasma processing, for example, at the time of forming a gate electrode or ashing of a resist film, can be prevented, and contamination of the back side of the semiconductor substrate can be prevented. Further, by performing lift-off cleaning which slightly etches the silicon oxide film, the cleaning efficiency can be improved.

Abstract: A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component.

Abstract: A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region by depositing, planarizing and selectively etching a conductive material. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

Abstract: This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

Abstract: The invention relates to an organic fieId-effect transistor, to a method for structuring an OFET and to an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, the functional polymer in the mold layer in which recesses are initially produced by imprinting.

Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a semiconductor device.

Abstract: A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according to a manufacturing method of a semiconductor device using a hard mask. Covering the substrate by an electrically conductive film allover, the density of electric charge accumulated in a gate electrode in the plasma process such as anisotropic etching can be reduced, and the degradation due to plasma process can be reduced.

Abstract: Provided are a synchronous semiconductor device and a method for preventing coupling between data buses. The synchronous semiconductor device supports at least two kinds of bit configuration modes and includes a first data bus and a second data bus. The first data bus is used to transmit data in a first bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode. The second data bus is used to transmit data in the first bit configuration mode and a second bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode and the second bit configuration mode. The first data bus and the second data bus are arranged alternately. In using the device and method, it is possible to prevent coupling between the data buses without additional shielding lines by using the same kind of data bus, which is not used to transmit data, as the shielding line.

Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction; depositing a barrier metal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer; patterning and etching the top electrode layer; and completing the memory ar

Abstract: A capacitor having a tantalum-contained-dielectric layer is formed by a fabrication method including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a plasma vapor deposition (PVD).

Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroelectric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer, the conductive layer is patterned to form both the first and second electrodes.

Abstract: Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: Disclosed is a method of forming an isolation film in semiconductor devices using a shallow trench. Trenches are formed in silicon substrates of a memory cell region and a peripheral circuit region. The inert ion is then injected into the surface of the trench in the peripheral circuit region, thus forming an amorphous layer. Thereafter, an oxidization process is implemented so that a thick oxide film is grown due to excessive oxidization at the amorphous layer, thus making thicker the trench in the peripheral circuit region than the trench in the memory cell region by a thickness of the oxide film.

Abstract: A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: An interpoly dielectric is formed using only a single layer of oxide and a single layer of nitride to allow a reduction in thickness. The nitride is thermally grown on silicon in a nitrogen environment to maintain a high quality layer, while the oxide is deposited by LPCVD.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: In a semiconductor device capable of reducing operation fails and a method of manufacturing the same, gate structures and source/drain regions are formed on a semiconductor substrate. Nitride spacers are formed on both sidewalls of each of the gate structures. A first insulating interlayer is formed to cover the gate structures. Source pad electrodes are formed in each of the first contact holes and connected to the exposed source regions. A second insulating interlayer is formed on the first insulating interlayer. Metal lines for signal transmission are formed on the second insulating interlayer so as to make direct contact with the drain region of each group to electrically connect the drain regions with each other, while being isolated from the source pad electrodes.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (&egr;-field) results from the changing dopant concentration. The creation of this &egr;-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: A semiconductor device manufacture method has the steps of: (a) forming a gate electrode traversing a corresponding one of active regions and forming extension regions of source/drain in the active region on both sides of the gate electrode; (b) depositing first and second insulating films having different etching characteristics and anisotropically etching the first and second insulating films to form a side wall spacer on the side walls of the gate electrode; (c) selectively etching the first insulating film to form a retraction portion; (d) implanting ions to form source/drain regions in the silicon substrate; and (e) depositing metal capable of silicidation, and performing a silicidation reaction and form silicide regions also under the retraction portion.