Abstract: A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation.

Abstract: An isolated pocket of a substrate of a first conductivity type is formed by forming a field oxide layer having an opening. A first implant of a dopant of a second conductivity type is performed to form a deep layer of the second conductivity type. The deep layer includes a deeper portion under the opening and shallower portions under the field oxide layer. A mask layer is formed over the opening One or more additional implants of dopant of the second conductivity type are performed to form sidewalls in the substrate, each sidewall extending from the bottom of the field oxide layer into the deep layer, the deep layer and the sidewalls forming an isolation region enclosing an isolated pocket of the substrate.

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).

Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: A method includes forming a first damascene interconnect layer in a first dielectric. A first dielectric film is deposited on the first dielectric and on the first damascene interconnect layer. A conductor layer is deposited on the first dielectric film. The conductor layer is patterned, via a single mask, to form a first conductor and a second conductor. The first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.

Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.

Abstract: A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

Abstract: Method of forming a lightly phosphorous doped silicon film. A substrate is provided. A process gas comprising a phosphorous source gas and a disilane gas is used to form a lightly phosphorous doped silicon film on the substrate. The diluted phosphorous source gas has a phosphorous concentration of 1%. The phosphorous source gas and the disilane gas have a flow ratio less than 1:100. The lightly phosphorous doped silicon film has a phosphorous doping concentration less than 1×1020 atoms/cm3.

Abstract: An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N−-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N−-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N− region (1a) which is part of the N−-type silicon substrate (1). The N− region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N−-type silicon substrate (1).

Abstract: In order to fabricate a semiconductor component having a contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T gate, a method is described in which a self-aligning positioning of gate base and gate head is effected by means of a spacer produced on a material edge.

Abstract: The invention relates to a method for producing an electronic component, a stack of semiconductor chips, and an electronic component including a stack of semiconductor chips. The stack has at least a lower electronic module connected via flipchip connections to a central area of a rewiring substrate. The stack also has at least an upper electronic module with external contact surfaces connected via bonding connections to outer areas of the rewiring substrate.

Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Abstract: The present invention comprises the steps of forming a connection hole in an interlayer insulating film including an organic insulating film; forming an inorganic film covering on an upper surface of the interlayer insulating film and an inner surface of the connection hole; forming an organic film for filling inside the connection hole on an inorganic film; removing the organic film inside the connection hole so as to leave a part of the organic film at a bottom of the connection hole; forming a wiring trench connecting to the connection hole in the interlayer insulating film; removing the organic film inside the connection hole; removing the inorganic film; and forming a trench wiring by filling a conductive material in the wiring trench and inside the connection hole and forming a plug continuing from the trench wiring.

Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Abstract: A method for etching contact/via openings in low-k dielectric layers is described The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the low-k layers without excessive polymer formation, thereby eliminating polymer pinch-off during the etching of deep, high aspect ratio contacts and vias in sub-tenth micron integrated circuit technology. Vertical walled contact and via openings may be formed using a DUV photoresist mask and non-oxygen containing fluorocarbon etching plasmas. An additional hardmask is therefore not needed. For non-carbon containing low-k dielectric layers the openings may be etched in simple fluorocarbon plasmas without excessive polymer formation.

Abstract: Nanochannel electrophoretic and electrochemical devices having selectively-etched nanolaminates located in the fluid transport channel. The normally flat surfaces of the nanolaminate having exposed conductive (metal) stripes are selectively-etched to form trenches and baffles. The modifications of the prior utilized flat exposed surfaces increase the amount of exposed metal to facilitate electrochemical redox reaction or control the exposure of the metal surfaces to analytes of large size. These etched areas variously increase the sensitivity of electrochemical detection devices to low concentrations of analyte, improve the plug flow characteristic of the channel, and allow additional discrimination of the colloidal particles during cyclic voltammetry.

Abstract: Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A method and an apparatus utilized for thermal processing of substrates during semiconductor manufacturing. The method includes heating the substrate to a predetermined temperature using a heating assembly, cooling the substrate to the predetermined temperature using a cooling assembly located such that a thermal conductance region is provided between the heating and cooling assemblies, and adjusting a thermal conductance of the thermal conductance region to aid in heating and cooling of the substrate. The apparatus includes a heating assembly, a cooling assembly located such that a thermal conductance region is provided between the heating and cooling assemblies, and a structure or configuration for adjusting a thermal conductance of the thermal conductance region.

Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.

Abstract: In one implementation, an etching process includes forming a carbon containing material over a substrate and plasma etching at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming openings in a masking layer over a substrate and etching material beneath the masking through the openings. The masking layer is removed and the substrate is plasma etched at a temperature of at least 400° C. In one implementation, an etching process includes forming a residue over the substrate during a first etching and subsequently plasma etching to remove the residue. In one implementation, a chemical vapor deposition process includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor, plasma etching using a first gas chemistry, depositing a material over the substrate within the reactor using a second gas chemistry.

Abstract: A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.

Abstract: A method for reducing wafer damage during an etching process is provided. In one of the many embodiments, the method includes assigning a bias voltage to each of at least one etching process, and generating the assigned bias voltage before initiation of one of the at least one etching process. The method further includes applying the assigned bias voltage to an electrostatic chuck before initiation of one of the at least one etching processes. The assigned bias voltage level reduces wafer arcing.

Abstract: A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C5F8 and CHF3, and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.

Abstract: A method is disclosed that provides reliable removal of residues after chemical mechanical polishing of a damascene semiconductor structure so that the residues may be reliably removed without unduly affecting copper trenches and vias. To this end, the relative speed and/or the pressure applied to the substrate is increased and decreased, respectively, to operate the CMP apparatus in a regime with a significantly lowered removal rate while, at the same time, the hydrodynamic lubrication is avoided. Therefore, process time is increased and allows enhanced controllability of the process. Additionally, an improved selectivity of the removal rate of already cleared portions and of portions having residues formed thereon is remarkably improved.

Abstract: A substrate processing apparatus removes resist films formed on wafers by holding the wafers in a processing vessel and exposing the wafers to a mixed gaseous fluid of steam and an ozone-containing gas into the processing vessel. The inner surfaces, to be exposed to the mixed gaseous fluid, of the processing vessel and the surfaces, to be exposed to the mixed gaseous fluid, of component members placed in the processing vessel are coated with SiO2 film to protect the same from the corrosive action of the mixed gaseous fluid.

Abstract: A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(InXGa1-X) )Se2) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described.

Abstract: A known lithographic method is used to remove a thin mask layer, particularly a Si3N4 liner, on one side of a depression in a semiconductor configuration having a depression. An ion beam is directed obliquely onto the depression at an angle, which removes the thin mask layer in irradiated regions.

Abstract: Techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices. In one implementation, a carrier wafer is fabricated to include a membrane on one side of the carrier wafer. The membrane on the carrier wafer is then bond to a surface of a different, device wafer by a plurality of joints. Next, the carrier wafer is etched away by a dry etching chemical to expose the membrane and to leave said membrane on the device wafer. Transfer of membranes with a wet etching process is also described.

Abstract: When a hole pattern is formed on a film to be processed, a matching deviation margin at a lithography step is reserved by making a diameter of a bottom of a hole substantially equal to a diameter of an aperture of the hole. The method for manufacturing the semiconductor apparatus includes the steps of: forming a (first) mask material film on a film to be processed; forming a tapered open pattern on the (first) mask material film; and etching the film to be processed by using the (first) mask material film as a mask.

Abstract: According to the present invention, a dummy wafer is formed by forming a masking film on a rear surface of a silicon wafer; spray coating aluminum and depositing an aluminum film on a front surface of the silicon wafer; spray coating ceramics or carbon and depositing a ceramic film or carbon film on the aluminum film so that the aluminum film may be completely covered; and removing the masking film formed on the rear surface. Also, a dummy wafer can be formed by using an aluminum wafer as a wafer substrate and subjecting it to anodic oxidation to form a film of aluminum oxide.

Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.

Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.

Abstract: A system, method and product of dry-etching a semiconductor device are disclosed, the system having a material supply for forming a material layer on the semiconductor substrate, a pattern for disposing at least one photoresist pattern on the material layer, a dry-etching chamber for housing a dry-etching process of the material layer, a chiller for adjusting the temperature of the chamber, the semiconductor substrate, the material layer and/or the photoresist for the dry-etching process, a stage for loading the semiconductor substrate in the dry-etching chamber, and a dry-etchant supply for dry-etching the material layer while the integrity of the photoresist pattern is enhanced by the adjusted temperature; the corresponding method including the steps of providing a semiconductor substrate, forming a material layer on the semiconductor substrate, disposing at least one photoresist pattern on the material layer, adjusting the temperature of the chamber, the semiconductor substrate, the material layer and/or t

Abstract: In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.

Abstract: A local dry etching method for a SOI wafer capable of flattening an active silicon layer to a layer thickness of a target at a high throughput and to a required accuracy by using a multi-step local dry etching apparatus wherein the apparatus comprises first and second vacuum chambers, a small diameter nozzle, a large diameter nozzle of a diameter larger than that of the small diameter nozzle, an activated species gas generator for generating activated species gases to be blown out of each of the nozzles, each of feeding devices disposed in each of the vacuum chambers for providing a relative speed between the SOI wafer and each of the nozzles to conduct scanning and transportation device, in which the active silicon layer of the SOI waver is etched in the first vacuum chamber to remove the surface unevenness and the active silicon layer is etched to a required layer thickness in the second vacuum chamber.

Abstract: A method for circuit modification of an microelectronic chip having at least one conductor in an organic dielectric, includes applying a protective inorganic surface layer on top of the organic dielectric, forming at least one window in the protective inorganic surface layer to selectively expose the underlying organic dielectric, etching the organic dielectric in the window area to selectively remove the organic dielectric adjacent to the conductor, and performing at least one process that modifies the conductor.

Abstract: A dual damascene structure with a lesser degree of shoulder loss is achieved. In a method for forming a dual damascene structure having a shoulder in an organic low k film layer by dry-etching the organic low k film layer 208 and a mask layer 210 formed over the organic low k film 208 using at least two different mixed gases, a first step in which the mask layer is etched using a first process gas and then the organic low k film layer is etched into a predetermined depth by continuously using the first process gas and a second step following the first step, in which the organic low k film layer is etched using a second process gas are executed. Since a protective wall is formed at a side wall of a via during the first step, the extent of the shoulder loss occurring in the junction region where a trench and a via form a junction can be reduced.

Abstract: A manufacturing method for a COF semiconductor device according to the present invention comprises:

Abstract: The present invention presents an improved baffle plate for a plasma processing system, wherein the design and fabrication of the baffle plate advantageously provides for a uniform processing plasma in the process space with substantially minimal erosion of the baffle plate.

Abstract: A mask pattern is formed on a substrate by using a solvent absorbent mold having a pattern structure with a relief and an intaglio portion. A mask layer dissolved in a solvent to obtain fluidity is prepared on the substrate. The mold is pressed onto the mask layer with a predetermined pressure, and a portion of the mask layer that contacts with the relief portion of the mold is introduced into the intaglio portion thereof. Then, the mold absorbs the solvent contained in the mask layer to thereby solidify the mask layer. Next, the mold is separated from the substrate and the portion of the mask layer that contacts with the relief portion of the mold is removed, thus finally obtaining the desired minute mask pattern.

Abstract: Described herein is a method for producing a haze-free (Ba, Sr)TiO3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a substantially uniform desired crystal orientation, for example, (100), preferably by forming the film by metal-organic chemical vapor deposition at a temperature greater than about 580° C. at a rate of less than about 80 Å/min, to result in a film having about 50 to 53.5 atomic percent titanium. In another embodiment, where the BST film serves as a capacitor for a DRAM memory cell, a desired {100} orientation is induced by depositing the bottom electrode over a nucleation layer of NiO, which gives the bottom electrode a preferential {100} orientation. BST is then grown over the {100} oriented bottom electrode also with a {100} orientation.

Abstract: Precursor compositions for the CVD formation of low k dielectric films on a substrate, e.g., as an interlayer dielectric material for fabrication of microelectronic device structures. The precursor composition includes a gaseous mixture of (i) at least one aromatic compound, (ii) an inert carrier medium and (iii) optionally at least one unsaturated constituent that is ethylenically and/or acetylenically unsaturated. The unsaturated constituent can include either (a) a compound containing ethylenic unsaturation and/or acetylenic unsaturation, or (b) an ethylenically unsaturated and/or acetylenically unsaturated moiety of the aromatic compound (i) of the precursor composition. The low k dielectric film material may be usefully employed in integrated circuitry utilizing copper metallization, to achieve low RC time constants and superior microelectronic device performance.

Abstract: A process is provided for producing an image display device which includes a thin film semiconductor device. In accordance with the process, semiconductor crystal grains are grown in a transverse direction in a semiconductor film by modulating a continuous wave laser into a pulsed laser beam and then irradiating the pulsed laser beam on the semiconductor film.

Abstract: A connector block having an alarm-isolation circuit includes a first alarm input terminal, a second alarm input terminal, a first alarm output terminal, a second alarm output terminal, and at least one diode. The first and second alarm input terminals are operable for electrical connection with a two-wire alarm input. The first and second alarm output terminals are electrically connected respectively to the first and second alarm input terminals. The at least one diode is electrically connected between the first alarm input terminal and a first alarm output terminal, thereby forming a portion of the alarm-isolation circuit. The one alarm-isolation circuit is capable of forwarding an electrical signal to a remote location. In other embodiments, a diode is used between each alarm input terminal and alarm output terminal, thereby inhibiting feedback among the alarm output terminals and the associated alarm input terminal.

Abstract: A subsystem of an avionics system is operated in a first mode for receiving software via a port; and in a second mode in accordance with a circuit that includes a terminator coupled to the port. By using the terminator to convey information regarding a desired configuration for operation in the second mode, communication and wiring is avoided between subsystems of the avionics system for conveying such information. In one implementation, operation in the second mode includes performing a collision avoidance function (e.g., providing a TCAS advisory). Configuration information in accordance with the circuit may specify an arrangement of shared antennas between multiple transponders and/or mode changes related to using an antenna for a collision avoidance function in a hijack mode of operation.