Patents Issued in April 8, 2004
  • Publication number: 20040065915
    Abstract: A semiconductor element provided in a semiconductor device includes a built-in contact-type sensor having a sensor area formed on a circuit formation surface. Connection terminals are provided in an area other than the sensor area. A wiring board is connected to the connection terminals of the semiconductor element so that an end surface of the wiring board is positioned on the circuit formation surface. A protective resin part covers a part extending from the end surface of the wiring board to the circuit formation surface so as to protect a connection portion between the semiconductor element and the wiring board.
    Type: Application
    Filed: June 25, 2003
    Publication date: April 8, 2004
    Applicant: Fujitsu Limited
    Inventor: Toshiyuki Honda
  • Publication number: 20040065916
    Abstract: Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory device 300 may include a first memory element 100 and a second memory element 200 formed in a wafer 11 and mutually isolated by an element isolation region 38, a first impurity diffusion layer 16 and a second impurity diffusion layer 14. The first and second memory elements 100 and 200 include gate dielectric layers 20 and 120, floating gates 22 and 122, selective oxide dielectric layers 24 and 124 and third impurity diffusion layers 15 and 25, respectively, and also include a common intermediate dielectric layer 26 and a common control gate 28, and connected to the first and second impurity diffusion layers 16 and 14 that are commonly shared.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Inventor: Kenji Yamada
  • Publication number: 20040065917
    Abstract: Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Inventors: Der-Tsyr Fan, Chiou-Feng Chen, Prateep Tuntasood
  • Publication number: 20040065918
    Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.
    Type: Application
    Filed: October 2, 2003
    Publication date: April 8, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
  • Publication number: 20040065919
    Abstract: A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 8, 2004
    Inventors: Peter H. Wilson, Steven Sapp, Neill Thornton
  • Publication number: 20040065920
    Abstract: A trench-type MOSgated device including high conductivity regions formed at the bottom of its trenches and field relief regions at or below the bottom of its channel region.
    Type: Application
    Filed: June 25, 2003
    Publication date: April 8, 2004
    Inventor: Timothy Henson
  • Publication number: 20040065921
    Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
  • Publication number: 20040065922
    Abstract: A complementary metal-oxide semiconductor (CMOS) structure for a battery protection circuit and a battery protection circuit therewith. A tri-well technique or a buried layer technique is used for such CMOS structure to allow the battery protection circuit therewith to operate at different low voltage levels. Thereby, low voltage process can be realized to effectively reduce the cost of the chip and simplify the design.
    Type: Application
    Filed: April 24, 2003
    Publication date: April 8, 2004
    Inventor: Chi-Chang Wang
  • Publication number: 20040065923
    Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 8, 2004
    Applicant: Industrial Technology Research Institute
    Inventor: Chyh-Yih Chang
  • Publication number: 20040065924
    Abstract: A thin film transistor having a single LDD structure is provided. The single LDD structure is disposed between source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side spaced from a second one of the source/drain structures by essentially a semiconductor material. Another thin film transistor having a first kind of LDD and a second kind of LDD structure is also provided. The second kind of LDD structure is adjacent to the first kind of LDD structure. The process for manufacturing such thin film transistor is also disclosed.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 8, 2004
    Applicant: Toppoly Optoelectronics Corp.
    Inventor: An Shih
  • Publication number: 20040065925
    Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 8, 2004
    Inventor: Arup Bhattacharyya
  • Publication number: 20040065926
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Application
    Filed: August 5, 2003
    Publication date: April 8, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20040065927
    Abstract: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).
    Type: Application
    Filed: October 3, 2002
    Publication date: April 8, 2004
    Inventor: Arup Bhattacharyya
  • Publication number: 20040065928
    Abstract: A method for fabricating an UV-programmed P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Inventors: Tung-Cheng Kuo, Chien-Hung Liu, Shyi-Shuh Pan, Shou-Wei Huang
  • Publication number: 20040065929
    Abstract: Disclosed is an organic gate insulating film and an organic thin film transistor using the same, in which a photo-alignment group is introduced into an organic insulating polymer, so that an organic active film has superior alignment, thereby increasing mobility. Further, the organic active film has a larger grain size, enhancing transistor characteristics.
    Type: Application
    Filed: September 9, 2003
    Publication date: April 8, 2004
    Inventors: Bon Won Koo, In Sung Song, In Seo Kee, Hwan Jae Choi, Eun Jeong Jeong, In Nam Kang
  • Publication number: 20040065930
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Publication number: 20040065931
    Abstract: A method of producing a semiconductor component (300; 400; 500; 600; 700; 800; 900; 1000; 1100), in particular a multilayer semiconductor component, and a semiconductor component produced by this method are described, where the semiconductor component has in particular a mobile mass, i.e., an oscillator structure (501, 502; 601, 702) according to the preambles of the respective independent patent claims.
    Type: Application
    Filed: November 12, 2003
    Publication date: April 8, 2004
    Inventors: Hubert Benzel, Heribert Weber, Frank Schaefer
  • Publication number: 20040065932
    Abstract: The invention relates to a sensor with at least one silicon-based micromechanical structure, which is integrated with a sensor chamber of a foundation wafer, and with at least one covering that covers the foundation wafer in the region of the sensor chamber, and to a method for producing a sensor.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 8, 2004
    Inventors: Frank Reichenbach, Stefan Pinter, Frank Henning, Hans Artmann, Helmut Baumann, Franz Laemer, Michael Offenberg, Georg Bischopink
  • Publication number: 20040065933
    Abstract: An image sensor device (10) has a transparent base carrier (12) and a circuit substrate (18) having a first side (20) attached to one planar side (14) of the base carrier (12). The substrate (18) includes a peripheral area (24) and a window area (26) that allows radiation to pass therethrough. A sensor integrated circuit (40) having an active area and a peripheral bonding pad area is connected to a second side (22) of the substrate (18) via flip chip bumps (42). Solder balls (46) are attached to an outer peripheral area of the second side (22) of the substrate (18). The substrate (18) provides for electrical interconnect between the solder balls (46) and the flip chip bumps (42). The overall device has a thickness of less than about 1.0 mm.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Inventors: Chee Seng Foong, Kok Wai Mui, Lan Chu Tan
  • Publication number: 20040065934
    Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.
    Type: Application
    Filed: August 26, 2003
    Publication date: April 8, 2004
    Applicant: International Rectifier Corp.
    Inventors: Srikant Sridevan, Daniel M. Kinzer
  • Publication number: 20040065935
    Abstract: Power devices in which a low on-resistance can be obtained while maintaining a high breakdown voltage and a method for manufacturing the power devices are described.
    Type: Application
    Filed: September 12, 2003
    Publication date: April 8, 2004
    Inventors: Suk-kyun Lee, Cheol-joong Kim, Tae-hun Kwon
  • Publication number: 20040065936
    Abstract: An integrated circuit transistor structure can include a gate electrode on a substrate and a source/drain region in the substrate adjacent to the gate electrode. An anti-punchthrough layer, separate from the substrate, is adjacent to the source/drain region.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Inventor: Byung-Jun Park
  • Publication number: 20040065937
    Abstract: Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Inventor: Chia-Shun Hsiao
  • Publication number: 20040065938
    Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 8, 2004
    Inventors: Seok-Jun Won, Cha-Young Yoo
  • Publication number: 20040065939
    Abstract: An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating thick oxide region, which areally adjoins the main side of the semiconductor body, and having a thin oxide region, which, likewise, adjoins the main side and is disposed above the semiconductor region and also has a smaller layer thickness than the thick oxide region. A gate electrode is provided on the thin oxide region and terminal regions are provided in the semiconductor region. The capacitance described has a larger tuning range compared with transistor varactors. The integrated, tunable capacitance can be used, for example, in LC oscillators of integrated VCOs.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Inventors: Judith Maget, Marc Tiebout
  • Publication number: 20040065940
    Abstract: A micro-electro-mechanical system (MEMS) capacitive resonator and methods for manufacturing the same are invented and disclosed. In one embodiment, the MEMS capacitive resonator comprises a semiconductor resonating member and a polysilicon electrode capacitively coupled to the semiconductor resonating member.
    Type: Application
    Filed: July 31, 2003
    Publication date: April 8, 2004
    Inventors: Farrokh Ayazi, Siavash Pourkamali Anaraki, Seong Yoel No
  • Publication number: 20040065941
    Abstract: A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Kenneth W. Marr
  • Publication number: 20040065942
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser,
  • Publication number: 20040065943
    Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 8, 2004
    Inventor: Steven Kirchoefer
  • Publication number: 20040065944
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first pad, a second pad and a conductor. The first pad is formed on the interlayer insulating film and its circumferential edges are covered with a first surface-protecting film. The second pad formed on the interlayer insulating film facing the first pad across a second surface-protecting film, and its circumferential edges are covered with a third surface-protecting film. The conductor is provided continuously on the first pad, the first to third surface-protecting films, and the second pad.
    Type: Application
    Filed: March 18, 2003
    Publication date: April 8, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Jun Shibata
  • Publication number: 20040065945
    Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.
    Type: Application
    Filed: September 15, 2003
    Publication date: April 8, 2004
    Inventor: Steven R. Smith
  • Publication number: 20040065946
    Abstract: A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.
    Type: Application
    Filed: June 20, 2003
    Publication date: April 8, 2004
    Inventor: Chih-Pin Hung
  • Publication number: 20040065947
    Abstract: A semiconductor module includes a substrate having opposite surfaces, a semiconductor device, and a plate-shaped lead. The semiconductor device is mounted on the substrate, and has opposite surfaces and electrodes. One of the opposite surfaces is disposed on the substrate. The electrodes are disposed on the other one of the opposite surfaces. The plate-shaped lead has an electrode joint joined to the electrodes, a wiring joint joined to a wiring unit disposed outside the semiconductor device, and a connector connecting the electrode joint and the wiring joint. At least the electrode joint includes a high thermal conductor, and a low expander disposed in the high thermal conductor. The semiconductor module is good in terms of the reliability and assembly easiness when wiring the electrodes of the semiconductor device.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Inventors: Tomohei Sugiyama, Kyoichi Kinoshita, Takashi Yoshida, Hidehiro Kudo, Katsufumi Tanaka, Eiji Kono
  • Publication number: 20040065948
    Abstract: An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 8, 2004
    Inventor: Krishna Seshan
  • Publication number: 20040065949
    Abstract: A flip chip interconnect structure is formed on a bump pad of a chip, and includes an under bump metallurgy (UBM) formed on the bump pad, and a solder bump formed on the UBM. The solder bump includes tin and is further doped with metallic particles that are capable of reacting with tin in the solder bump to from an inter-metallic compound due to a thermal effect produced in use of a later fabrication process or an operation on the chip. Furthermore, the material of the metal particles is selected from a group consisting of copper, silver and nickel.
    Type: Application
    Filed: May 6, 2003
    Publication date: April 8, 2004
    Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng
  • Publication number: 20040065950
    Abstract: An electronic component package and method of fabrication is provided. The electronic component package includes a ceramic substrate and a plurality of bonding pads formed on the substrate, each pad forming an interface with the ceramic. Formed on the bonding pads is a bonding material, and a plurality of electrical leads are secured to corresponding pads by the bonding material. A layer of adhesive is formed over at least the interfaces between the pads and ceramic.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Inventors: Gaurav Agrawal, Jesse W. Booker, Christopher E. Sosh
  • Publication number: 20040065951
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Application
    Filed: August 11, 2003
    Publication date: April 8, 2004
    Applicant: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai
  • Publication number: 20040065952
    Abstract: An optical semiconductor product includes an integrated circuit chip having an optical sensor in its front face. The chip is attached to a support plate and electrical interconnection is made therebetween. A protective ring is fastened to the front face of the chip, around and at some distance from the optical sensor. A ring of encapsulating material is deposited to surround the periphery of the chip and lie between the front face of the support plate (2) and the protective ring.
    Type: Application
    Filed: February 5, 2003
    Publication date: April 8, 2004
    Inventor: Christophe Prior
  • Publication number: 20040065953
    Abstract: A semiconductor chip and a wiring strip are placed on a flat side of a base sheet. The semiconductor chip has parallel first and second surfaces. Electrodes are connected to the first surface. The electrodes all terminate in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. The wiring strip has one end portion connected to the second surface of the semiconductor chip and the opposite end portion terminating in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. A mold resin fills gaps between the semiconductor chip, the wiring strip, and the base sheet to lock the semiconductor chip and the wiring strip. The base sheet is removed.
    Type: Application
    Filed: July 2, 2003
    Publication date: April 8, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tomoki Kato
  • Publication number: 20040065954
    Abstract: The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 8, 2004
    Inventors: Martin W. Weiser, Nancy F. Dean, Brett M. Clark, Michael J. Bossio, Ronald H. Fleming, James P. Flint
  • Publication number: 20040065955
    Abstract: A semiconductor device (10) has a silicon substrate (12) with first and second transistors formed in the substrate. A copper interconnect (20) is coupled between an active region (14) of the first transistor and an active region (16) of the second transistor. A barrier layer (24) is disposed under the copper interconnect. The barrier layer contains titanium, aluminum, nitrogen, and oxygen with of composition ratio given as TiwAlxNyOz, where w=1, x=1.4±0.5, y=3.0±0.3, and z=1.0±0.2. The barrier layer limits migration of copper into the silicon. A silicide region (18) is formed in the active regions of the first and second transistors and makes electrical contact with the copper interconnect. A portion of the barrier layer resides between the copper interconnect and the silicide region. An oxide layer (22) is disposed between the copper interconnect and the substrate. A portion of the barrier layer resides between the copper interconnect and the substrate.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 8, 2004
    Inventors: Hyunchul C. Kim, Terry L. Alford
  • Publication number: 20040065956
    Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang
  • Publication number: 20040065957
    Abstract: A method of fabricating a semiconductor device includes the step of depositing a second insulating film on a first insulating film, patterning the second insulating film to form an opening therein, and etching the first insulating film while using the second insulating film as an etching mask, wherein a low-dielectric film is used for the second insulating film.
    Type: Application
    Filed: April 21, 2003
    Publication date: April 8, 2004
    Inventors: Kaoru Maekawa, Masahito Sugiura
  • Publication number: 20040065958
    Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).
    Type: Application
    Filed: February 24, 2003
    Publication date: April 8, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
  • Publication number: 20040065959
    Abstract: Lower electrode contact structures and methods of forming the same provide an interface having a large surface area between a lower electrode and the underlying layers. The lower electrode is in contact with a contact plug and an insulation layer in which the contact plug is buried. At least one supporting layer protrudes upright along the outer peripheral edge of the top surface of the contact plug. The interface between the lower electrode and the underlying layers is thus increased by the supporting layer(s) so that the lower electrode and the underlying layers will solidly adhere to each other.
    Type: Application
    Filed: August 6, 2003
    Publication date: April 8, 2004
    Inventor: Jeong-Ju Park
  • Publication number: 20040065960
    Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.
    Type: Application
    Filed: October 3, 2002
    Publication date: April 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: Frank D. Egitto, Elizabeth Foster, Raymond T. Galasco, Voya R. Markovich, Manh-Quan Tam Nguyen
  • Publication number: 20040065961
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a Cu wiring is not smaller than about 0.9 &mgr;m and smaller than about 1.44 &mgr;m and the width of another Cu wiring and the diameter of a plug are about 0.18 &mgr;m, there are arranged two or more plugs which connect the Cu wirings and another Cu wirings electrically with each other on the Cu wiring.
    Type: Application
    Filed: June 20, 2003
    Publication date: April 8, 2004
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Publication number: 20040065962
    Abstract: On the circuit surfaces of integrated circuit chips, there are adjacently laid out a power source pad for a power source wire at a plus voltage side and a power source pad for a power source wire at a minus voltage side. On a single-surface printed wiring board, a first set of two power source wires and a second set of two power source wires are flip-chip mounted with two power source pads of the integrated circuit chips respectively. The first and second sets of the power source wires are formed substantially in parallel with each other, by maintaining substantially constant wire widths and substantially constant wire interval. Near the outer periphery of the printed wiring board, the first and second sets of the power source wires are bent smoothly to follow the periphery.
    Type: Application
    Filed: March 25, 2003
    Publication date: April 8, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kohji Shinomiya
  • Publication number: 20040065963
    Abstract: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming wire bond z-interconnects between the upper and lower substrates.
    Type: Application
    Filed: August 2, 2003
    Publication date: April 8, 2004
    Applicant: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20040065964
    Abstract: A semiconductor package with a thermal enhance film mainly comprises a substrate, a semiconductor chip and a thermal enhance film. The semiconductor chip is electrically connected to the substrate and the thermal enhance film is formed on the back surface of the semiconductor chip. Therein, the thermal enhance film can be regarded as a heat transmission layer to transmit the heat to the outside and upgrade the thermal efficiency of the semiconductor package. In addition, the thermal enhance film can be made of a material comprising polymer. For example, the thermal enhance film is a thermally conductive polymer layer and can be regarded as a buffer layer to prevent the active surface of the semiconductor chip from being chipped. Furthermore, a manufacturing method to manufacture the semiconductor package is provided.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 8, 2004
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Chi Lee, Chih-Huang Chang, Chian-Chi Lin, Cheng-Yin Lee