Abstract: A package for power converters in which all parts are electrically connected with one multi-layer circuit board. A sub-package with at least a power-dissipating chip, having a bare top up-facing heat-slug is electrically connected with the board by a plurality of symmetric leads. A heat spreader is directly attached onto the bare top heat-slug of the sub-packages, planar magnetic parts and top surfaces of other components with thermally conductive insulator. The heat dissipated by the sub-packages is transferred to the attached heat spreader by the bare top heat-slug, and further transferred to the ambient. The assembly features compact and inexpensive power converter package with improved electrical performance and enhanced thermal management.

Abstract: A heat sink assembly includes a back plate (10), a clip (20) and a heat sink (50). The back plate is attached below a motherboard (60) on which a CPU (63) is mounted. The heat sink is attached on the CPU. Two posts (13) of the back plate extend through the motherboard and the heat sink. The heat sink includes a base (51) and fins (55). A longitudinal channel (57) is transversely defined through the fins. The base defines a recess (53) under the channel fittingly receiving an annular disc (58) therein. The clip includes a pressing portion (22) received in the channel, and two locking portions (29) engaging with the corresponding posts. A bolt (40) is screwed through the pressing portion to abut against the disc. By adjusting a depth to which the bolt is screwed, the clip can provide adjustable pressure acting on the heat sink.

Abstract: A sectional computer housing includes a plurality of frame posts and a plurality of sectional panels molded using aluminum extrusion. Each of the frame posts is provided with a screw groove at one side thereof and a track at two adjacent sides to the side having the screw groove, respectively. Each of the sectional panel having a turtledove tail-shaped protruding seat at one end thereof and a track at the other end thereof. A plurality of sectional panels is similarly fastened to one another using the protruding seats and the tracks at one side thereof for forming side, top or bottom panels. Outermost protruding seats and the tracks are coordinated with the tracks of the frame posts, and further positioned by longitudinally penetrating screws through the sectional panels and into the screw grooves of the frame posts, thereby assembling into a computer housing having any desired dimensions.

Abstract: The invention is related to a fixture device for motherboard module by placing two fixing plates on the locational surface of a major control device. A Π-shaped slide way with the same width as the motherboard module is formed on the base plate below the fixing plate. Additionally, a locating button in front of the opening of the slide way is used to secure the motherboard module into the slide way. Through this approach, the motherboard module can be easily installed/disassembled by pressing the locating button without using any tools or test fixtures.

Abstract: A server system includes a plurality of printed circuit assemblies. The server system includes a chassis for housing the plurality of printed circuit assemblies. A server management card coupled to the plurality of printed circuit assemblies monitors and manages operation of the server system. The server management card receives and stores status information from the plurality of printed circuit assemblies. A first LCD panel is mounted on a first side of the chassis and is coupled to the server management card. A second LCD panel is mounted on a second side of the chassis and is coupled to the server management card.

Abstract: Disclosed herein is an electronic device including a cabinet and a shelf accommodated in the cabinet. The shelf has a floating mechanism and a plurality of guide rails for guiding a plurality of printed circuit board units. The floating mechanism includes a plurality of holes formed through the shelf, each of the holes having a first diameter; a plurality of tapped holes formed through the cabinet so as to respectively correspond to the holes of the shelf; and a plurality of screws inserted through the holes of the shelf and threadedly engaged with the tapped holes of the cabinet, respectively, each of the screws having a second diameter smaller than the first diameter. The cabinet has a plurality of first guide pins, and the shelf has a plurality of second guide pins each having a diameter smaller than that of each first guide pin.

Abstract: An apparatus and method for retaining a length of fiber optic cable to a circuit board includes a body portion. The body portion of the apparatus includes at least a pair of spaced legs extending from the body portion, each of the legs is adapted to be received in a mounting opening formed in the PC board. Each of the spaced legs includes a foot portion adapted for securing the body to the circuit board and at least a pair of spaced arms extend from the body portion defining a slot between the arm and the body portion for receiving and retaining a portion of the length of fiber optic cable. The arms are spaced a distance from each other for retaining the fiber optic cable in an arc having a radius greater than a minimum bend radius of the fiber optic cable.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makesit possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: A power supply structure includes a first circuit board, a second circuit board, a first connecting part and a second connecting part. The second circuit board is horizontally disposed above the first circuit board, a first connecting part electrically connected between the first circuit board and the second circuit board for transmitting signals of the first circuit board and second circuit and a second connecting part electrically connected between the first circuit board and the second circuit board for conducting currents of the first circuit board and the second circuit.

Abstract: Shielding for a blade server style computer wherein each individual blade is surrounded with shielding.

Abstract: A shielding cage assembly (10) for shielding a plurality of transceiver modules therein includes a conductive body cage (1), a conductive cover cage (2) and a plurality of dividing walls (3), which cooperatively define a plurality of hollowed spaces for receiving the transceiver modules therein. Retaining tabs (121), (311) are respectively formed on the body cage and the dividing walls, and engage in a corresponding plurality of slots (24a, 24) defined in the cover cage to hold with the cover cage to the body cage and to fix the dividing walls between the cover cage and body cage.

Abstract: The invention employs a coreless isolated transformer, with associated electronic circuitry, for providing an initial bias and enable signal for control and drive circuitry that is referenced to the output of a converter. The improvement is accomplished by embedding the transformer primary and secondary windings into a multi-layer PCB so that the transformer does not occupy space on the top and bottom surfaces of the PCB The initial bias voltage is used to initialize operation of the control circuit when referenced to the output side of the converter. Thus, complete regulation and drive signals are generated on the output side.

Abstract: A method for controlling a parallel array of rectifier bridges includes outputting control signals to repetitively fire bridge elements; skipping repetitive firing of the elements for one out of plural counts; sensing temperatures of the elements; averaging some of the sensed temperatures to provide a corresponding average temperature for each of the parallel bridge elements; comparing one of the sensed temperatures to the corresponding average temperature; increasing the counts when the sensed temperature of one of the elements is less than the corresponding average temperature, or decreasing the counts when the sensed temperature of the one of the elements is greater than the corresponding average temperature; and setting the counts to a first predetermined value when the sensed temperature of the one of the elements is greater than a second predetermined value above the corresponding average temperature.

Abstract: An AC/DC converter includes a resonance converter (A3) which is suitable, for example, for operation with different AC line voltages from different AC power grids. The AC/DC converter further includes a bridge circuit (A4) drivable as a full-bridge circuit and as a half-bridge circuit, an arrangement (A2) working as an up-converter coupled, at least via a capacitor, (C2) to the resonance converter (A3), and a transformer (T) in the resonance converter (A3) and realizing a point (7) at which the arrangement (A2) is capacitively (C2) coupled to the resonance converter (A3). The primary winding of the transformer (T) is divided and this dividing point is arranged as the point (7).

Abstract: An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and delayed to the subsequent clock cycle. A FeRAM memory cell having two ports is needed so that consecutive operations do not conflict with each other. A read operation is initiated through a first port in a first clock cycle. In the subsequent clock cycle, the rewrite finishes through the first port. The next operation utilizes the second port, without conflicting with the rewrite process. By alternating ports used in each clock cycle, the rewrite step is hidden in the subsequent clock cycle to shorten the read operation. In an alternate method, all read operations are initiated through one port, while the second port is reserved exclusively for write operations and rewrites.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n×n (e.g., four) memory cells alternatively selected according to a combination of n (e.g., two) pairs of positive and negative phase signals and provided to output the positive and negative phase signals according to the data stored in the selected memory cell, variable wiring unit provided with signal lines for inter-connecting the variable logical circuits and switching elements for connecting/disconnecting signal lines inter-secting to each other, a wiring connection state storage memory circuit where the states of the switching elements are stored.

Abstract: A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.

Abstract: Leakage current from non-selected memory cells is substantially eliminated by placing a negative voltage on the selection line of the non-selected cells. This negative voltage on the gate of the access transistors in the cells reduces the leakage current that would otherwise leak onto a shared sense line if the selection line were biased at 0 volts. In one embodiment the pre-charge voltage on the affected sense line is reduced so that the difference between the pre-charge voltage and the negative voltage does not exceed the design voltage of the transistors in the memory cells.

Abstract: A unit memory cell comprises first and second field effect transistors of a first conduction type, third and fourth field effect transistors of a second conduction type, and first and second resistance elements. A gate electrode of the first transistor is connected to a second node, a gate electrode of the second transistor is connected to a first node, a series connected structure constructed by connecting a source/drain path of the third transistor and the first resistance element in series is connected between the first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of the fourth transistor and the second resistance element in series is connected between the second node and a second bit line paired with the first bit line, and both gate electrodes of the third and fourth field effect transistors are connected to a word line.

Abstract: The present invention is aimed at decreasing the current required for writing in a magnetic random access memory (MRAM), and power consumption thereof. In a magnetic random access memory of the present invention, information is written in memory elements arranged in a same row or column by performing once each of the first information writing step of applying a first magnetic field to put memory elements in the high-resistance state, and the second information writing step of applying a second magnetic field to the memory elements in which the first information has not been written to write information in all memory elements in the same row under recording of information.

Abstract: Systems, devices and methods are provided for magnetic memory elements with low remanence flux concentrators. Improved bit yield is attributable to reduced remanence in the flux concentrator. Remanence provides the memory element with a biasing magnetic field. The flux concentrator includes anisotropy aligned with an appropriate conductor. One aspect of the present subject matter is a memory cell. One memory cell embodiment includes a magnetic memory element and a flux concentrator operably positioned with respect to a conductor. The conductor is adapted to provide a current-induced magnetic flux to the magnetic memory element. The flux concentrator includes an easy axis of magnetization aligned with the conductor and a hard axis of magnetization orthogonal to the easy axis of magnetization. Other aspects are provided herein.

Abstract: A read block is constituted of a plurality of TMR elements arranged in a lateral direction. One end of each of the TMR elements in the read block is connected in common, and connected to a source line via a read select switch. The other ends of TMR elements are independently connected to read bit lines/write word lines. The read bit lines/write word lines are connected to common data lines via a row select switch. The common data lines are connected to a read circuit.

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Abstract: A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.

Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of rows and columns disposed substantially in a rectangle, with a plurality of word lines coupled with memory gate electrodes intersecting a first side of the rectangle substantially perpendicularly, a plurality of bit lines coupled with memory drain-source current paths intersecting a second side of the rectangle substantially perpendicularly (the second side also substantially perpendicularly intersecting the first side), a row select circuit being disposed at the first side for coupling with the word lines, and peripheral circuitry including a column select circuit and a sense circuit being disposed at the second side.

Abstract: The nonvolatile memory includes a nonvolatile memory circuit that possesses a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration, a program control circuit that writes information into the nonvolatile memory circuit, a volatile latch circuit that latches information read from the nonvolatile memory circuit, and a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuit. In response to the instruction of the readout operation, the readout control circuit supplies the operating voltage for the static latch operation to the nonvolatile memory circuit, and stops the supply of the operating voltage, after completing the latch operation.

Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.

Abstract: In a low-amplitude driver circuit of the present invention, a P-channel MOS transistor is provided between the output signal line to be driven and the internal power supply line, and control is performed so that this P-channel MOS transistor turns on when the low-amplitude driver circuit outputs a high level (Vcc-Vtn). As a result, the output signal line substantially does not float at or above Vcc-Vtn.

Abstract: A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

Abstract: A data memory for storing data, having a memory cell array (2), which comprises a large number of memory cells (3), each of which can be addressed by means of a memory cell select transistor (4) connected to a word line (9) and to a bit line (13) and which have a storage capacity for storing one data bit, the memory cell array (2) containing redundant memory cells (3′), which are provided in order to replace memory cells (3) which have been produced wrongly, by means of readdressing, and having read amplifiers (22), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell (3) via an associated bit line (13) and are supplied with a buffered supply voltage, the redundant memory cells (3′) which have not been readdressed being connected to the associated bit lines (13′) and additionally buffering the supply voltage for the read amplifiers (22).

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A system for repairing a memory column includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable to receive a control signal indicating an error in the first data bit. The control generator is operable to generate a select signal, and the multiplexer is operable to select the second data bit in response to the select signal.

Abstract: A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.

Abstract: A nonvolatile semiconductor memory device and a method for testing the same by which the faulty memory device causing the unexpected data rewrite can be surely excluded. The test is carried out to judge whether or not a memory element storing a binary information corresponding to presence or not of an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated therefrom, the semiconductor substrate including a source and a drain formed thereon, can exactly hold the electric charge injected to the floating gate in advance. In the test, an approximately equal voltage is applied to the source and drain as the voltage for drawing out the electric charge held in the floating gate.

Abstract: An integrated memory having a memory cell array: including word lines for selecting memory cells, bit lines for reading out or writing data signals of the memory cells, a precharge circuit for precharging at least one of the bit lines to a precharge voltage that differs from a supply voltage of the memory. The precharge circuit has a loop regulating circuit for setting the precharge voltage using an actual voltage of the one of the bit lines. The precharge circuit makes it possible to reduce the power loss of the memory in conjunction with low area consumption.

Abstract: The invention concerns a device for reading a storage cell (4), comprising a reading differential amplifier (18) having a first input terminal (16) connected to a column of cells (10) and a circuit (34) designed to feed to a second input terminal (20) of the amplifier (18) a reference voltage (Vref). The circuit (34) comprises means (38) for storing the voltage of said column and means (38, 40, 42) for applying as reference voltage (Vref) the stored voltage modified by a predetermined quantity.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.

Abstract: Embodiments of the present invention generally provide a soft error-resistant latch circuit. The latch circuit generally includes first and second inverters, each formed by at least two transistors. At least one delay element decouples the gate of at least one of the transistors of one of the inverters from a diffusion area of at least one of the transistors of the other inverter.

Abstract: An electrostatic discharge (ESD) device used with a high-voltage input pad is described. The ESD device serves as a secondary device of a two-stage protection circuit, and comprises a substrate, a first MOS transistor and a second MOS transistor. The first MOS transistor is disposed on the substrate and comprises a first gate, a first drain and a first source, wherein the first gate is coupled to a bias Vg1, and the first drain is coupled to the high-voltage input pad. The second MOS transistor is disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first MOS transistor.

Abstract: A nonvolatile semiconductor memory unit which is provided with a nonvolatile semiconductor memory and a controller for performing a read operation, a write operation and an erase operation on the nonvolatile semiconductor memory unit, including an external power source which derives its supply of electric power from outside, an internal power source which derives its supply of electric power from a secondary battery and is connected to the nonvolatile semiconductor memory and the controller, a voltage detecting circuit for detecting a voltage of the external power source and a switching circuit which is provided between the external power source and the internal power source and is subjected to on-off control by an output of the voltage detecting circuit so as to enable and disable the external power source, respectively.

Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.

Abstract: A single integrated circuit flash memory controller is provided. When the CPU is operating, the operating time of the external ROM and all the flash memory devices are designed or programmed to function in an alternative manner, for example, the flash memory device will not be activated while the external ROM is operating to retrieve the program code. On the contrary, while data is being retrieved from the flash memory device, the CPU will be in a waiting status, in other words, the CPU does not function to retrieve the program code from the external ROM while the data is being retrieved from the flash memory device. Accordingly, this design makes it possible for the single integrated circuit flash memory control to accommodate required connections for connecting with the external ROM as well as all the flash memory device without the need to increasing pin terminals or the size of the integrated circuit package.