Abstract: A Group-III nitride semiconductor device including a crystal substrate, an electrically conducting Group-III nitride semiconductor (AlXGaYIn1−(X+Y)N: 0≦X<1, 0<Y≦1 and 0<X+Y≦1) crystal layer vapor-phase grown on the crystal substrate, an ohmic electrode and an electrically conducting boron phosphide crystal layer provided between the ohmic electrode and the Group-III nitride semiconductor crystal layer, the ohmic electrode being disposed in contact with the boron phosphide crystal layer. Also disclosed is a method for producing the Group-III nitride semiconductor device, and a light-emitting diode including the Group-III nitride semiconductor device.

Abstract: A light emitting device employing gallium nitride type compound semiconductor which generates no crystal defect, dislocation and can be separated easily to chips by cleavage and a method for producing the same are provided. As a substrate on which gallium nitride type compound semiconductor layers are stacked, a gallium nitride type compound semiconductor substrate, a single-crystal silicon, a group II-VI compound semiconductor substrate, or a group III-V compound semiconductur substrate is employed.

Abstract: A photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices that are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word. Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electrical signal. The voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices may be supplied by voltage divider networks coupled between the cathode terminal of the devices and ground potential or voltage reference sources coupled to the input terminals of the heterojunction thyristor devices. In this manner, electrical signals whose magnitude corresponds to contribution of each optical bit in the digital word are produced.

Abstract: An impurity precipitation region is formed by introducing an impurity, e.g., oxygen, into a silicon substrate or a silicon layer and thermally treating it, and performing high selectivity anisotropic etching with the precipitation region used as a micro mask. Thus, a cone (conic body or truncated conic body having an annular leading end) having a very sharp and slender needle shape with an aspect ratio of about 10 and a diameter of about 10 nm to 30 nm in the vicinity of its leading end is obtained with the micro mask used as the top. By forming an insulation layer and a drive electrode such as a gate electrode around the cone, the cone can be used for a field emission device, a single electron transistor, a memory device, a high frequency switching device, a probe of a scanning type microscope or the like.

Abstract: An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal.

Abstract: An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

Abstract: In a heterojunction FET in which source and drain areas are formed by carrying out high temperature annealing process after carrying out ion implantation in areas to be formed into source and drain areas, conventionally, the N-type carrier supply layer and the N-type active layer are doped with Si. In place of doping with Si, doping with Se or Te is adopted. Thereby, in high temperature annealing process for activating the ion implanted areas, which serves as source and drain areas, unlike the Si donor, inactivation of donor due to reaction with F-atoms occurs scarcely with respect to the diffusion of F-atoms on the surface of the epitaxial substrate, which adhered during the process. Further, since the Se and Te are impurities from VI-family, when the Se or Te occupies any grid position of atoms from III-family or V-family, the Se or Te serves as the donor. Accordingly, a high performance heterojunction FET of little deterioration of the FET characteristics can be obtained.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A semiconductor light emitting device is formed by adhering a semiconductor layered portion having a light emitting layer forming portion to a conductive substrate via a metal layer. The metal layer has at least a first metal layer for ohmic contact with the semiconductor layered portion, a second metal layer made of Ag, and a third metal layer made of a metal which allows adhesion to the conductive substrate at a low temperature. As a result, the rate of reflection of light from the metal layer increases due to the presence of Ag in the metal layer. Further, the metal in the metal layer is prohibited from diffusing into the semiconductor layer, so that the semiconductor layer does not absorb light. And therefore the brightness of the semiconductor light emitting device can further be increased.

Abstract: A semiconductor memory device, which can hides a delay in a refresh operation from an outside for speeding up operation, comprises a memory cell including first and second transistors connected between a bit line for a write system and a bit line for a read system, and a capacitor C for data storage, in which a word line for a write system and a word line for a read system are connected to control terminals of the two transistors, respectively, a circuit for comparing a refresh address with an address selected according to a read/write signal among read/write addresses from an address holding circuit for holding input address signal and performing control so that if a mismatch is detected, a read/write operation using one of the read and write systems, selected by the read or write address and a refresh operation using the other of the read and write systems, selected by the refresh address are performed in parallel and if a match has been detected, the read or write operation using the word line and the bit

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: Bit lines are arranged with minimum width and minimum space in a chip, and each bit line is given a maximum of first potential difference. The minimum space is the value which will not make a line short-circuit in a line due to dielectric strength, when the first potential difference is applied across the bit lines. This value may be the design rule or the minimum dimensions capable of being processed by lithography. A second potential difference lager than the first potential difference is applied across a shielded power line and the bit lines. The shielded power line is not adjacent to the bit lines in the wiring width direction in the area where the bit lines are arranged with the minimum space.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a substrate on which field oxide layers are formed for isolating unit cells, a floating gate dielectric layer formed between the adjacent field oxide layers, wherein the floating gate dielectric layer includes a first dielectric layer and a second dielectric layer which are connected in parallel between a source and a drain formed on the substrate, and the thickness of the first dielectric layer is thicker than the second dielectric layer, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate; and a control gate formed on the control gate dielectric layer.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Abstract: The present invention provides a method for manufacturing a semiconductor device, an associated method for manufacturing an integrated circuit, and an LDMOS device manufactured in accordance with the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, may include depositing a layer of photoresist material over a substrate and creating an active device opening having sidewall angles associated therewith through the photoresist material. Additionally, the method may include forming a dummy opening through the photoresist material, wherein the dummy opening is located proximate the active device opening to reduce a shrinkage of the photoresist between the dummy opening and the active device opening and thereby inhibit nonuniform distortion of the sidewall angles.

Abstract: A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: An image sensor pixel has variable conversion gain to prevent overexposure of the pixel without reducing the exposure period. Under dim lighting conditions, the pixel operates with high conversion gain and is highly sensitive to light. When the incident light is bright, the pixel switches into a low conversion gain, low-sensitivity mode. The variable conversion gain is implemented by connecting a variable capacitive load in parallel with the photodiode of the image sensor pixel. When the incident light intensity exceeds a certain threshold, the variable capacitive load is increased to allow the photodiode to absorb more light. Likewise, the variable capacitive load is decreased when the incident light intensity is below a certain threshold.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: A semiconductor device has a plurality of capacitors. The semiconductor device includes a first capacitor arranged on a substrate and including first upper and lower electrode layers between which a first capacitor insulation film is interposed, and a second capacitor arranged on the substrate and including second upper and lower electrode layers between which a second capacitor insulation film is interposed, the second upper and lower electrode layers having a same structure as that of the first upper and lower electrode layers, and the second capacitor having a per-unit-area capacity different from that of the first capacitor.

Abstract: A semiconductor device has a capacitor including a storage node as a pair of electrodes isolated from each other by a capacitor dielectric layer and a cell plate, and includes a first contact and interlayer insulation layers formed on the first contact and having holes reaching the first contact. Hole and holes have diameters different from each other, and the diameters discontinuously change on a boundary between hole and holes. Further, the storage node is formed along inner wall surfaces of holes and is electrically connected to the first contact. With this, in the semiconductor device having a capacitor, a capacitor capacity can increase while stably ensuring an electrical connection of a capacitor lower electrode.

Abstract: In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

Abstract: A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.

Abstract: A polysilicon self-alignment contact and a polysilicon common source line. A cell array formed on a semiconductor substrate has a second cell adjacent to a first cell in a Y-axis orientation, and a third cell adjacent to the first cell in an X-axis orientation. Each cell comprises a first gate structure and a second gate structure, a source region formed in the semiconductor substrate adjacent to the first gate structure and the second gate structure, and an opening formed between the first gate structure and the second gate structure to expose the source region. A drain region is formed in the semiconductor substrate adjacent to the second gate structure of the first cell and the first gate structure of the second cell. A contact hole is formed between the first cell and the second cell to expose the drain region. A polysilicon layer is formed in the contact hole to serve as a polysilicon self-aligned contact.

Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Abstract: A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions arranged in a first direction of the memory cell array with a channel substrate region therebetween, and a gate structure arranged above the channel substrate region. The source/drain regions and channel substrate regions are formed in a substrate arranged on an insulating layer, with the channel substrate regions of memory transistors adjacent each other in the first direction being separated from each other by respective source/drain regions extending down to the insulating layer. The source/drain regions and the channel substrate regions of memory transistors adjacent each other in a second direction of the memory cell array furthermore are isolated from each other by trenches filled with insulating material and formed in the substrate so as to extend down to the insulating layer.

Abstract: A non-volatile semiconductor memory device has, at a main surface of a semiconductor substrate, an uneven shape with recesses and protrusions repeated continuously and alternately and further includes a source diffusion layer region having a source region formed from an upper surface of each protrusion to the depth direction of the semiconductor substrate and a source diffusion layer interconnection formed from a bottom surface of the recess to the depth direction of the semiconductor substrate when the semiconductor substrate is viewed two-dimensionally. The depth of the bottom surface of the source region from the upper surface of the protrusion is made equal to or larger than the depth of the bottom surface of the recess from the upper surface of the protrusion. Thus, a non-volatile semiconductor memory device is provided which is suitable for miniaturization and in which resistance of the source diffusion layer region can easily be lowered.

Abstract: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

Abstract: The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.

Abstract: A memory cell has a trench, in which a trench capacitor is disposed. Furthermore a vertical transistor is formed in the trench above the trench capacitor. A barrier layer is disposed for the electric connection of the conductive trench filling to a lower doping region of the vertical transistor. The barrier layer is a diffusion barrier for dopants or impurities that are contained in the conductive trench filling.

Abstract: The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions 504b. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity 510 of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: A light emitting layer made of a group III-V nitride semiconductor is formed between a first semiconductor layer made of an n-type group III-V nitride semiconductor and a second semiconductor layer made of a p-type group III-V nitride semiconductor. In side portions of the second semiconductor layer, oxidized regions are formed through the oxidization of the second semiconductor layer itself so as to be spaced apart from each other in the direction parallel to the plane of the light emitting layer. A p-side electrode is formed across the entire upper surface of the second semiconductor layer including the oxidized regions, and an n-side electrode is formed on one surface of the first semiconductor layer that is away from the second semiconductor layer.

Abstract: A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.

Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, an SOI film disposed on the insulating layer, a gate insulator disposed on the SOI film, and a gate electrode disposed on the gate insulator. A source, a drain, and a channel are formed in the SOI film so that the gate insulator is located at least between the channel and the gate electrode, thereby forming a MOSFET including the source, the drain, the channel, the gate electrode, and the gate insulator. The gate electrode is made of P-type polysilicon doped with P-type impurities such as boron. Further, the channel is doped with N-type impurities such as arsenic or phosphorus.

Abstract: An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The transistor further includes a gate insulating film that has a thin oxide silicon film (a thin film portion) and a LOCOS film (a thick film portion). The body region has an impurity profile in which the concentration reaches a maximum value near the surface and decreases with distance from the surface. The drain offset region has an impurity profile that has an impurity-concentration peak in a deep portion located a certain depth-extent below the lower face of the LOCOS film.

Abstract: There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions (12) are formed in one P-type semiconductor substrate (11). The N-type deep well regions (12, 12) are electrically isolated by the P-type semiconductor substrate (11). Over the N-type deep well regions (12), a P-type deep well region (13) and a P-type shallow well region (15) are formed to fabricate an N-type substrate variable-bias transistor (26). Over the N-type deep well region (12), an N-type shallow well region (14) is formed to fabricate a P-type substrate variable-bias transistor (25). Further a P-type DTMOS (28) and an N-type DTMOD (27) are fabricated.

Abstract: The present invention provides an alloy system as metal gate material of MOSFET devices that can solve the issue of work function incompatibility of metal gate and then can achieve low threshold voltage of surface channel MOSFETs effectively to satisfy the requirement of low voltage and high performance operation. To achieve this purpose, a chemically inert and thermally stable element, platinum (Pt), with high work function is selected as the basic component, which is doped with low work function element, such as tantalum (Ta), or titanium (Ti) to various atomic ratios. The work function can be adjusted to arbitrary value depends on the atomic ratio of element.

Abstract: A complementary integrated circuit comprises: an n-channel element having a gate electrode in which at least a portion contacting a gate insulating film is made of a first metal material having a work function close to the work function of n-type polysilicon; and a p-channel element having a gate electrode in which at least a portion contacting a gate insulating film is made of a second metal material having a work function close to the work function of p-type polysilicon. Preferably, the first metal material consists of a material selected from a group consisting of zirconium and hafnium, and the second metal material consists of a material selected from a group consisting of platinum silicide, iridium silicide, cobalt, nickel, rhodium, palladium, rhenium and gold. Alternatively, the first metal material may consist of a material selected from a group consisting of zirconium and hafnium, and the second metal material may consist of rhenium.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that is spaced apart from the first insulating layer. A lightly doped source/drain region is formed in the surface portions of the substrate between the second insulating layer and the gate structure. A source/drain extension layer are formed on the lightly doped source/drain region. A heavily doped source/drain region is formed on the second insulating layer so as to connect with the source/drain extension layer. The short channel effect is suppressed and the source/drain junction capacitance is reduced.

Abstract: A micromechanical component is described which includes a substrate (1); a monocrystalline layer (10), which is provided above the substrate (1) and which has a membrane area (10a); a cavity (50) that is provided underneath the membrane area (10a); and one or more porous areas (150; 150′), which are provided inside the monocrystalline layer (10) and which have a doping (n+; p+) that is higher than that of the surrounding layer (10).

Abstract: An image sensor is disclosed that has a concave micro-lens structure. The image sensor includes a plurality of pixels formed in a semiconductor substrate, each pixel including a light sensitive element. Further, a base material having a first index of refraction is formed over the pixels. Micro-lens cavities are formed in the base material over the light sensitive elements, the micro-lens cavity having a concave shape. Finally, color filters are formed into the micro-lens cavities, the color filters having a second index of refraction that is higher than the first index of refraction.

Abstract: An image sensor is disclosed that has a concave micro-lens structure. The image sensor includes a plurality of pixels formed in a semiconductor substrate, each pixel including a light sensitive element. Further, a base material having a first index of refraction is formed over the pixels. Micro-lens cavities are formed in the base material over the light sensitive elements, the micro-lens cavity having a concave shape. Finally, a filler material is formed into the micro-lens cavities, the filler material having a second index of refraction that is higher than the first index of refraction.

Abstract: A method of forming a base for a color filter layer of an image sensor is disclosed. The image sensor includes an array of pixels formed in a substrate. The method comprises depositing a polymer layer over the substrate. The polymer layer is patterned to form gaps in the polymer layer, the gaps located between the pixels. Finally, a second polymer layer is deposited into the gaps.

Abstract: An image sensor comprising a plurality of pixels formed in a semiconductor substrate, each pixel including a light sensitive element, and a color filter material formed over the light sensitive element, the color filter material formed in a micro-lens shape.