Patents Issued in April 29, 2004
  • Publication number: 20040080009
    Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Gurtej S. Sandhu, Zhiping Yin
  • Publication number: 20040080010
    Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
    Type: Application
    Filed: May 20, 2003
    Publication date: April 29, 2004
    Applicant: Cree Lighting Company
    Inventors: Primit Parikh, Umesh Mishra
  • Publication number: 20040080011
    Abstract: This disclosure describes one-chip micro-integrated optoelectronic sensors and methods for fabricating and using the same. The sensors may include an optical emission source, optical filter and a photodetector fabricated on the same transparent substrate using the same technological processes. Optical emission may occur when a bias voltage is applied across a metal-insulator-semiconductor Schottky contact or a p-n junction. The photodetector may be a Schottky contact or a p-n junction in a semiconductor. Some sensors can be fabricated on optically transparent substrate and employ back-side illumination. In the other sensors provided, the substrate is not transparent and emission occurs from the edge of a p-n junction or through a transparent electrode. The sensors may be used to measure optical absorption, optical reflection, scattering or fluorescence.
    Type: Application
    Filed: August 18, 2003
    Publication date: April 29, 2004
    Applicant: UNIVERSITY OF HOUSTON
    Inventors: David Starikov, Igor Berishev, Abdelhak Bensaoula
  • Publication number: 20040080012
    Abstract: The present invention relates to a nonvolatile memory device having asymmetric source/drain regions and a fabricating method thereof. In the device, a first and second impurity regions are formed in a substrate, and are separated by a first channel region and a second channel region. A tunnel insulating layer, a charge storing layer, and a gate interlayer insulating layer is disposed on the substrate in the first channel region, with the gate interlayer insulating layer being extended over the substrate in the second channel region. A control gate is then disposed over the previously formed layers in both regions. The first channel region and the first impurity region are, respectively, wider than the second channel region and the second impurity region. Thus, the erase speed of the device can be increased in an erase operation, by allowing an increased hot-hole injection rate.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 29, 2004
    Inventor: Sung-Ho Kim
  • Publication number: 20040080013
    Abstract: In a chip-stack semiconductor device including multiple semiconductor chips vertically stacked on top of each other, each of the semiconductor chips includes multiple through electrodes connected to each other in regions inside of electrode pads derived from a device region, and each of the through electrodes links a front surface to a back surface of the semiconductor chip. This arrangement provides a chip-stack semiconductor device which can prevent the increase in the size of the device and resolve the difficulty of stacking multiple semiconductor chips on top of each other, both of which are the problems associated with the provision of a number of through electrodes.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 29, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshio Kimura, Yoshihisa Dotta
  • Publication number: 20040080014
    Abstract: Disclosed are a transistor in the semiconductor device and method of fabricating the same. A gate oxide film is formed using a nitrification oxide film in a low voltage device region and a gate oxide film is formed to have a stack structure of a nitrification oxide film/oxide film/nitrification oxide film in a high voltage device region. An electrical thickness by an increased dielectric constant could be reduced even when a physical thickness of the gate oxide film is increased. The leakage current and diffusion and infiltration of a dopant into the gate oxide film or the channel region could be prevented. Furthermore, an electrical characteristic of the device could be improved by reducing the leakage current.
    Type: Application
    Filed: July 9, 2003
    Publication date: April 29, 2004
    Inventor: Doo Yeol Ryoo
  • Publication number: 20040080015
    Abstract: A contact configuration has an ohmic contact between a metalization layer and a semiconductor body of monocrystalline semiconductor material. An amorphous semiconductor layer is formed between the metalization layer and the monocrystalline semiconductor body. The layer is formed of the same semiconductor material as the body. The contact configuration is either produced by applying amorphous semiconductor material on the semiconductor body (e.g., sputtering, vapor deposition, glow discharge) or by damage formation in the semiconductor body.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 29, 2004
    Inventors: Anton Mauder, Hans-Joachim Schulze, Helmut Strack
  • Publication number: 20040080016
    Abstract: According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a first logic path. The first transistor has a first contact, a first gate length and a first contact to gate centerline spacing. The method also includes providing a second transistor in a second logic path. The second transistor has a second contact, a second gate length and a second contact to gate centerline spacing. The first contact to gate centerline spacing is substantially equal to the second contact to gate centerline spacing. The method also includes selecting a different gate length for the first gate length using a predetermined design criterion.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 29, 2004
    Inventor: Theodore W. Houston
  • Publication number: 20040080017
    Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 29, 2004
    Inventor: Jeng-Jye Shau
  • Publication number: 20040080018
    Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Sung Kim, Si-Young Choi, Jung-Woo Park, Jong-Ryol Ryu, Byeong-Chan Lee
  • Publication number: 20040080019
    Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Yong-Chul Oh, Gyo-Young Jin
  • Publication number: 20040080020
    Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.
    Type: Application
    Filed: December 8, 2003
    Publication date: April 29, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Mori, Mitsuhiro Noguchi
  • Publication number: 20040080021
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Publication number: 20040080022
    Abstract: On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a fuse region provided with a plurality of fuses is provided. The reflector layer of copper has a plane of reflection recessed downward to reflect a laser beam. The reflector layer of copper is arranged to overlap substantially the entirety of the fuse region, as seen in a plane. A laser beam radiated to blow the fuse can have a reduced effect on a vicinity of the fuse region. A semiconductor device reduced in size can be obtained.
    Type: Application
    Filed: February 28, 2003
    Publication date: April 29, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuhiro Ido, Kazushi Kono, Takeshi Iwamoto
  • Publication number: 20040080023
    Abstract: A conductive material such as silver is charged in a via hole of an insulative substrate made of low-temperature-sintered ceramic. A lower electrode, a dielectric layer, and an upper electrode are formed in a thin film on the insulative substrate. Thus a thin-film capacitor element is formed in which the capacitance value of the capacitor is specified by the overlapping part of the lower electrode and the upper electrode opposed through the dielectric layer. The dielectric layer is shaped like a ring with the via hole (conductive material) as the center and the part exposed inward from the inner periphery of the dielectric layer is served as a lead section of the lower electrode. The lead section is connected to a ground electrode on the back of the insulative substrate through the conductive material.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 29, 2004
    Applicant: Alps Electric Co., Ltd.
    Inventor: Kazuhiko Ueda
  • Publication number: 20040080024
    Abstract: A ball-limiting metallurgy stack is disclosed for an electrical device that contains at least one copper layer disposed upon a titanium adhesion metal layer. The ball-limiting metallurgy stack resists tin migration toward the upper metallization of the device. An etch process flow is also disclosed which resists the redepostion of the tin during etching of a copper layer.
    Type: Application
    Filed: October 24, 2002
    Publication date: April 29, 2004
    Applicant: Intel Corporation
    Inventor: Madhav Datta
  • Publication number: 20040080025
    Abstract: In a lead frame, a die-pad portion is defined for a semiconductor element to be mounted, a plurality of wire bonding portions are arranged along a periphery of the die-pad portion within a region to be finally divided as a semiconductor device for the die-pad portion, and a plurality of land-like external terminal portions are arranged in a region outside the wire bonding portions. Furthermore, a plurality of linear connection lead portions are formed to integrally join the wire bonding portions to the respective corresponding external terminal portions. The die-pad portion, the wire bonding portions, the external terminal portions and the connection lead portions are supported by an adhesive tape.
    Type: Application
    Filed: September 15, 2003
    Publication date: April 29, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tetsuichiro Kasahara, Akinobu Abe
  • Publication number: 20040080026
    Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 29, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masanori Minamio, Hiroshi Horiki, Tetsushi Nishio
  • Publication number: 20040080027
    Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned between bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured and corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Inventors: Ford B. Grigg, William J. Reeder
  • Publication number: 20040080028
    Abstract: A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the first electrode and a first terminal portion. A second lead frame includes a second connecting portion connected to the second electrode and a second terminal portion. The semiconductor chip is sealed by a housing. The housing is formed so as not to cover part of surfaces of the first and second connecting portions.
    Type: Application
    Filed: August 19, 2003
    Publication date: April 29, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi Yanagisawa
  • Publication number: 20040080029
    Abstract: An image sensor device includes a QFN type leadframe having a central die attach flag and an outer bonding pad area having a plurality of bonding pads. A sensor IC is attached to the flag. The IC has a first surface with an active area and a peripheral bonding pad area that includes bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the leadframe bonding pads, thereby electrically connecting the IC and the leadframe. Stud bumps are formed on the first surface of the IC and a transparent cover is disposed over the IC active area and resting on the stud bumps. The cover allows light to pass therethrough onto the IC active area. A mold compound is formed over the leadframe, wirebonds and a peripheral portion of the cover.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 29, 2004
    Inventors: Wai Wong Chow, Man Hon Cheng, Wai Keung Ho
  • Publication number: 20040080030
    Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.
    Type: Application
    Filed: December 5, 2003
    Publication date: April 29, 2004
    Inventors: Setho Sing Fee, Lim Thiam Chye
  • Publication number: 20040080031
    Abstract: A window-type ball grid array (WBGA) semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame has a plurality of leads encompassing an opening, each lead having an upper surface and an opposing lower surface. A resin material is pre-molded on the lower surfaces of the leads, with wire-bonding portions and ball-implanting portions defined on the leads being exposed. At least a chip is mounted on the upper surfaces of the leads and covers the opening, allowing the chip to be electrically connected to the wire-bonding portions of the leads by a plurality of bonding wires via the opening. Then, an encapsulant is formed to encapsulate the chip and fill into the opening for encapsulating the bonding wires. Finally, solder balls are implanted on the ball-implanting portions of the leads to complete fabrication of the semiconductor package.
    Type: Application
    Filed: February 27, 2003
    Publication date: April 29, 2004
    Applicant: Siliconware Precision Industries, Ltd., Taiwan
    Inventors: Chien Ping Huang, Chih-Ming Huang, Jui-Yu Chuang, Lien-Chi Chan
  • Publication number: 20040080032
    Abstract: The present invention aims to manufacture a large size semiconductor device with the inter-substrate transcription technology of thin film circuits. Enlargement is enabled by disposing a plurality of second substrates (21) in a tile shape. As the second substrate (21), a print substrate or flexible print circuit having double-sided wiring or multilayer wiring is employed. The plurality of second substrates (21) is driven independently, and the plurality of second substrates (21) is made to mutually overlap, and a drive circuit (23) is disposed at such overlapping portion. Moreover, the plurality of second substrates (21) is made to mutually overlap, and the mutual circuits are connected at such overlapping portion.
    Type: Application
    Filed: March 20, 2003
    Publication date: April 29, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mutsumi Kimura, Satoshi Inoue, Sumio Utsunomiya, Hiroyuki Hara, Wakao Miyazawa
  • Publication number: 20040080033
    Abstract: A flip chip assembly comprises an IC chip having a plurality of first solder bumps formed on a lower surface thereof and a heat sink having a plurality of second solder bumps, wherein the heat sink are attached to an upper surface of the IC chip via the second solder bumps. The present invention further provides a method for producing the flip chip assembly.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 29, 2004
    Applicant: Advanced Semiconductor Engineering Inc.
    Inventor: Jen Kuang Fang
  • Publication number: 20040080034
    Abstract: An area array semiconductor device is constituted of a circuit wiring substrate having a circuit wiring and a semiconductor chip mounted on the circuit wiring substrate and electrically connected with the circuit wiring. A sealing layer composed of a sealing resin is formed such that the sealing layer has an angle of 30° to 60° with respect to a side of the circuit wiring substrate.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Kunio Satomi, Yasushi Takeuchi
  • Publication number: 20040080035
    Abstract: The integrated electromechanical microstructure comprises a base substrate and a cavity closed by a protective cover. Means for adjusting the pressure in the cavity after the protective cover has been sealed comprise at least one element made of pyrotechnic material combustion whereof releases gas into the cavity. The pressure in the cavity can thus be adjusted independently from the sealing process. Selective ignition of the elements made of pyrotechnic material can be achieved by heating electrical resistors or by laser beams coming from outside the microstructure and directed selectively towards the elements made of pyrotechnic material through a transparent zone of the protective cover.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 29, 2004
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventor: Gilles Delapierre
  • Publication number: 20040080036
    Abstract: A system in package structure includes a first substrate, a first chip, a first heat-dissipating component, a second substrate, and a second chip. In this case, the first chip is formed on and electrically connected to the first substrate, and the first heat-dissipating component having a heat-conducting portion is formed above the first chip. The second chip is formed on and electrically connected to the second substrate. The second substrate is set above the first heat-dissipating component and electrically connected to the first substrate.
    Type: Application
    Filed: October 23, 2003
    Publication date: April 29, 2004
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ching-Hui Chang, Shih-Chang Lee, Wei-Chang Tai, Gwo-Liang Weng, Cheng-Yin Lee
  • Publication number: 20040080037
    Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Chee Seng Foong, Kok Wai Mui, Kim Heng Tan, Lan Chu Tan
  • Publication number: 20040080038
    Abstract: A ground shield for an integrated component device to prevent coupling between integrated capacitors and/or inductors and other integrated components. Components are formed upon a substrate. A conductive metal layer is formed or deposited thereon. The conductive metal layer is electrically connected to ground and an isolation layer is formed or deposited upon the conductive metal layer. An integrated capacitor, for example a MIM-type capacitor, is then formed upon the isolation layer. The grounded conductive metal layer absorbs electrical noise such that coupling between the capacitor and other components is prevented.
    Type: Application
    Filed: January 11, 2002
    Publication date: April 29, 2004
    Inventors: Lee Chew, Jonathon Y. Cheah
  • Publication number: 20040080039
    Abstract: This invention provides a newly designed coplanar line and an optical module or an electrical module using the coplanar line. The coplanar line comprises a signal transmission line and a pair of ground planes, each are arranged both sides of the signal transmission line. The coplanar line comprises three portions. The first portion has a relatively narrow width of the signal transmission line and the distance to the ground planes. The second portion has a relatively wider width of the signal transmission line and the distance to the ground planes, and the third portion smoothly connects the first portion to the second portion. The distance to the ground planes in the third portion has an exponential relation to the width of the signal transmission line thereof.
    Type: Application
    Filed: August 8, 2003
    Publication date: April 29, 2004
    Inventor: Yoshihisa Araya
  • Publication number: 20040080040
    Abstract: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 29, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihisa Dotta, Toshio Kimura
  • Publication number: 20040080041
    Abstract: A semiconductor device for an improved heatsink structure. The semiconductor device is composed of a first substrate, a first heatsink plate connected to the first substrate, a second substrate having a rear surfaces connected to the first heatsink plate, a semiconductor chip having a main surface bonded to a main surface of the second substrate, and a second heatsink plate connected to a rear surface of the semiconductor chip.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Publication number: 20040080042
    Abstract: In order to provide an improved heat transfer interface between an solid state device and a heat sink to which it is soldered, one or more “vents” are provided in the interface between the solid state device and the heat sink to prevent the entrapment of gases that could form solder voids. Advantageously, the provision of such vents in the interface surface geometry of the semiconductor may be effected by the use of appropriate masking and etching following the epitaxial regrowth process. Alternatively, the heat sink or a solder preform may be provided with suitable notches. The use of such “die-bond vents” also allows solder, after melting, to be forced under the chip by external gas pressure such that no solder voids are left.
    Type: Application
    Filed: October 24, 2002
    Publication date: April 29, 2004
    Inventors: Steven Henry Macomber, Jeffrey Powers
  • Publication number: 20040080043
    Abstract: A semiconductor device with reinforced under-support structure and a method for fabricating the semiconductor device are provided, which can be used in the packaging of an MPBGA/TFBGA (Multi-Package Ball Grid Array & Thin Fine-pitch Ball Grid Array) module to help reinforce the TFBGA under-support structure therein. The proposed chip-packaging method is characterized by the provision of large-area solder pads at the corners of a solder-pad array used for TFBGA attaching application, in order to form solder bumps of a large cross section and volume during reflow process to help reinforce the TFBGA under-package structure. This feature can reinforce the TFBGA under-package structure without having to use flip-chip underfill technology, and without having to use extra large type solder balls and arrange pads into different pitches as in the prior art.
    Type: Application
    Filed: May 19, 2003
    Publication date: April 29, 2004
    Applicant: Siliconware Precision Industries, Ltd.
    Inventors: Ho-Yi Tsai, Chin-Ming Shih, Ying-Ren Lin
  • Publication number: 20040080044
    Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.
    Type: Application
    Filed: July 30, 2003
    Publication date: April 29, 2004
    Inventors: Shinji Moriyama, Tomio Yamada
  • Publication number: 20040080045
    Abstract: A semiconductor device has multiple through electrodes with the same cross-sectional area extending through a semiconductor chip linking its front to back surface. The number of electrodes used is determined in accordance with the magnitude of the electric current for the same signal. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are readily capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 29, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshio Kimura, Yoshihisa Dotta
  • Publication number: 20040080046
    Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 29, 2004
    Inventors: Lee Choon Kuan, Chong Chin Hui, Lee Wang Lai
  • Publication number: 20040080047
    Abstract: In a semiconductor device of a structure comprising a thin semiconductor element bonded to a reinforcing plate with a bonding layer of a predetermined thickness, resin binder used for forming the bonding layer contains fillers including first filler, which has a diameter generally equal to a target thickness of the bonding layer to be adjusted to a value within a range of proper thickness (from 25 &mgr;m to 200 &mgr;m). This can maintain the bonding layer within the range of proper thickness when the semiconductor element is bonded to the plate, and ensure on-board mounting reliability of the semiconductor device.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Publication number: 20040080048
    Abstract: Disclosed herein is an anisotropically conductive sheet that exhibits conductivity in its thickness-wise direction, and is suitably used as a connector.
    Type: Application
    Filed: June 23, 2003
    Publication date: April 29, 2004
    Applicant: JSR CORPORATION
    Inventors: Yuichi Haruta, Naoshi Yasuda
  • Publication number: 20040080049
    Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Ccube Digital Co., Ltd.
    Inventor: Jong-Heon Kim
  • Publication number: 20040080050
    Abstract: A method for controlling a plasma etch process while etching a layer stack having a first layer disposed above an end-point generating layer is disclosed. The method includes etching through the first layer and at least partially through the end-point generating layer while monitoring an absorption rate of a light beam traversing an interior portion of the plasma processing chamber, wherein the end-point generating layer is selected from a material that produces a detectable change in the absorption rate when etched. The end-point generating layer is characterized by at least one of a first characteristic and a second characteristic. The first characteristic is an insufficient thickness to function as an etch stop layer, and the second characteristic is an insufficient selectivity to etchants employed to etch through the first layer to function as the etch stop layer. The method additionally includes generating an end-point signal upon detecting the detectable change.
    Type: Application
    Filed: March 27, 2003
    Publication date: April 29, 2004
    Applicant: Lam Research Corporation
    Inventors: Brian K, McMillin, Eric Hudson, Jeffrey Marks
  • Publication number: 20040080051
    Abstract: A semiconductor device includes: a silicon substrate having a main surface; an interlayer insulation film disposed on the main surface of the silicon substrate and having a top surface and a contact hole reaching the silicon substrate; a conductive film having a side surface and a top surface ranging from the side surface and filling the contact hole; a bottom electrode disposed in contact with the top and side surfaces of the conductive film; a dielectric film disposed on the bottom electrode; and a top electrode disposed on the dielectric film. The conductive film has its top surface more distant from the main surface of the silicon substrate than the interlayer insulation film has its top surface. The semiconductor device can be microfabricated and a desired capacitor structure can also be obtained to provide the semiconductor device with high reliability.
    Type: Application
    Filed: September 23, 2003
    Publication date: April 29, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Kenji Kawai
  • Publication number: 20040080052
    Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.
    Type: Application
    Filed: July 28, 2003
    Publication date: April 29, 2004
    Applicants: Advanced Semiconductor Engineering, Inc., ASE Material Inc.
    Inventors: In-De Ou, Chih-Pin Hung, Chia-Shang Chen, Kuang-Hua Lin, Shin-Hua Chao
  • Publication number: 20040080053
    Abstract: A structure is formed on a semiconductor wafer by forming a dielectric layer with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recessed area, where the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer. A metal layer is then formed to fill the recessed area and cover the non-recessed area and the plurality of dummy structures. The metal layer is then electropolished to expose the non-recessed area.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 29, 2004
    Inventors: Hui Wang, Peihaur Yih
  • Publication number: 20040080054
    Abstract: In a writing board wherein an opening is defined at a predetermined position of a film-like insulating substrate, an electric wiring provided with a connection terminal covering the opening is disposed on a principle plane of the insulating substrate, and a conductive member to be connected with the connection terminal of the electric wiring is disposed inside the opening; the conductive member having a thickness from a surface on which the electric wiring of the insulating substrate has been disposed is thinner than that of the insulating substrate.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Applicant: HITACHI CABLE, LTD.
    Inventors: Akira Chinda, Akira Matsuura
  • Publication number: 20040080055
    Abstract: An underfill material for attaching and underfilling a semiconductor component on a substrate includes a polymer base material, and electrically conductive particles in the polymer base material. The particles are configured to melt and rigidify bonded electrical connections between solder terminal contacts on the component and substrate contacts on the substrate. A size and concentration of the particles is selected to prevent electrical conductivity in X and Y directions. A method for attaching and underfilling the component on the substrate includes the steps of depositing the underfill material on the substrate or the component, placing the terminal contacts in contact with the substrate contacts while the underfill material is in a viscous or B-stage condition, bonding the terminal contacts to the substrate contacts to form the connections, and then curing the underfill material to form an underfill layer.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventor: Tongbi Jiang
  • Publication number: 20040080056
    Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. A flattened ball is attached to die contacts and a gold wire runs parallel to the die and then to a via on the substrate. The wire may be attached to the flattened ball by a wedge technique or other such known techniques. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 29, 2004
    Inventors: David Chong Sook Lim, Hun Kwang Lee, Howard Allen, Stephen Martin
  • Publication number: 20040080057
    Abstract: A conductive sash is etched around the periphery of a land grid array interconnection on a carrier for dense integrated circuit connections. If the array comprises more than one module or module chip domain, the conductive sash is also positioned between the modules. The dimensions of the sash are such that it is slightly larger than a frame of an interposer or other electrical connector which is placed upon the array. In this fashion, the interposer or other electrical connector rests upon the sash and provides protection against particulate and gaseous contamination of the array.
    Type: Application
    Filed: September 27, 2003
    Publication date: April 29, 2004
    Applicant: International Business Machine Corporation
    Inventor: Mark Kenneth Hoffmeyer
  • Publication number: 20040080058
    Abstract: A tamper resistant mixture adjustment screw arrangement for a carburetor. The arrangement includes a carburetor body having at least one air/fuel adjustment screw threaded therein. The adjustment screw has a threaded shank and a head portion. The head portion is defined by a smooth top surface and an undulant, uneven side surface capable of being engaged and mated by an adjusting tool having a complementary undulant, uneven side surface capable of being engaged and mated by an adjusting tool having a complementary undulant, uneven surface for initially adjusting the air/fuel mixture in the carburetor. A blocking curb extends from the carburetor body to a level which at least substantially corresponds to a projecting extent of each adjustment screw and being closely spaced to the screw head to prevent the screw from being turned by commonly available tools, but to permit the screw to be adjusted by the adjusting tool.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 29, 2004
    Applicant: Electrolux Home Products, Inc., A corporation of Delaware
    Inventors: Paul A. Warfel, Mike Wallace, Rodney W. Tynes, Tony Cochran, Jeffrey S. Franke