Abstract: A bracket assembly for connecting a fixture to a support, the bracket assembly comprising in combination a male subbracket for connection to one of the fixture or support, a female subbracket for connection to the other one of the fixture and the support, the subbrackets being complementarily configured for coupling to each other.

Abstract: An exterior rear view mirror assembly is disclosed which incorporates a bezel formed generally beneath the mirror housing. The bezel accommodates a rearward facing light source assembly to provide a rearward facing signal. The bezel may be integrally formed with the rear view mirror assembly or may be a separate component attached to the rear view mirror assembly.

Abstract: A wheel incorporating a flashing light feature includes a power source, a plurality of lighting elements and a flashing circuit to selectively provide lighting signals to the plurality of lighting elements. The wheel incorporating a flashing light feature further includes at least two motion switches to activate the flashing circuit. The at least two motion switches include a spring having a fixed end and a free end and a metal cap positioned proximate the free end of the spring for electrical engagement by the free end of the spring. Examples of articles with a wheel incorporating a flashing light feature include scooters, roller skates, in line skates, roller shoes and other types of wheeled footwear.

Abstract: Day travelling light, in particular for automotive vehicles, comprising a light source in an illumination housing and a means associated with the light source for bundling the light emitted by the light source, wherein the light source comprises at least one LED (13) (FIG. 1).

Abstract: The present invention is a headlamp and headlamp assembly that utilizes light emitting diodes as a light source. The light emitting diode headlamp and headlamp assembly effectively emanates white light and is capable of low beam and high beam functions. The light emitting diode headlamps comprise high-flux light emitting diodes, a reflector subassembly, and a first and second light transmissive member.

Abstract: In a headlamp apparatus comprising a sub-CPU integrally provided on a headlamp for controlling an optical axis direction changing operation and a main CPU for sending out to the sub-control circuit a control signal for changing the direction of the optical axis, the sub-CPU comprises a power-on resetting circuit of a simple configuration comprising a capacitor and a resistor. When the main CPU detects an abnormality in the sub-CPU, a power supply is temporarily cut off by a power supply control means, and the sub-CPU is reset by a power-on resetting circuit. An abnormality triggered by a runaway of the sub-CPU can be resolved so that the sub-CPU can be restored to a normal condition as quickly as possible.

Abstract: An eye grabber flashing LED store display adaptable to a standard store display peg is a flashing LED device to be used in stores to draw attention to the products the display is intended for. It uses an LED or LEDs, an electronic circuit, and an energy source such as batteries or solar panels or both. The invention is housed or secured by paper, polymer, composite, metal or other material and may optionally double as a sign displaying any means of graphics. The invention is adaptable to many store display methods including the standard peg display for carded products. The LED is preferably positioned either directly on the housing or at the tip of the peg the products hang on where it can be easily seen by anyone within the perimeter. A malleable wire LED light device and means of controlling lighting effects is a lighting device designed to provide white and/or colored illumination and lighting effects in and on various structures and machinery including tight places to reach.

Abstract: A voltage sense circuit and power supply regulation technique. In one aspect, a voltage sense circuit utilized in a power supply regulator includes a transformer including a sense winding and an output winding. A first diode is coupled to the sense winding, a first resistor is coupled to the first diode and a first capacitor coupled to the first resistor and the first diode. A second diode coupled to the first capacitor, the first resistor and the first diode. A second capacitor coupled to the second diode such that a voltage across the second capacitor is representative of a voltage across the output winding.

Abstract: An integrated circuit inverter controller that includes at least one input pin that is configured to receive two or more input signals. The input pin may be multiplexed so that the appropriate input signal is directed to appropriate circuitry within the controller to support two or more functions of the controller. Alternatively, the input signals may be present in differing time periods so that a single pin can support two or more functions. Multifunctional or multitasked pins reduce the overall pin count of the inverter controller.

Abstract: A high-voltage power supply (10) includes: a power scaling section (130) that receives an input voltage signal and converts the input voltage signal to a controllable DC voltage; a push-pull converter (140) for converting the controllable DC voltage to a high-frequency wave; and a voltage multiplier (200) receiving the high-frequency wave generated by the push-pull converter (140) and performing successive voltage doubling operations to generate a high-voltage DC output. In one implementation, the voltage multiplier (200) receives a square wave having a frequency of approximately 100 kHz and outputs an adjustable DC voltage of approximately 0-to-30 kV. In one implementation, the high-voltage power supply (10) includes an insulation system (250) for the voltage multiplier module (200), such an insulation system being formed of n insulating layers and m conducting strips positioned between successive insulating layers.

Abstract: A power supply apparatus, such as an uninterruptible power supply, includes an AC input configured to be coupled to an AC power source and an AC output. The apparatus also includes an AC/DC converter circuit, e.g., a boost rectifier circuit, with an input coupled to the AC input. The apparatus further includes a DC/AC converter circuit, e.g., an inverter circuit, configured to be coupled between an output of the AC/DC converter circuit and the AC output. A bypass circuit is operative to establish a coupling between the AC input to the AC output in a first (e.g., bypassed) state and to interrupt the coupling in a second (e.g., “on line”) state. The AC/DC converter circuit is operative to control current at the AC input when the bypass circuit is in the first state.

Abstract: The invention relates to a compensation circuit for the phase shift between a first input (3) for a voltage determination and a second input (4) for a current determination in electric meters for direct connection, whereby a DC-tolerant converter (5), for current transformation, is arranged before said second input (4) and a high pass filter (R1, C) is arranged before the first input (3), for a first equalisation of the non-frequency-dependant phase compensation. A further equalisation of the phase compensation occurs by means of a correction device (5) in a measuring chip (2), which is connected in series with the inputs (3, 4) for voltage determination and current determination.

Abstract: An alternator system having an alternating current voltage source includes a rectifier coupled to the voltage source, a sensor coupled to the voltage source and an engine and a control circuit coupled to the voltage source, the rectifier and the sensor. The control circuit provides control signals to the rectifier and the voltage source. The alternator system further includes a fault protection controller coupled to an output of the alternator system and coupled to the control circuit. The rectifier operates such that the alternator system provides a load match which results in output power levels which are relatively high compared with output power levels of conventional alternator systems and the fault protection controller operates under fault conditions (e.g. load dump), and overrides the other controllers in the alternator system based on output voltage when a load dump occurs.

Abstract: A switching power supply AC-DC-DC or AC-DC-AC with power factor corrector function is provided. The switching power supply circuit includes a quasi active shaping function that shapes an input current of a power line. In the whole system, the active switch or switches are only used to control the output power and no more current stress on the active switch or switches. It is possible to minimize the whole system size.

Abstract: A DC to DC converter having improved transient response, accuracy, and stability. The DC to DC converter includes a first comparator configured to compare a first signal with a second signal. The first signal has a DC offset determined, at least in part, by a DC reference voltage source. The second signal is representative of an output voltage level of the DC to DC converter. The comparator is further configured to provide a control signal to a driver based on a difference between the first signal and the second signal, the driver driving the output voltage of the DC to DC converter. The DC to DC converter further includes an accuracy circuit to enhance accuracy of the DC to DC converter. The DC to DC converter may further include a stability circuit to enhance stability of the DC to DC converter.

Abstract: Method and apparatus are disclosed for providing a constant voltage, high frequency sinusoidal output across a varying load, using either a single or multiple switch topology operating at constant frequency while maintaining high efficiency over the entire load range. This embodiment is especially suited to applications which require the sinusoidal voltage be held very close to a desired value in the presence of rapid changes in the conductance of the load, even in the sub-microsecond time domain as is common in computer applications and the like and in powering electronics equipment, especially a distributed system and especially a system wherein low voltage at high current is required.

Abstract: An integrated circuit inverter controller that includes at least one input pin that is configured to receive two or more input signals. The input pin may be multiplexed so that the appropriate input signal is directed to appropriate circuitry within the controller to support two or more functions of the controller. Alternatively, the input signals may be present in differing time periods so that a single pin can support two or more functions. Multifunctional or multitasked pins reduce the overall pin count of the inverter controller.

Abstract: An integrated circuit inverter controller that includes at least one input pin that is configured to receive two or more input signals. The input pin may be multiplexed so that the appropriate input signal is directed to appropriate circuitry within the controller to support two or more functions of the controller. Alternatively, the input signals may be present in differing time periods so that a single pin can support two or more functions. Multifunctional or multitasked pins reduce the overall pin count of the inverter controller.

Abstract: A power converter (10) adapted for receiving an AC input signal and a DC input signal and responsive thereto for providing a converted DC signal in which the converted DC signal has electrical characteristics which are selectable. The converter includes a programming circuitry (726) having a programmable memory (715) for storing a selection code, the programming circuitry (726) is cooperable for establishing the electrical characteristics of the converted DC signal based on the selection code.

Abstract: The invention includes a memory cell sensing system. The memory cell sensing system includes a plurality of memory cells located on a first plane of an integrated circuit. The system further includes a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane. Each sense amplifier is connectable to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell. The invention also includes a method of sensing a state of a selected memory cell within a plurality of memory cells. A plurality of the memory cells are located on a first plane of an integrated circuit. A plurality of sense amplifiers are located on a sense plane that is adjacent to the first plane. The method includes connecting a sense amplifier to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell.

Abstract: In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.

Abstract: A system-in-package (SiP) type semiconductor device has a test function capable of conducting a test singly on a memory chip directly from outside. When a mode signal included in a test signal input from an external connection terminal indicates a “normal operation mode”, a test circuit provided on a logic chip allows a logic circuit to use an access path (wiring) to a memory circuit. On the other hand, when the mode signal indicates a “test mode”, the test circuit uses the access path to access the memory circuit and conducts a test, an accelerated life test, or a multi-bit test, based on the content of the test signal input from the external connection terminal. The test circuit also conducts a built-in self-test.

Abstract: A device that includes a layer of material having particles dispersed therein, a first electrode on a first surface of the layer, and a second electrode on a second surface of the layer opposite the first surface. A state of the particles is changed when a prescribed voltage is applied across the first and second electrodes.

Abstract: A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.

Abstract: A semiconductor memory device includes a plurality of blocks, each of which includes a memory cell array, and outputs data signals and a redundancy signal. The semiconductor memory device further includes at least one first multiplexer which is coupled to the blocks, and selects one of the blocks, and a second multiplexer which performs redundancy processing based on the data signals and the redundancy signal which have undergone block selection by the first multiplexer.

Abstract: A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which selects writable and readable memory cells with the address selector circuit, conveys write signals to a memory cell selected by a write circuit, conveys read signals from a memory cell selected by a read circuit, and receives a clock signal, to generate operational timing signals to be conveyed to an address selector circuit, a write circuit and a read circuit, a circuit in which the operational timing is not too tight is configured of a higher threshold voltage MOSFET than the MOSFETs of other circuits.

Abstract: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A magnetic thin film element is provided with a magnetoresistive film including a first magnetic layer composed of a perpendicular magnetization film, a second magnetic layer composed of a perpendicular magnetization film having a higher coercive force than that of the first magnetic layer, and a nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. The resistance of the magnetoresistive film varies depending on whether or not the magnetic spins of the first magnetic layer and the second magnetic layer are in the same direction.

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.

Abstract: A multiple-level memory cell comprising: a memorization element formed of several polysilicon resistors associated in series between two input/output terminals; and a load in series with said resistive element, the midpoint of this series association forming a read terminal of the memory cell, and the respective junction points of said resistors of the memorization element being accessible.

Abstract: A magnetic memory of the present invention includes two or more memory layers and two or more tunnel layers that are stacked in the thickness direction of the layers. The two or more memory layers are connected electrically in series. A group of first layers includes at least one layer selected from the two or more memory layers. A group of second layers includes at least one layer selected from the two or more memory layers. A resistance change caused by magnetization reversal in the group of first layers differs from a resistance change caused by magnetization reversal in the group of second layers.

Abstract: In one embodiment, a memory device includes a plurality of magnetic data cells and a magnetic reference cell extending uninterrupted along more than one of the plurality of data cells.

Abstract: A magnetic memory device includes first and second magnetoresistance elements. The first and second magnetoresistance elements store information and are provided apart from each other in a first direction. A first wiring to apply a magnetic field to the first and second magnetoresistance elements is provided along the first direction. A first magnetic circuit is formed along a side of the first wiring and has a notch in its portion between the first and second magnetoresistance elements.

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

Abstract: On a given substrate are successively formed a buffer layer, a recording layer made of carrier induced ferromagnetic material, a metallic electrode layer via an insulating layer, to complete a nonvolatile solid-state magnetic memory as an electric field effect transistor. For recording, a first electric field is applied to the recording layer via the metallic electrode layer under a given external magnetic field, and then, a second electric field is applied to the recording layer via the metallic electrode layer so that the hole carrier concentration of the recording layer can be reduced lower than at the application of the first electric field, thereby to invert the magnetization of the recording layer and thus, realize recording operation for the recording layer.

Abstract: The present invention is a method and apparatus to program and/or to test a non-volatile memory cell to be programmed into a plurality of bit states (with each bit state having two states). More particularly, the method rapidly programs or tests such a cell by hard programming the cell when the cell is to be programmed into a state which permits the minimal amount of current t o flow in the channel. The charge pump integral with the memory device is capable of generating two types of pulses: a small incremental pulse, and a “hard” pulse, which is used only if the cell is to be programmed into the fully programmed state. For the states between fully programmed and fully erased, the incremental pulse is used to incrementally program the cell.

Abstract: A multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Third, a means of decoding an external address value in response to a write command such that the writing analog voltage is electrically coupled to the memory cell is included. Fourth, there is included a means of converting the memory cell analog voltage into an external data word value comprising one value of the set of at least three possible values corresponding to the memory cell analog voltage. Finally, a means of encoding the external address value in response to a read command such that the memory cell analog voltage is electrically coupled to the means of converting the memory cell analog voltage is used.

Abstract: The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.

Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.

Abstract: Data writing and reading methods and the implementation circuitry is revealed, in which two flash memories are connected to a data bus in parallel, and two data writing or reading signal lines are respectively electrically connected to each flash memory. The data writing or reading timings of flash memories are controlled by two non-overlapping data writing or reading signals, which may differ from each other by 180°, thereby data can be written into or read from the flash memory so as to increase the data writing and reading efficiencies.

Abstract: In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

Abstract: N-channel MOS transistors in a read gate circuit have respective sources connected to a sense amplifier activation line of a sense amplifier, not to a ground node. A read column selection line is selected prior to activation of the sense amplifier. Accordingly, paired read data lines are driven simultaneously with the activation of the sense amplifier.

Abstract: A process of repairing defects in linked list memories is disclosed. One of the linked list memories is selected as a defect marking memory and faults in rows of the defect marking memory are detected. Row addresses having at least one fault in defect address registers are stored; when at least one fault in the rows of the defect marking memory is detected. Faults in rows of other linked list memories are detected, where the other linked list memories are the linked list memories other than the defect marking memory and a marking code is stored for each row address of the other linked list memories in the defect marking memory, where a particular marking code indicates whether a particular row address has at least one fault. The defect address registers and the defect marking memory are searched when addresses of the linked list memories are linked and row addresses indicated as having at least one fault are skipped in the linking process.

Abstract: A method for identifying Serial Peripheral Interface (SPI) compatible serial interface memory devices. A microprocessor sends a single command requesting identification information to an SPI device installed on the SPI bus. A byte string, including the JEDEC manufacturer ID, device ID, and any extended device information, is sent back to the microprocessor. The byte string may include one or more continuation codes when the manufacturer ID exceeds 1 byte. The byte string also includes one byte indicating how many bytes of extended device information should be read by the microprocessor. The identification process, issuing the command and receiving the reply, is completed in one operation.

Abstract: A configurable circuit array that includes a matrix of cells, where each cell includes interconnected analog and/or digital circuit elements. The cells are fabricated on a common semiconductor substrate, and are electrically isolated from each other. The circuit elements in the cells are electrically coupled to circuit elements in other cells, and are electrically coupled to bonding pads by coaxial transmission lines capable of transmitting extremely high frequency signals. The transmission lines include a center conductor and first and second shield conductors, where the shield conductors prevent cross-talk interference. The transmission lines extend vertically from the substrate until they are a suitable distances above the circuit elements in the cell. From there, the transmission lines extend horizontally relative to the substrate to the opposite end connection point, where they again extend vertically down to the substrate.

Abstract: A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter holds the number of repetitions of a repeat sequence that is prescribed by the program. The up counter holds a PC value that is counted up for each clock pulse. The selector selects, as a PC value to be output next, the post-jump PC value or the value that is held by the up counter. The logic circuit refers to the output value of the program counter and the output values of the registers and the down counter, and generates a signal that instructs the selector what PC value should be selected as the next output value.