Abstract: The invention provides a content addressable memory device having the capability of functioning as a content addressable memory device with a reduced memory capacity even when the device includes a large number of failed words in some memory blocks.

Abstract: A semiconductor memory device comprising a redundancy circuit having a small area and high repair efficiency in which time required to store the address of a defect is short and which can reduce the manufacturing cost of the device is disclosed. Repairing addresses are sorted and stored in accordance with a specific order. In case of storing four addresses for eight addresses, a set SFG of fuses corresponding to eight decoded addresses DA0 to DA7 is provided and information indicative of the ordinal position of the fuse in the corresponding fuse-decision results which are logic 1 is used to associate the address with the repair-decision result.

Abstract: On a given substrate are successively formed a buffer layer, a recording layer made of carrier induced ferromagnetic material, a metallic electrode layer via an insulating layer, to complete a nonvolatile solid-state magnetic memory as an electric field effect transistor. For recording, a given electric field is applied to the recording layer via the metallic electrode layer so that the hole carrier concentration can be reduced to decrease the coercive force of the recording layer and thus, perform recording operation through the magnetic inversion of the recording layer with a relatively small external magnetic field.

Abstract: The present invention relates to all-optical OR and XOR logic elements employing saturable absorbers as optical gates. Saturable absorbers are arranged in paths of the Mach-Zehnder interferometer, respectively. If the total power of an input optical signal and a continuous wave signal is higher than a transparent input power of the saturable absorbers, the input optical signal passes through the saturable absorbers, and then the optical signals through the two paths are combined, so that it is possible to obtain the operational characteristics of the OR and XOR logic elements.

Abstract: Structures and methods for making a magnetic structure are discussed. Various embodiments increase a magnetic field to unambiguously select a magnetic memory cell structure. One method includes folding a current line into two portions around a magnetic memory cell structure. Each portion contributes its magnetic flux to increase the magnetic field to unambiguously select the magnetic memory cell structure. Another method increases the flux density by reducing a cross-sectional area of a portion of the current line, wherein the portion of the current line is adjacent to the to the magnetic memory cell structure.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

Abstract: A phase changeable memory device includes a substrate having a lower electrode disposed thereon. A phase changeable pattern is disposed on the lower electrode and an upper electrode is disposed on the phase changeable pattern that has a tip that extends therefrom and is directed toward the lower electrode.

Abstract: The invention relates to a content-addressable memory. An object of the invention is to make the content-addressable memory adaptable to various apparatuses and systems having different configurations without substantially altering the basic configuration thereof. The content-addressable memory includes a storage section having a plurality of storage areas for storing respective plural pieces of information; an ancillary storage section having a plurality of ancillary storage areas that correspond to the plurality of storage areas and store priority ranks that are assigned to the respective plurality of storage areas; and a controlling section for outputting, when at least one of the storage areas stores therein information matching with an externally supplied word, pointers of all or part of the at least one of the storage areas in descending order of priority ranks that are stored in ancillary storage areas corresponding to the at least one of storage areas.

Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

Abstract: A memory device which includes at least one bank having first and second unit blocks, each containing a plurality of cell arrays and first and second decoding units for decoding an inputted column address and outputting column selecting signals of the first and second unit blocks includes a column address transmitting unit, a first combining circuit, a second combining circuit, a first and a second output pads.

Abstract: In a mode entrance control circuit and a mode entering method to stably enter a semiconductor memory device into a predetermined operating mode only when insensitive to a change of a process, temperature, or voltage, etc., and simultaneously satisfying a constant entrance condition, the mode entrance control circuit includes an operation control part for generating an operation enable signal when a first voltage applied through a first pad is over a first determination voltage, a voltage division part for dividing a second voltage applied through a second pad to generate a trimming reference voltage, and a mode entrance signal generating part operated in response to the operation enable signal, for comparing a level of an applied fixed reference voltage with a level of the trimming reference voltage, and for generating a mode entrance enable signal to allow the semiconductor memory device to enter into a predetermined mode.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

Abstract: Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.

Abstract: A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.

Abstract: A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit. The memory cells are precharged when a precharge signal is enabled. The sense amplifier has an additional discharge path enabled by the disabled precharge signal to speed up reading data. The latch circuit is turn off by the enabled precharged signal to hold the data.

Abstract: Methods and apparatus for trimming a reference circuit. A representative technique includes transmitting a constant signal (e.g., a constant current or voltage). The constant signal is received (e.g., at a device pin or other contact). The constant signal is compared to a reference signal. Variables are obtained for program/erase pulses from a user. The reference circuit signal is adjusted to match the constant signal by sending program/erase pulses to the reference circuit. The program/erase pulses are set based on the variables for program/erase pulses and a result of comparing the constant signal with the reference signal.

Abstract: In a Vss precharge scheme, a dummy cell including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line is arranged in complementary bit lines respectively. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row active is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charges of the same amount are injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.

Abstract: An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.

Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.

Abstract: A method and circuit for optimizing power consumption and performance of driver circuits are described. More particularly, embodiments of the present invention provide an enhanced driver circuit. The enhanced driver circuit provides a first voltage, and a detector coupled to the enhanced driver that monitors the first voltage. If the first voltage falls below a predetermined value, the enhanced driver increases the first voltage to at least an optimal voltage.

Abstract: A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.

Abstract: A flash memory, and a flash memory access method and apparatus allowing memory access and error block recovery by creating a mapping table representing a physical address and status of a data block into a map block of the flash memory and referring to the mapping table. The flash memory includes a map block having a first mapping table containing a physical address allocated to each of blocks constituting a data block and status information of each of the blocks, a second mapping table containing mapping information between the physical address and a local address on each of the blocks in the first mapping table from which error blocks are excluded, and a third mapping table in which most recent mapping information is written and processed by a specified value to minimize an update operation of the second mapping table.

Abstract: A semiconductor memory has a memory cell array, a command decoder, and an input/output control circuit. The memory cell array has a plurality of memory cells which store data. The command decoder decodes a command input from outside. The input/output control circuit controls writing of data into the memory cell and an output of the data to the outside, in accordance with an output of the command decoder. If a write command is input in the command decoder, write data received from outside is written in the memory cell when two write commands are input in the command decoder subsequent to the write command.

Abstract: A method for evaluating and controlling a mixing process for polymer-based compounds includes the steps: obtaining initial starting conditions and values for viscosity dependent parameters; increasing batch temperature by a differential amount; calculating mixing parameters such as batch temperature, dispersion, viscosity, and torque based upon fundamental kinetic, thermodynamic, and Theological models; determining whether an endpoint or end points of one or more mixing parameters has been achieved; and changing one or more conditions so as to achieve the desired endpoint(s).

Abstract: The invention relates to a single screw extruder comprising a barrier screw and a barrel in which the barrier screw is held in a manner that permits to rotate and comprising at least one feed zone longitudinal section and at least one melting zone longitudinal section (23). The extruder (10) is characterized in that the barrel (11), on the inner wall (50) thereof in the area of the melting zone longitudinal section (23), has at least one groove (52) which runs in a longitudinal direction. The invention also relates to a method for extruding plastic material using a single screw extruder (10) comprising a barrier screw (40) which is held inside a cylinder (11) in a manner that permits it to rotate, whereby the extruder (10) comprises a feed zone (21, 22) and a melting zone (23), and the barrier screw (40) has at least one solid matter channel (49) and a melting channel (48).

Abstract: A combination static mixer and heat exchanger having heat exchanger tubes (1) which are provided over their circumference with fins (2a, 2b) which have a static mixing effect.

Abstract: The invention relates to a dynamic mixer for mixing at least two paste components of different volume proportions. Said mixer comprises a housing with at least two inlet openings and at least one outlet opening, a mixer element being rotatably mounted in a mixing chamber of said housing. The housing has at least one delay chamber comprising a limiting wall that blocks the paste stream in the direction of flow and at least one opening that opens into the mixing chamber, said opening(s) being set back in relation to the limiting wall. The mixer is particularly suitable for mixing paste components with a relatively high viscosity of, for example, greater than 800 Pas.

Abstract: A keyed paint container holder for paint mixers having a pivoting interlock key movable with respect to a paint container receptacle of the holder for orienting a rectangular footprint paint container to have a handle of the paint container in a corner of the holder adjacent the interlock key. The interlock key has first and second portions and is pivotable with respect to the holder to at least first and second positions and, optionally, to a third position. The holder accepts a cylindrical paint container as an alternative to the rectangular footprint paint container.

Abstract: A mixer of fluids, such as paint or resins, having a shaft capable of rotating about a longitudinally-extending, centerline axis of the shaft and at least one rotor assembly that is fixedly connected to and axially-aligned of the shaft. The shaft rotates about its centerline axis as well as each rotor assembly. Each rotor assembly consists of a plurality of spaced apart rotors. Each rotor has substantially uniform upper and lower surfaces and generally smooth and uniform edges. In preferred form, each rotor is a smooth disk that may be flat, wavy, concave, convex, dimpled, or tilted in shape.

Abstract: A method and apparatus suitable for coupling seismic or other downhole sensors to a borehole wall in high temperature and pressure environments. In one embodiment, one or more metal bellows mounted to a sensor module are inflated to clamp the sensor module within the borehole and couple an associated seismic sensor to a borehole wall. Once the sensing operation is complete, the bellows are deflated and the sensor module is unclamped by deflation of the metal bellows. In a further embodiment, a magnetic drive pump in a pump module is used to supply fluid pressure for inflating the metal bellows using borehole fluid or fluid from a reservoir. The pump includes a magnetic drive motor configured with a rotor assembly to be exposed to borehole fluid pressure including a rotatable armature for driving an impeller and an associated coil under control of electronics isolated from borehole pressure.

Abstract: There is described a micromachined ultrasonic transducers (MUTS) and a method of fabrication. The membranes of the transducers are fusion bonded to cavities to form cells. The membranes are formed on a wafer of sacrificial material. This permits handling for fusions bonding. The sacrificial material is then removed to leave the membrane. Membranes of silicon, silicon nitride, etc. can be formed on the sacrificial material. Also described are cMUTs, pMUTs and mMUTs.

Abstract: A photo-timer module, comprising: a upper cover which has a hollow window; a lower cover which could affix to said upper cover; a control and power circuit which is placed into said upper cover, wherein a portion of said control and power circuit is revealed in said hollow window, said control and power circuit has a plurality of input pins and a plurality of output pins wherein the plurality of input pins and the plurality of output pins are stretching out of said lower cover; a mask plate placing above said hollow window comprises at lease one hole thereon, so that a portion of said control and power circuit is revealed in said hollow window, and a transparent plate placing above said mask plate is used for protecting and convenient observing said control and power circuit; after assembly, said control and power circuit could control a power on or off by sensing variation of a light and show the status on said hollow window.

Abstract: A timepiece includes a reference wheel and one or more target wheels to be detected and corrected to the correct or standard time. The target wheels each includes a number of binary codes angularly spaced from each other, and each having a number of digits radially spaced from each other. The reference wheel includes a number of orifices angularly and radially spaced from each other, for moving over the digits of the binary codes and for determining the positions of the wheels by moving the orifices of the reference wheel relative to the digits of the binary codes.

Abstract: An assembly and method for recording and/or reading high-density data includes a phase change media, an antenna placed adjacent the phase change media, and a source of electromagnetic radiation.

Abstract: A near-field optical probe and optical near-field generator are provided. A problem of a probe having a scatterer in which optical near-field noises are generated at the parts other than for a point at which an intense optical near-field is generated, is solved. In one example of the probe, a surface of the parts except for a vertex of the scatterer at which the intense optical near-field is generated is etched so that an etching depth becomes not less than a penetration depth of the optical near-field. The probe facilitates control of noises when a sample is observed or recording marks are reproduced.

Abstract: The present invention provides an information processing unit with improved operability. A reading section (10) reads information recorded in an optical disk, and outputs a read signal. A DSP (20) detects the read signal and processes to a reproducible form. A quick return button selects at least one of the processing details for starting or stopping the information processing and for changing a reproducing position of the information. When a reproducing state changing section (120) recognizes a change instruction for changing a processing state for the information, a reproduction control section (52) changes the processing state by the DSP 20 based on the processing details selected with the quick return button.

Abstract: The rewriting counts in respective areas of a rewritable medium are uniformized. If empty areas are present on the rewritable medium rearward of a recording start position in terms of addresses, then data is recorded in those empty areas. When no empty areas become available rearward of the recording start position, data is then recorded in empty areas forward of the recording start position. The numbers of times that data is recorded in recording areas of the recording medium are thus averaged.

Abstract: A tape-shaped switch (500) is provided on a base part (410). Coil springs (460) support a ring-shaped rotational drive section (450) on the position opposed to the switch (500), biasing the same away from the base part (410), so that that the rotational drive section (450) may move toward and from the base part (410). First buffers are provided in association with the switches (501) of the tape-shaped switch (500), respectively. A flange (313) extends outward from the disc-shaped table plate (311) of a jog table unit (310) and is mounted on the rotational drive section (450). When the user depresses the jog table unit (310), moving the same downward, at least one of the switches (501) is closed. The motion of the jot table unit (310) is reliably detected because it is detected at a position outside that part of the jog table unit (310), which is depressed so that good feeling of the operation can be obtained.

Abstract: To make simple in structure and to still ensure precise disc loading, a disc loading-and-unloading structure for a disc apparatus comprises a drive motor, a drive roll assembly, a free-roll slider, a rotary lever, a slider, and link-and-spring connection means. The drive roll assembly has first and second drive rolls, an intervening transmission gear wheel, and a rotatable arm plate. The first drive roll is rotatably fixed to a stationary stud axle next to one end of the disc slot, and is connected to the drive motor. The first and second drive rolls are fixed to the opposite ends of the rotatable arm plate with the intervening transmission gear wheel sandwiched therebetween. The free-roll slider is next to the other end of the disc slot. The free-roll slider has first and second free rolls, and a slidable arm plate, and the first and second free rolls are fixed to the opposite ends of the slidable arm plate.

Abstract: Disclosed herein is an optical pickup unit and information recording and reproducing apparatus. The present invention provides an optical pickup unit which can store and maintain the characteristics of the optical pickup unit itself, and further provides an information recording and reproducing apparatus, which enables mass production without increasing costs even though optical pickup units having different characteristics are assembled, and enables maintenance to be easily performed without increasing costs. The optical pickup unit (10) of the present invention has an LD (11), an object lens (13) for focusing light emitted from the LD (11) on a disk, actuators (15 and 16) for driving the object lens (13) to vary the position of the object lens (13) relative to the disk, and a PD (14) for detecting light reflected from the disk. In addition, the optical pickup unit (10) has an EEPROM (18) for storing optical pickup information of the optical pickup unit (10) therein.

Abstract: Prior to recording/reproducing information to/from an optical disk rotationally driven by a spindle motor, an optical pickup is moved to a plurality of measuring positions set beforehand in a radial direction of the optical disk. A relative tilt between the optical disk and the optical pickup is detected with the spindle motor being rotated so that a linear velocity at each of the measuring positions equals a linear velocity upon actually recording or reproducing the information thereat. The tilt detected at each of the measuring positions is stored as tilt detection data corresponding to each of the measuring positions.

Abstract: A focus offset setting portion gives a predetermined quantity of offset to a focus control quantity used to reduce a focus error signal to zero based on the focus error signal generated by a focus error generation portion, and outputs a result. An adaptive equalizer including an adaptive control portion and an FIR filter subjects a reproduction signal RF provided from an optical pickup to waveform equalization based on a signal decoded by a Viterbi decoder. A controller obtains an optimum point of a focus offset by using a tap coefficient of the adaptive equalizer, and changes a set value of a focus offset setting portion.

Abstract: An optical disk in which tracks in which a header region at which positional information showing a recorded position is recorded and a user region at which user information is recorded are alternately arranged, and in which the user region is made to wobble in a direction perpendicular to the arranging direction are formed, and in which a first region in which at least one of a phase, a frequency, and an amplitude of a wobble is different from the other portions is formed at a portion a given length before the header region in playback order within the user region.

Abstract: An amplifier may include an output stage including first and second output transistors, and a biasing stage for generating first and second biasing voltages at control terminals of the first and second output transistors, respectively, based upon a supply voltage and an input signal of the amplifier. The amplifier may also include a clamping stage having first and second clamping transistors for clamping outputs of the first and second output transistors to upper and lower clamping voltages, respectively. Additionally, the amplifier may also advantageously include a saturation detector connected to the clamping stage for providing a saturation signal for at least one of (a) the output of the first output transistor being clamped to the upper clamping voltage, and (b) the output of the second output transistor being clamped to the lower clamping voltage.

Abstract: An optical head device includes a light source for emitting light; a collection optical system for collecting the light emitted by the light source to an information memory medium including at least one of a track having a mark or a space selectively arranged, and a track having a prescribed groove; a light detector having a plurality of detection areas for receiving the light reflected by the information memory medium and outputting a signal in accordance with a light amount of the light received; a division element for dividing the light reflected by the information memory medium and allowing the light to be received by the light detector; a switch element for receiving a first signal and a second signal, which are respectively obtained in accordance with the reflected light incident on a first prescribed area and a second prescribed area of the division element and outputting either one of the first signal or the second signal, the first and second prescribed areas being obtained by dividing the division e

Abstract: A mass memory storage device for reading data stored on a mass memory storage medium on which the data is stored at a substantially uniform density including a support arrangement configured to receive and support the medium. A drive arrangement is operatively connected to the support arrangement such that the drive arrangement rotates the medium at a substantially constant rotational speed when the device is operated in its intended way. A read head for reading the data stored on the medium is positioned adjacent to the medium with the read head being movable relative to the medium. A read channel arrangement for processing the data read by the read head is operatively connected to the read head. The read channel arrangement has a substantially continuously variable read channel data processing rate which varies according to the rate at which the read head reads the data from the medium. In a preferred embodiment, the device is a CD drive.

Abstract: An optical information recording medium of the present invention includes first to Nth recording layers (where N is an integer equal to or larger than 2) arranged sequentially from an opposite side of an incident side of a laser beam. The laser beam that has entered from one side is irradiated onto any one of the first to Nth recording layers, thereby recording and reproducing information. At least any one of the first to Nth recording layers includes a correction information recording portion. The correction information recording portion contains a correction information for correcting a laser beam intensity based on a change in a transmittance of the second to Nth recording layers between an unrecorded state and a recorded state.