Abstract: An Application Level Gateway (ALG) based on an universal parser, in a data transmission network. This ALG enables all data flow of an application level protocol to be checked for concordance with the formal syntax description of the data transmission protocol, and with a security policy. The ALG contains a transmission controller, universal parser, and at least one parser plug-in for each universal parser. This parser plug-in is specific to the data transmission protocol, and can be automatically created from the formal syntax description of a data transmission protocol. A security policy (rules, restrictions) can be implemented in the parser plug-in and/or in the settings.

Abstract: A network configuration (10) including a first network medium which is a 1394 network as well as a second network medium. Each of the first and second network media is coupled to a corresponding plurality of host computers (H1 through H3 and H5 through H7). The network configuration further includes a link layer gateway computer (H4) coupled to both the first network medium and the second network medium. The link layer gateway computer is operable to communicate a data packet from a source host computer selected from one of the plurality of host computers coupled to the first network medium to a destination host computer selected from one of the plurality of host computers coupled to the second network medium.

Abstract: A system and method for controlling queues by reducing the amount of redundant operations requested by commands associated with elements in the queue is provided. Control of queueing is provided by combining elements in the queue requesting redundant operations and eliminating those elements from the queue. Priority levels for each of the elements are also combined.

Abstract: Method for further processing data in a computer network.

Abstract: The invention discloses a method for calculating constrained paths for a transmission network. The method has the capability of automatic calculation of the shortest paths satisfying the SDH/SONET protection requirement, and can effectively reduce repeat computation times. The method comprises the steps of: collecting attribute information of the link to which each node is connected and obtaining the number of the protect entity to which the link belongs; flooding the collected information to other nodes according to a protocol; combining each node according to the numbers of the protection entities to which each link respectively belongs and forming the topology structure of each protection entity of whole network and related link attribute information; and calculating constrained paths for the transmission network. Since the protection topology is pre-calculated in this method, the repeat computation times can be effectively reduced and the constrained paths can be calculated in real time.

Abstract: Method of processing MPLS packets in a telecommunication equipment comprising the following steps in the following order:

Abstract: Methods, systems, and data structures are provided for dynamically routing a data packet through a Content Distribution Network (CDN). A routing table includes a desired path for a data packet and one or more alternative paths. Each path includes links and each link connects pairs of an entry node, intermediate nodes, and a destination node together. Each link also includes policies that are processed by the entry node and the intermediate nodes. If conditions of currently available nodes (local nodes) trigger one or more of the policies, then any processing node dynamically reorders a number of the currently available nodes within the routing table. After the processing, the data packet is routed to a next or preferred currently available node within the routing table.

Abstract: A system for managing attribute data provides reference characters to define attribute strings, and thereby provide compressed attribute data. The reference characters may be configured in a tree structure with the reference characters repeatable and configured in parallel resizeable arrays to define attribute data, for example, XML attribute tags. A translation table is provided for use in translating the reference characters associated with the attribute strings. A management server in connection with a user interface provides for management of network resources, including storage devices, associated with the attribute data. The storage devices may be configured to include logical units, with the reference characters repeated and used to represent redundant strings in the different logical units.

Abstract: A message processor accesses an electronic message. The message processor identifies from within the electronic message any schema-based time markers including time related message data associated with the message processor. The message processor determines if a schema-based time marker within the electronic message should be modified. This can include signing a portion of time related message data to indicate to a subsequent message processor that the time related message data can be trusted. The message processor routes the message (either directly or through one or more intermediary message processors) to a destination message processor. The destination message process receives the message and processes the electronic message according to time related message data included in the message. This can include trusting the portion time related data that was singed by the message processor.

Abstract: A communication node for enabling interworking of a first network in which data transfer is based on a combination of request and response and a second network in which data transfer is not based on a combination of request and response is disclosed. In the communication node, a packet conversion processing is applied to a first packet received by the first interface on the first network side so as to obtain a second packet corresponding to the second network at a time of executing an application across the first network and the second network, and a correspondence between the first packet and the second packet is stored in a packet correspondence memory. Then, a destination node on the first network to which a response packet is to be transferred is identified by referring to the packet correspondence memory using an information of the response packet at a time of receiving the response packet corresponding to the second packet by the second interface on the second network side.

Abstract: A method of an embodiment of the invention is disclosed that includes sending data from a computing device to an image-forming device server for output by the image-forming device. The image-forming device server compresses the data, and sends the data as compressed data to the image-forming device for output thereby.

Abstract: It is an object to provide a ring-shaped network which can speedily perform initialization even when a plurality of data transmission apparatuses, each performing multi-valued transmission while assigning one or more bits of data as one data symbol to a signal level, are connected thereto, and a data transmission apparatus.

Abstract: A method and system for performing network merge testing are disclosed. In one embodiment, the network merge testing method comprises: (i) gathering configuration information from at least two networks; (ii) comparing the configuration information; and (iii) displaying a report that indicates whether an attempted merge of the at least two networks would succeed. The report preferably identifies conflicts between the network configurations, and the method may further include automatic or guided resolution of the conflicts. The configuration information may include: zone names and memberships; domain and port names; security settings; inter-op modes; and long distance modes. A system for implementing the method is also disclosed herein. The system and method may advantageously prevent or diagnose causes of network segmentation.

Abstract: A method, program product and system for integrating user specific output options into an upload for a network service, the method comprising: obtaining information regarding user specific output options from an source that is not a part of the network service; and, incorporating the user specific output options into user interface data to be uploaded from a network service to a network service agent of the user. Another embodiment provides an implementation at the client side.

Abstract: A system and method for operating on data within a network device is described. Between two data operations in a network device is a FIFO queue, which is used to separate the clock domains of the data operations. Data from the first operation is stored in the FIFO queue, which signals an indication to the second operation that there is data in the queue. When the second operation is signaled that there is data in the FIFO queue, it immediately begins reading data from the queue, and begins performing its prescribed operations on the data once it has read enough data from the queue for it to begin operating.

Abstract: A multi-format card read/write optical disc drive comprises a micro-controller for processing actions between each component. The micro-controller is connected to a read/write drive, a multi-format card read/write controller, a data codec (coder/decoder), an analog interface transducer, and a computer interface controller. Through the read/write drive and the multi-format card read/write controller, read/write actions are performed to an optical disc and memory cards of various formats, respectively. The data codec is used to decode compressed media data and encode raw data for compression. The analog interface transducer-receives a digital data decoded by the data codec and then converts them into an analog signal for output. The computer interface controller is used to provide connection with a computer for performing bi-directional communications with the computer.

Abstract: A serial ATA control circuit is provided. The control circuit includes a plurality of serial ATA controllers, a plurality of port controlling circuits, a plurality of switch devices, and a switch controller. Each of the serial ATA controllers has a memory accessing controller and two transceivers. The serial ATA control circuit is connected to at least one serial ATA device through the port controlling circuits. The a plurality of port controlling circuits are connected to corresponding serial ATA controllers through the plurality of switch devices controlled by the switch controller. The connection path between each port controlling circuit and corresponding serial ATA controller is selected by the switch controller to achieve optimal data transfer rate.

Abstract: Provided are an integrated circuit device having two or more ports and a system for the device, where the device includes a first port for inputting and outputting data and a second port for inputting the data, and either the first port and/or the second port is selected by an external command when the data is input; the second port has ½n the number of pins of the first port, where n is a natural number; the device includes two or more ports that operate independently so that turn around time is reduced and the data bus efficiency of the integrated circuit device and the system are improved.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: A method for enabling a data processing system with a host running under an operating system and with a disk array storage device organized by logical devices to processes plural I/O requests from one or more host processors concurrently.

Abstract: A computer comprising a housing; a circuit board supported in the housing; a plurality of slot connectors supported on the circuit board; a first card configured for sliding receipt in one of the slot connectors; a processor mounted on the first card; a second card configured for sliding receipt in one of the slot connectors; a memory mounted on the second card; and an optical interconnect coupling the first card to the second card, the processor being configured to communicate with the memory via the optical interconnect. A method of assembling a computer, the method comprising supporting a circuit board in a housing; supporting a plurality of slot connectors on the circuit board; mounting a processor on a first card; inserting the first card into a first one of the slot connectors; mounting a memory on a second card; inserting the second card into a second one of the slot connectors; and optically coupling the first card to the second card for optical communications between the processor and the memory.

Abstract: A system is described herein where an embedded computer method for (‘router’) is provided for full-duplex (two-way) communication between devices and TCP/IP based networking. This system uses a process development component to configure communication between the router and devices. A controller is described that can manage device functions within a single router or among a collection of routers. This controller layer can be inside the router hardware or within the data-publishing layer. Each router is connected physically to devices using physical communication ports.

Abstract: Providing a method and a controller which readily performs a switchover of a dual-role device between a USB host and a USB device

Abstract: Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.

Abstract: In a device and method for controlling packet flow, priority data of a packet received by one of a plurality of ports are determined. A packet memory is monitored to determine whether an address pointer of the packet memory exceeds a predetermined limit value. A port is selected to control packet flow by using the priority data when the address pointer of the packet memory exceeds the predetermined limit value. Then, the selected port is directed to control the packet flow. By using the priority data designated to a packet or a port, the packet flow may be controlled in consideration of various kinds of network services.

Abstract: The invention transfers video data between a handheld computer and an external video device.

Abstract: Apparatus and methods for keyboard data normalization are disclosed. The example apparatus and methods convert physical location dependent keyboard data into keycap dependent data in a pre-boot environment.

Abstract: The present invention relates generally to a method and system for processing data. In a particular embodiment, the method includes receiving data to be processed from a network communication channel, storing the received data to be processed in memory based files at a computer memory that is local to and directly coupled to a processor via a high-speed memory bus, processing the received and stored data at the processor to produce processed data, compressing the processed data using a data compression software routine resident at the computer memory to produced processed and compressed data, and storing the processed and compressed data at a computer disk storage unit.

Abstract: Methods and associated structure operable within a SCSI-based storage subsystem are provided to adapt the storage controller for use with non-SCSI storage enclosures. A firmware layer of the present invention intercepts SCSI read/write requests and pass-through command blocks (CDBs) generated by the storage management core of the controller and translates the requests and command structures into corresponding command structures for transmission to a non-SCSI storage enclosure. In like manner, the firmware layer of the present invention receives status information from non-SCSI storage enclosures and translates the status information into corresponding SCSI compatible status information. In one exemplary preferred embodiment, a storage subsystem designed for interaction with SCSI storage enclosures may be adapted in accordance with the present invention to utilize lower-cost, IDE compatible storage enclosures.

Abstract: The present invention provides a smart hard-disk drive (sHDD). It can act as a host and directly communicate with multimedia devices. The sHDD offers true portability and provides a universal multimedia exchange platform (i.e. communicating directly with digital camera, mp3 player, camcorder, movie-playing device, etc.) The HDD integration breaks the traditional design barrier by integrating at least a portion of the HDD electronics onto the system motherboard.

Abstract: A drive assembly includes a carrier, a drive supported by the carrier, and an interface board. The tape drive includes a bus connector and a power connector. A plurality of cables are coupled to the bus connector and the power connector. The interface board includes an expander coupled to the cables and an external connector coupled to the expander. A storage array includes a backplane, a plurality of storage devices coupled to the backplane, a bus coupled to the storage devices, and at least one input/output connector coupled to the bus. Each storage device includes a carrier, a drive supported by the carrier, and an interface board. The drive includes a bus connector and a power connector. A plurality of cables are coupled to the bus connector and the power connector. The interface board includes an expander coupled to the cables and an external connector coupled to the expander.

Abstract: A method and apparatus for speculative response arbitration to improve system latency have been described.

Abstract: A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Abstract: Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

Abstract: In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effective, and at least one delay circuit generates one or more delayed interrupt request selection signals obtained by delaying the interrupt request selection signal by one or more delay times. Each of selection circuits selects either one of the interrupt request signals or the testing-purpose interrupt request signal based on the delayed interrupt request selection signal. The testing-purpose interrupt request signals output from the respective selection circuits at a different timing, can be sequentially input to the interrupt controller.

Abstract: When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Abstract: A system and method is provided for a computer network system to allow a device associated with a client-ID to be replaced without requiring the network system to reconfigure the client-ID information. The client-ID configuration information can be associated or tied to a slot or holder for a network device, rather than the network device itself. For example, the client-ID configuration information may be tied to an FRU holder, such as a Compact Peripheral Component Interconnect (CPCI) slot, and not the FRU itself. The client-ID configuration information is managed by a central resource. Accordingly, when the network device is replaced with a new device, the client-ID can be assigned from this central resource. The central resource may be a service processor or an alarm card. The service processor may access a storage device to retrieve the client-ID and transmit it to an FRU. Thus, when the FRU is replaced, this client-ID information is downloaded from the service processor by the new FRU.

Abstract: Substantial reduction or total elimination of switching transients (glitches) in an information handling system caused by inserting and/or removing hot-pluggable nodes having large power requirements is achieved with a plurality of power supplies having spare power capacity and being configurable into a main power source and an isolated power source. When insertion of a new hot-pluggable node is detected, this newly inserted node is powered from the isolated power source that is not coupled to the other existing operational nodes. When power to the new hot-pluggable node has stabilized and no longer has any detectable transients thereon, the new node is coupled to the main power source which powers the existing nodes of the information handling system. The isolated power source may thereafter be coupled to the main power source for added power supply redundancy. The new node may be detected and made part of or removed from the information handling system without being coupled to the main power source.

Abstract: A docking station may comprise first, second, and third ports. The first port may be connectable to a computer, the second port may be connectable to a digital imaging device, and the third port may be connectable to at least one peripheral device. The computer may function as a host for the peripheral device when the computer is connected to the first port. The digital imaging device may function as a host for the peripheral device when the computer is not connected to the first port and the digital imaging device is connected to the second port.

Abstract: A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.

Abstract: A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

Abstract: A USB cable connects to a USB connector in an electrical/electronic product and a USB connector in a separate type USB unit so that a USB controller and a conversion circuit are connected. The conversion circuit converts a USB signal into an external interface signal which is transmitted to and received from a peripheral device. The external interface signal is transmitted to and received from the peripheral device through an external interface connector. The minimum number of interface connector is selected from various external interface connectors through which the external interface signal is transmitted to and received from the peripheral device. By connecting expansion connectors 5 and 6 in a USB unit and those in another USB unit, the USB signal is transmitted and received between the USB unit and another USB unit.

Abstract: Machine-readable media, methods, and apparatus are described for flexibly establishing lanes of links. In some embodiments, any port of a device may be connected to another port of another device. Further, the device may determine interconnections of its ports to ports of other devices by issuing requests on its ports.

Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: A data storage device that includes an array of resistive memory cells and a circuit that is electrically connected to the array. The resistive memory cells include magnetic random access memory cells that are electrically connected to diodes. The circuit is capable of applying a first voltage to some of the resistive memory cells in the array, a second voltage to other cells in the array, and a third voltage to yet other cells in the array. Also, a method of sensing the resistance state of a selected resistive memory cell using the circuit.

Abstract: A memory controller is provided, which includes a request input for receiving successive memory access requests and a memory interface configured for coupling to a memory device having a plurality of banks. The memory controller has a bank control circuit, which generates a bank access command on the memory interface for a respective one of the banks in response to each memory access request to that bank. The bank control circuit has a plurality of selectable operating modes, including a Request Count Mode. When in the Request Count Mode, the bank control circuit generates a bank precharge command on the memory interface for the respective bank if none of a predetermined number of subsequent ones of the memory access requests is to that bank.

Abstract: A system and method for updating a binary image stored across a block-structured memory device, such as a flash memory device. From comparison of original and new images, an update package is generated which includes an encoded instruction set comprising COPY and ADD operations instructing the copying of source data from locations in the memory device and adding other data provided in the update package. The instruction set comprises SETBLOCK operations that direct updating of the memory blocks in an order that optimizes the COPY and ADD operations required and resulting update package size. The instruction set further comprises SETCOPYOFFSET operations to toggle between copy-offset modes thereby allowing for improved efficient encoding of COPY operations. The update package further includes an array of status bits corresponding to the memory blocks to be updated, thereby allowing for reliable restarting of the update process following power loss or other interruption.

Abstract: The present invention directly copies and constructs a partial inverse physical/logical address mapping table via a relation between a physical address and its corresponding logical address at the beginning of turning-on the system and storing the partial inverse physical/logical address mapping table (AMT) in a random access memory (RAM). Then, the function of the memory disk device, which is composed of a counter, a comparator or other hardware, is utilized to sequentially search the partial inverse physical/logical address mapping table (AMT) in a random access memory (RAM) until to obtain the corresponding physical address to the awaited-searching logical address. Hence, the present invention can obtain an effectively balance between the process speed and the space. The present invention does not occupy too much space on the premise of keeping fast processing speed.