Abstract: As a pre-processing step for transmitting a timecode, a checking information is retrieved from a LTC. A checking data is created using the retrieved checking information. The checking data is superimposed on a VITC.

Abstract: The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: The invention relates to a method and device for performing channel simulation, the device comprising a set of channel simulation units (200 to 214) for simulating a radio channel, each unit comprising radio frequency parts (200A to 214A) and baseband parts (200B to 214B). In the solution of the invention, the baseband parts of several different units (200 to 214) are arranged to simulate the same channel.

Abstract: A cell buffer with built-in testing mechanism is provided. The cell buffer provides the ability to measure voltage provided by a power cell. The testing mechanism provides the ability to test whether the cell buffer is functioning properly and thus providing an accurate voltage measurement. The testing mechanism includes a test signal provider to provide a test signal to the cell buffer. During normal operation, the test signal is disabled and the cell buffer operates normally. During testing, the test signal is enabled and changes the output of the cell buffer in a defined way. The change in the cell buffer output can then be monitored to determine if the cell buffer is functioning correctly. Specifically, if the voltage output of the cell buffer changes in a way that corresponds to the provided test signal, then the functioning of the cell buffer is confirmed. If the voltage output of the cell buffer does not change correctly, then the cell buffer is known not to be operating correctly.

Abstract: An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.

Abstract: A method and a configuration produce a fault signal that is suitable for identifying transmission faults when using differential signaling. A first mid-level signal whose potential is in the area of the mid-point between the signal level on a first signal line and a signal level on a second signal line, when a logic “1” is transmitted is compared with a second mid-level signal formed when a logic “0” is transmitted. The fault signal is produced if the discrepancy between the two mid-level signals is greater than a predetermined threshold value.

Abstract: A data storage medium which includes a link zone, an apparatus and a method of recording data, and an apparatus and a method of reproducing data. The data storage medium includes a plurality of ECC blocks in which user data are stored, and a plurality of link zones arranged among the ECC blocks so as to correspond to the ECC blocks, Additional information on the ECC blocks is recorded in the link zones.

Abstract: By applying additional error correction during transmission of any 8B/10B pattern without increasing the number of overhead bits, improved performance is possible, while still maintaining the other advantages of the 8B/10B code. In effect, a new “coding layer” is added wherein the 8B/10B encoded data goes through a low latency encoding process during transmission, and is regenerated by a complementary low latency decoding process during the receive process, to provide a coding gain of the code of about 5-6 dB (from about BER=le−5 to about BER=le−17) by detecting and correcting errors during transmission in the communication channel. Moreover, it is now possible to have an additional communication channel between both end stations with a side-band channel data rate of about 16 mbps. The original 8B/10B data stream data rate remains the same and the user gets the benefits of the error correction and additional communication channel without any bandwidth penalty.

Abstract: An apparatus for controlling a Hybrid Automatic Repeat Request (HARQ) is provided. In the apparatus, a physical layer includes a decoder for decoding a control message received over the packet data control channel, a demodulator for demodulating packet data received over the packet data channel, and a turbo decoder for decoding the demodulated packet data. A physical layer's HARQ controller determines whether to demodulate and decode the received packet data depending on a decoding result of the control message, outputs the decoded control message to the demodulator and the turbo decoder for demodulation and decoding of the received packet data, controls output of a response signal according to decoding result of the packet data, and delivers the turbo-decoded packet data to an upper layer.

Abstract: CIRC code decoding includes for each input frame a one-symbol delay operation of every second data symbol and the inversion of parity symbols, C1 word decoding, de-interleaving, C2 word decoding, and a two-symbol delay op-eration before output. The error correction capabilities can be improved if the C1 word decoding, de-interleaving and C2 word decoding are carried out twice (double pass operation) before the two-symbol delay operation and out-put. The invention allows double pass operation as well as sin-gle pass operation and uses a single memory with minimum capacity, wherein to three parts of the memory specific operations are assigned and wherein the memory is con-trolled in a special way.

Abstract: A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.

Abstract: An RF signal that is a disk reproduction signal is binarized through an equalizer and a slicer, followed by data demodulation, and an error rate of the reproduction signal is detected in an error detection circuit. If the error rate in the error detection circuit is higher than a prescribed value, a slice balance adjustment circuit performs slice balance adjustment for the slicer and a boost adjustment circuit performs boost adjustment for the equalizer.

Abstract: A method and an apparatus are provided for isolating faulty semiconductor devices in a multiple format graphics system. The apparatus includes a buffer adapted to receive at least one data stream in at least one of a plurality of formats and a convolver comprising at least one signature register, wherein the convolver is adapted to determine the format of the at least one data stream. The apparatus further includes a router adapted to route the data stream from the buffer to the convolver and an analyzer adapted to access the signature register, wherein the analyzer is capable of isolating at least one of a faulty semiconductor device and a faulty interconnect based upon the contents of the signature register and the determined format.

Abstract: The invention relates to a method for transmitting packet data (PDU) in a communications system (UMTS, GPRS) between a transmitter (BS; MS) and a receiver (MS; BS). The aim of the invention is to ensure correct processing of such packet data. To this end, the packet data (PDU) are repeatedly transmitted by the transmitter (BS; MS) and are received by the receiver (MS: BS) as data received earlier (x) or data received later (y). A diversity combination (MRC) of the data received earlier (x) and the data received later (y) is performed to reconstruct the transmitted data packet (PDU).

Abstract: The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

Abstract: A method of controlling the sending of data packets from a Base Station (BS) of a Radio Access Network (RAN) to a UE, where the BS is one of a set of BSs transmitting identical data to the UE and each said data packet has a sequence number. The method comprises implementing at the BS an Automatic Repetition reQuest (ARQ) mechanism for resending data packets erroneously received by the UE and, upon receipt of an ARQ status message from the UE, advancing a transmission window of the BS so that its lower region covers the packet having the highest sequence number for which an ARQ acknowledgement has nor yet been received. Where a single BS is transmitting in the downlink direction, and a soft handover set exists for an uplink reverse channel, downlink sending buffers of the BSs of the soft handover set may be synchronized by the exchange of ARQ messages between BSs.

Abstract: When an error is detected in a received header, in estimating reference information while assuming an error in a packet receiving interval, a header is decompressed using at least one value of another candidate sequence numbers used in correcting an erroneous sequence number, corresponding to a time that elapses between previously receiving a packet correctly and receiving a current packet and to the packet receiving internal. It is thereby possible to increase a possibility of estimating the reference information correctly and suppress the number of discarded packets at a receiving side, while suppressing increases in introduced processing amount in data transmission with header compression.

Abstract: When transmitting voice data, correction codes each representing data of one data packet are added to the transmitted data from the outset. Thus, it is made possible to restore one data packet lost for the first time, and when and only when two successive data packets are discarded, one packet data is lost. In this way, the data discarding endurance is improved.

Abstract: A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

Abstract: A method and apparatus are disclosed for MAP decoding of signals encoded using error correction codes to make maximum probability decisions about each transmitted bit. A disclosed MAP decoding algorithm extends the work of Hartman and Rudolph and exploits properties of Hamming error correction codes to provide a decoding algorithm having a complexity that is proportional to n log n for Hamming codes. The invention computes a difference, &rgr;, of the probabilities the that transmitted symbol was zero and one based on characteristics of the channel and then determines the product of the &rgr;l values corresponding to non-zero positions of codewords of the dual code using real vector and F2[2]-vector fast Walsh-Hadamard transforms. The invention also processes all positions of all codewords to determine a sum for each position that indicates the reliability that a received bit is a given value for a given position using the real vector fast Walsh-Hadamard transforms.

Abstract: Embodiments of a system and method for using mobile agents for collaborative content control in peer-to-peer networks. A peer may launch a mobile agent including an itinerary of peers to be visited and indications of one or more documents that the peers are collaboratively editing. The mobile agent may visit peers indicated by the itinerary to collect version information for the document(s). The mobile agent may return the version information to the initiating peer, which may coordinate each of the document(s) on the peer to a most recent version in accordance with the version information provided by the mobile agent. Visited peers may use the payload to determine if their version of the document(s) are up to date and, if not, may add a version update request to the payload. The initiating peer may send the most recent version information to peers that added version update requests to the payload.

Abstract: A system and method for processing extensible markup language (XML) documents over the World Wide Web via a remote server. In one aspect, the invention provides: a workspace management system for creating unique workspaces for each of a plurality of organizations; an XML editing system having a template editing system for editing XML templates, a content editing system for editing XML content, and a document collaboration system for controlling access to XML documents; a database for remotely storing XML documents for the plurality of organizations; and an application server for serving the workspace and XML editing system to clients via the World Wide Web. Also included is a system for publishing the XML documents stored in the database to a company's website or for publishing in a non-HTML format.

Abstract: The invention relates to a method for classifying information in a portable data processor, and a portable data processor. The method comprises: processing information based on commands obtained from a user interface in the portable data processor; associating information multi-dimensionally into at least two different categories according to information type and at least one other criterion; presenting the associations in the user interface and carrying out processing related to the associations based on the commands obtained from the user interface; and storing the associations for subsequent use.

Abstract: System for evaluating an information aggregate includes a metrics database for storing document indicia including document attributes, associated persons and time-stamped tracked activities; a query engine responsive to a user request and the metrics database for aggregating documents having same, unique attributes in an information aggregate; the query engine further for calculating recency value of the aggregate; and a visualization engine for visualizing recency values for a plurality of aggregates at a client display. Base recency, relative recency, cross-aggregate recency, and normalized cross-aggregate recency metrics are provided.

Abstract: Methods and apparatus for generating a report template for generation of a spreadsheet report are disclosed. First, a grid including a plurality of cells is displayed. One or more database fields for which data is to be obtained from a database are identified, where each of the database fields is associated with a separate group with which one or more rows in the grid can be associated. One or more groups as defined by the one or more database fields are then associated with a corresponding set of one or more rows in the grid, thereby associating cells within the set of rows with the corresponding group. A user may then enter information within one or more of the plurality of cells of the displayed grid, where the received information indicates at least one of a format of the spreadsheet report to be created and information to be displayed in one or more cells of the spreadsheet report.

Abstract: A system and method for parsing source code written in a high-level programming language at multiple levels may be performed to populate a tree data structure. To obtain information at lower levels, higher levels are be parsed. Each level of parsing is performed as a separate stage with the results of higher levels being used to feed parsing at lower levels. The system and method of the present invention provide for parsing at a requested level, not parsing to a lower level than requested.

Abstract: Methods, apparatus and systems to keep a desired element properly addressed in a structured document in which particular elements are addressed, even if the structured document is modified. In an example embodiment, the invention comprises a difference computation unit for computing a difference between structured documents, and an XPath update unit for generating addressing information from addressing information that addresses a part of a particular structured document based on information on the difference computed by the difference computation unit, the generated addressing information addressing a corresponding part of the other structured document.

Abstract: A system and method for copying formatting information between group editable Web pages is provided. The system includes a web server and devices, such as computers, which can communicate via a network. Users at the computers can access one or more of the Web pages and request that the accessed page's formatting information be copied over to one or more specified target Web pages. The Web server is configured to extract a first set of formatting information, such as HTML formatting templates, from a source web page displayed on one or more computers in the network. Further, the Web server replaces a corresponding second set of formatting information in the target Web page(s) with the first set of extracted formatting information.

Abstract: An image processing method which is used to confirm a layout when an image is formed onto a recording medium on the basis of an application. The method includes: an image forming step of forming the image based on the application; and a display control step of controlling a process for displaying the image so that a portion corresponding to the inside of the recording medium of the image formed in the image forming step and a portion corresponding to the outside of the recording medium can be discriminated.

Abstract: A request is transferred from a first information processing apparatus to a second one, and document data for printing is generated in accordance with the print request by a generating program provided in an image generating apparatus, and then the generated document data is transferred from the second information processing apparatus to the first one so that the document data is printed out. A type of input data or a type of output data processable by the generating program provided in the image generating apparatus is registered in the second information processing apparatus. A type of input data necessary to generate the document data and a type of the document data generated is specified in accordance with the print request. A generating program for generating the document data is selected by comparing the specified type to the registered type. A generating request for generating the document data is transferred to the image generating apparatus having the selected generating program.

Abstract: An image to be used as wallpaper of a mobile terminal can be processed easily. A catalog of image data sets stored in an image database is displayed on a terminal and one of the image data sets to be used as the wallpaper is selected. A model and a destination address of the mobile terminal to which a processed image data set is sent are input, and an image represented by the selected image data set is displayed on the terminal. An image area is displayed in the image, according to the model of the mobile terminal. A user of the terminal moves, reduces, or enlarges the image area for specifying an area in the image. The selected image data set is processed according to the specified area, and the processed image data set generated in this manner is sent to the destination address.

Abstract: The invention is generally directed to a method for selecting a font that uses a mark-up language document to group together multiple pre-existing fonts into a single font family or “virtual font.” The mark-up language document includes rules regarding the conditions under which individual fonts within the family are to be used. This permits, for example, a font developer to create, in an efficient manner, an international font using several preexisting fonts.

Abstract: In a mixed-loaded type semiconductor device including a plurality of MOS transistors having gate insulating films different in thickness, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than a predetermined thickness is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than the predetermined thickness. In particular, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than 2.6 nm allowing the tunneling of the electric charges to occur is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than 2.6 nm.

Abstract: A semiconductor device having first and second operation modes includes a signal line, first and second flip-flops, and a switching circuit. The signal line transmits an instruction signal in the second operation mode. The first flip-flop operates in synchronism with a clock in the first operation mode and the instruction signal in the second operation mode. The switching circuit propagates an input to the output of the first flip-flop in response to the instruction signal in the second operation mode. The second flip-flop operates in synchronism with the clock in the first operation mode, and in the second operation mode, selects a test pattern as an input signal instead of an input signal in the first operation mode, and operates in synchronism with the clock.

Abstract: Search functions of a physical layout tool are performed by converting a given physical layout name and selected searching layout names from string representations into numerical representations and comparing the converted numerical representation of the given physical layout name with the converted numerical representations of searching physical layout names until a match occurs. In one embodiment, metal and via layer numbers included in string representations of physical layout names are converted to integer values by selecting number characters from predetermined positions in a string, such as number characters that identify the metal or via layer.

Abstract: A methodology for determining the placement of decoupling capacitors in a power distribution system and system therefor is disclosed. In one embodiment, a method for determining the placement of decoupling capacitors in a power distribution system includes determining target impedance, creating a power distribution system model, performing an LC (inductive-capacitive) resonance analysis, and performing a cavity resonance analysis. During the performance of the LC resonance analysis, capacitors may be selected in order to suppress impedance peaks resulting from LC resonances. Following the LC resonance analysis, the method may place the capacitors in the power distribution system at evenly spaced intervals. During the performance of the cavity resonance analysis, the capacitors may be repositioned in the power distribution system so as to suppress cavity resonances.

Abstract: A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first timing path is identified in a first timing report corresponding to a first partition of a circuit. For at least one timing constraint applied to the first timing path, a second timing path in a second partition of the circuit that causes the timing constraint is determined. A second timing report comprising the first timing path from the first timing report and the second timing path from the second partition is generated.

Abstract: A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.

Abstract: A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.

Abstract: Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.

Abstract: An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into twp or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.

Abstract: A semiconductor integrated circuit includes a variable region to be subjected to a layout modification in conjunction with a change of a circuit component within the variable region; and a fixed region that is free from the layout modification, and includes a circuit such as a CPU core and peripheral functional section whose signal transfer characteristics are known when the circuit is considered as a closed circuit. It can reduce the manpower required for the layout modification and characteristic verification and evaluation of the circuit involved in the layout modification.

Abstract: The present invention pertains to a system and method for specifying links, connectivity and bandwidth in an interconnect fabric. For example, a method for allocating connectivity and bandwidth of an integrated circuit may include receiving an interconnect fabric description, the described interconnect fabric having a plurality of platforms linked over an isochronous interconnect fabric. An arrangement of links of the received interconnect fabric is virtualized based on bandwidth. An arrangement of links of the received interconnect fabric is virtualized based on connectivity. The links are allocated on the basis of the virtualized link arrangements based on bandwidth and connectivity.

Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph.

Abstract: A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.

Abstract: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Abstract: A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.

Abstract: A method for designing a logic circuit and a CAD program which allow a logic circuit with desired performance to be designed in a short period of time by suppressing the elongation of a logic design period for achieving a circuit area, an operating speed, power consumption, and the like as target specifications are provided at low cost. Shorter-period and lower-cost design is accomplished by allowing a user to use a high-performance logic synthesis CAD program at no charge if he only checks circuit characteristics resulting from synthesis and collecting a fee if the user is satisfied with the resulting circuit characteristics and intends to use a gate level logic circuit. In a design phase which receives a register transfer level or operation level logic circuit and synthesizes a gate level logic circuit, desired circuit characteristics are obtainable in a short period of time at low cost.